pci.c 7.7 KB

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  1. /*
  2. * PCI support code.
  3. * To do:
  4. * initialise bridge mappings if the PCI BIOS didn't.
  5. */
  6. #include "u.h"
  7. #include "../port/lib.h"
  8. #include "mem.h"
  9. #include "dat.h"
  10. #include "fns.h"
  11. #include "io.h"
  12. #include "../port/error.h"
  13. enum {
  14. MaxFNO = 7,
  15. MaxUBN = 255,
  16. };
  17. enum
  18. { /* command register */
  19. IOen = (1<<0),
  20. MEMen = (1<<1),
  21. MASen = (1<<2),
  22. MemWrInv = (1<<4),
  23. PErrEn = (1<<6),
  24. SErrEn = (1<<8),
  25. };
  26. static Lock pcicfglock;
  27. static Lock pcicfginitlock;
  28. static int pcicfgmode = -1;
  29. static int pcimaxdno;
  30. static Pcidev* pciroot;
  31. static Pcidev* pcilist;
  32. static Pcidev* pcitail;
  33. static int pcicfgrw32(int, int, int, int);
  34. uchar *vgabios;
  35. static int
  36. pciscan(int bno, Pcidev** list)
  37. {
  38. ulong v;
  39. Pcidev *p, *head, *tail;
  40. int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
  41. maxubn = bno;
  42. head = nil;
  43. tail = nil;
  44. for(dno = 0; dno <= pcimaxdno; dno++){
  45. maxfno = 0;
  46. for(fno = 0; fno <= maxfno; fno++){
  47. /*
  48. * For this possible device, form the
  49. * bus+device+function triplet needed to address it
  50. * and try to read the vendor and device ID.
  51. * If successful, allocate a device struct and
  52. * start to fill it in with some useful information
  53. * from the device's configuration space.
  54. */
  55. tbdf = MKBUS(BusPCI, bno, dno, fno);
  56. l = pcicfgrw32(tbdf, PciVID, 0, 1);
  57. if(l == 0xFFFFFFFF || l == 0)
  58. continue;
  59. /* optional safety checks:
  60. if(l == pcicfgrw32(tbdf, PciPCR, 0, 1))
  61. continue;
  62. if(l != pcicfgrw32(tbdf, PciVID, 0, 1))
  63. continue;
  64. if(l == pcicfgrw32(tbdf, PciPCR, 0, 1))
  65. continue;
  66. */
  67. p = malloc(sizeof(*p));
  68. p->tbdf = tbdf;
  69. p->vid = l;
  70. p->did = l>>16;
  71. if(pcilist != nil)
  72. pcitail->list = p;
  73. else
  74. pcilist = p;
  75. pcitail = p;
  76. p->rid = pcicfgr8(p, PciRID);
  77. p->ccrp = pcicfgr8(p, PciCCRp);
  78. p->ccru = pcicfgr8(p, PciCCRu);
  79. p->ccrb = pcicfgr8(p, PciCCRb);
  80. p->pcr = pcicfgr32(p, PciPCR);
  81. p->intl = pcicfgr8(p, PciINTL);
  82. /*
  83. * If the device is a multi-function device adjust the
  84. * loop count so all possible functions are checked.
  85. */
  86. hdt = pcicfgr8(p, PciHDT);
  87. if(hdt & 0x80)
  88. maxfno = MaxFNO;
  89. /*
  90. * If appropriate, read the base address registers
  91. * and work out the sizes.
  92. */
  93. switch(p->ccrb){
  94. case 0x03: /* display controller */
  95. if(vgabios == nil) {
  96. v = pcicfgr32(p, PciROM);
  97. pcicfgw32(p, PciROM, v|1); /* enable decode */
  98. vgabios = kmapv(((uvlong)0x88<<32LL)|(v&~0xffff), 0x10000);
  99. // print("VGA BIOS %lux -> %lux\n", v, vgabios);
  100. }
  101. /* fall through */
  102. case 0x01: /* mass storage controller */
  103. case 0x02: /* network controller */
  104. case 0x04: /* multimedia device */
  105. case 0x07: /* simple communication controllers */
  106. case 0x08: /* base system peripherals */
  107. case 0x09: /* input devices */
  108. case 0x0A: /* docking stations */
  109. case 0x0B: /* processors */
  110. case 0x0C: /* serial bus controllers */
  111. if((hdt & 0x7F) != 0)
  112. break;
  113. rno = PciBAR0 - 4;
  114. for(i = 0; i < nelem(p->mem); i++){
  115. rno += 4;
  116. p->mem[i].bar = pcicfgr32(p, rno);
  117. pcicfgw32(p, rno, -1);
  118. v = pcicfgr32(p, rno);
  119. pcicfgw32(p, rno, p->mem[i].bar);
  120. p->mem[i].size = -(v & ~0xF);
  121. }
  122. break;
  123. case 0x00:
  124. case 0x05: /* memory controller */
  125. case 0x06: /* bridge device */
  126. default:
  127. break;
  128. }
  129. if(head != nil)
  130. tail->link = p;
  131. else
  132. head = p;
  133. tail = p;
  134. }
  135. }
  136. *list = head;
  137. for(p = head; p != nil; p = p->link){
  138. /*
  139. * Find PCI-PCI bridges and recursively descend the tree.
  140. */
  141. if(p->ccrb != 0x06 || p->ccru != 0x04)
  142. continue;
  143. /*
  144. * If the secondary or subordinate bus number is not initialised
  145. * try to do what the PCI BIOS should have done and fill in the
  146. * numbers as the tree is descended. On the way down the subordinate
  147. * bus number is set to the maximum as it's not known how many
  148. * buses are behind this one; the final value is set on the way
  149. * back up.
  150. */
  151. sbn = pcicfgr8(p, PciSBN);
  152. ubn = pcicfgr8(p, PciUBN);
  153. if(sbn == 0 || ubn == 0){
  154. sbn = maxubn+1;
  155. /*
  156. * Make sure memory, I/O and master enables are off,
  157. * set the primary, secondary and subordinate bus numbers
  158. * and clear the secondary status before attempting to
  159. * scan the secondary bus.
  160. *
  161. * Initialisation of the bridge should be done here.
  162. */
  163. pcicfgw32(p, PciPCR, 0xFFFF0000);
  164. l = (MaxUBN<<16)|(sbn<<8)|bno;
  165. pcicfgw32(p, PciPBN, l);
  166. pcicfgw16(p, PciSPSR, 0xFFFF);
  167. maxubn = pciscan(sbn, &p->bridge);
  168. l = (maxubn<<16)|(sbn<<8)|bno;
  169. pcicfgw32(p, PciPBN, l);
  170. }
  171. else{
  172. maxubn = ubn;
  173. pciscan(sbn, &p->bridge);
  174. }
  175. }
  176. return maxubn;
  177. }
  178. static void
  179. pcicfginit(void)
  180. {
  181. char *p;
  182. lock(&pcicfginitlock);
  183. if(pcicfgmode == -1){
  184. pcicfgmode = 0;
  185. pcimaxdno = 15; /* was 20; what is correct value??? */
  186. if(p = getconf("*pcimaxdno"))
  187. pcimaxdno = strtoul(p, 0, 0);
  188. pciscan(0, &pciroot);
  189. }
  190. unlock(&pcicfginitlock);
  191. }
  192. static int
  193. pcicfgrw8(int tbdf, int rno, int data, int read)
  194. {
  195. int x;
  196. uchar *p;
  197. if(pcicfgmode == -1)
  198. pcicfginit();
  199. x = -1;
  200. if(BUSDNO(tbdf) > pcimaxdno)
  201. return x;
  202. p = (uchar*)arch->pcicfg(tbdf, rno);
  203. if(read)
  204. x = *p;
  205. else
  206. *p = data;
  207. return x;
  208. }
  209. int
  210. pcicfgr8(Pcidev* pcidev, int rno)
  211. {
  212. return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
  213. }
  214. void
  215. pcicfgw8(Pcidev* pcidev, int rno, int data)
  216. {
  217. pcicfgrw8(pcidev->tbdf, rno, data, 0);
  218. }
  219. static int
  220. pcicfgrw16(int tbdf, int rno, int data, int read)
  221. {
  222. int x;
  223. ushort *p;
  224. if(pcicfgmode == -1)
  225. pcicfginit();
  226. x = -1;
  227. if(BUSDNO(tbdf) > pcimaxdno)
  228. return x;
  229. p = (ushort*)arch->pcicfg(tbdf, rno);
  230. if(read)
  231. x = *p;
  232. else
  233. *p = data;
  234. return x;
  235. }
  236. int
  237. pcicfgr16(Pcidev* pcidev, int rno)
  238. {
  239. return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
  240. }
  241. void
  242. pcicfgw16(Pcidev* pcidev, int rno, int data)
  243. {
  244. pcicfgrw16(pcidev->tbdf, rno, data, 0);
  245. }
  246. static int
  247. pcicfgrw32(int tbdf, int rno, int data, int read)
  248. {
  249. int x;
  250. ulong *p;
  251. if(pcicfgmode == -1)
  252. pcicfginit();
  253. x = -1;
  254. if(BUSDNO(tbdf) > pcimaxdno)
  255. return x;
  256. p = (ulong*)arch->pcicfg(tbdf, rno);
  257. if(read)
  258. x = *p;
  259. else
  260. *p = data;
  261. return x;
  262. }
  263. int
  264. pcicfgr32(Pcidev* pcidev, int rno)
  265. {
  266. return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
  267. }
  268. void
  269. pcicfgw32(Pcidev* pcidev, int rno, int data)
  270. {
  271. pcicfgrw32(pcidev->tbdf, rno, data, 0);
  272. }
  273. Pcidev*
  274. pcimatch(Pcidev* prev, int vid, int did)
  275. {
  276. if(pcicfgmode == -1)
  277. pcicfginit();
  278. if(prev == nil)
  279. prev = pcilist;
  280. else
  281. prev = prev->list;
  282. while(prev != nil) {
  283. if((vid == 0 || prev->vid == vid)
  284. && (did == 0 || prev->did == did))
  285. break;
  286. prev = prev->list;
  287. }
  288. return prev;
  289. }
  290. Pcidev*
  291. pcimatchtbdf(int tbdf)
  292. {
  293. Pcidev *pcidev;
  294. if(pcicfgmode == -1)
  295. pcicfginit();
  296. for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
  297. if(pcidev->tbdf == tbdf)
  298. break;
  299. }
  300. return pcidev;
  301. }
  302. void
  303. pcihinv(Pcidev* p)
  304. {
  305. int i;
  306. Pcidev *t;
  307. if(pcicfgmode == -1)
  308. pcicfginit();
  309. if(p == nil) {
  310. p = pciroot;
  311. print("bus dev type vid did intl memory\n");
  312. }
  313. for(t = p; t != nil; t = t->link) {
  314. print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %2d ",
  315. BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
  316. t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
  317. for(i = 0; i < nelem(p->mem); i++) {
  318. if(t->mem[i].size == 0)
  319. continue;
  320. print("%d:%.8lux %d ", i,
  321. t->mem[i].bar, t->mem[i].size);
  322. }
  323. print("\n");
  324. }
  325. while(p != nil) {
  326. if(p->bridge != nil)
  327. pcihinv(p->bridge);
  328. p = p->link;
  329. }
  330. }
  331. void
  332. pcireset(void)
  333. {
  334. Pcidev *p;
  335. int pcr;
  336. if(pcicfgmode == -1)
  337. pcicfginit();
  338. for(p = pcilist; p != nil; p = p->list){
  339. pcr = pcicfgr16(p, PciPSR);
  340. pcicfgw16(p, PciPSR, pcr & ~0x04);
  341. }
  342. }
  343. void
  344. pcisetbme(Pcidev* p)
  345. {
  346. int pcr;
  347. pcr = pcicfgr16(p, PciPCR);
  348. pcr |= MASen;
  349. pcicfgw16(p, PciPCR, pcr);
  350. }
  351. void
  352. pciclrbme(Pcidev* p)
  353. {
  354. int pcr;
  355. pcr = pcicfgr16(p, PciPCR);
  356. pcr &= ~MASen;
  357. pcicfgw16(p, PciPCR, pcr);
  358. }