sd53c8xx.c 54 KB

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  1. /*
  2. * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
  3. * Nigel Roles (nigel@9fs.org)
  4. *
  5. * 27/5/02 Fixed problems with transfers >= 256 * 512
  6. *
  7. * 13/3/01 Fixed microcode to support targets > 7
  8. *
  9. * 01/12/00 Removed previous comments. Fixed a small problem in
  10. * mismatch recovery for targets with synchronous offsets of >=16
  11. * connected to >=875s. Thanks, Jean.
  12. *
  13. * Known problems
  14. *
  15. * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
  16. */
  17. #define MAXTARGET 16 /* can be 8 or 16 */
  18. #include "u.h"
  19. #include "../port/lib.h"
  20. #include "mem.h"
  21. #include "dat.h"
  22. #include "fns.h"
  23. #include "io.h"
  24. #include "../port/sd.h"
  25. extern SDifc sd53c8xxifc;
  26. /**********************************/
  27. /* Portable configuration macros */
  28. /**********************************/
  29. //#define BOOTDEBUG
  30. //#define ASYNC_ONLY
  31. //#define INTERNAL_SCLK
  32. //#define ALWAYS_DO_WDTR
  33. #define WMR_DEBUG
  34. /**********************************/
  35. /* CPU specific macros */
  36. /**********************************/
  37. #define PRINTPREFIX "sd53c8xx: "
  38. #ifdef BOOTDEBUG
  39. #define KPRINT oprint
  40. #define IPRINT intrprint
  41. #define DEBUG(n) 1
  42. #define IFLUSH() iflush()
  43. #else
  44. static int idebug = 1;
  45. #define KPRINT if(0) iprint
  46. #define IPRINT if(idebug) iprint
  47. #define DEBUG(n) (0)
  48. #define IFLUSH()
  49. #endif /* BOOTDEBUG */
  50. /*******************************/
  51. /* General */
  52. /*******************************/
  53. #ifndef DMASEG
  54. #define DMASEG(x) PCIWADDR(x)
  55. #define legetl(x) (*(ulong*)(x))
  56. #define lesetl(x,v) (*(ulong*)(x) = (v))
  57. #define swabl(a,b,c)
  58. #else
  59. #endif /*DMASEG */
  60. #define DMASEG_TO_KADDR(x) KADDR((x)-PCIWINDOW)
  61. #define KPTR(x) ((x) == 0 ? 0 : DMASEG_TO_KADDR(x))
  62. #define MEGA 1000000L
  63. #ifdef INTERNAL_SCLK
  64. #define SCLK (33 * MEGA)
  65. #else
  66. #define SCLK (40 * MEGA)
  67. #endif /* INTERNAL_SCLK */
  68. #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
  69. #define MAXSYNCSCSIRATE (5 * MEGA)
  70. #define MAXFASTSYNCSCSIRATE (10 * MEGA)
  71. #define MAXULTRASYNCSCSIRATE (20 * MEGA)
  72. #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
  73. #define MAXASYNCCORERATE (25 * MEGA)
  74. #define MAXSYNCCORERATE (25 * MEGA)
  75. #define MAXFASTSYNCCORERATE (50 * MEGA)
  76. #define MAXULTRASYNCCORERATE (80 * MEGA)
  77. #define MAXULTRA2SYNCCORERATE (160 * MEGA)
  78. #define X_MSG 1
  79. #define X_MSG_SDTR 1
  80. #define X_MSG_WDTR 3
  81. struct na_patch {
  82. unsigned lwoff;
  83. unsigned char type;
  84. };
  85. typedef struct Ncr {
  86. uchar scntl0; /* 00 */
  87. uchar scntl1;
  88. uchar scntl2;
  89. uchar scntl3;
  90. uchar scid; /* 04 */
  91. uchar sxfer;
  92. uchar sdid;
  93. uchar gpreg;
  94. uchar sfbr; /* 08 */
  95. uchar socl;
  96. uchar ssid;
  97. uchar sbcl;
  98. uchar dstat; /* 0c */
  99. uchar sstat0;
  100. uchar sstat1;
  101. uchar sstat2;
  102. uchar dsa[4]; /* 10 */
  103. uchar istat; /* 14 */
  104. uchar istatpad[3];
  105. uchar ctest0; /* 18 */
  106. uchar ctest1;
  107. uchar ctest2;
  108. uchar ctest3;
  109. uchar temp[4]; /* 1c */
  110. uchar dfifo; /* 20 */
  111. uchar ctest4;
  112. uchar ctest5;
  113. uchar ctest6;
  114. uchar dbc[3]; /* 24 */
  115. uchar dcmd; /* 27 */
  116. uchar dnad[4]; /* 28 */
  117. uchar dsp[4]; /* 2c */
  118. uchar dsps[4]; /* 30 */
  119. uchar scratcha[4]; /* 34 */
  120. uchar dmode; /* 38 */
  121. uchar dien;
  122. uchar dwt;
  123. uchar dcntl;
  124. uchar adder[4]; /* 3c */
  125. uchar sien0; /* 40 */
  126. uchar sien1;
  127. uchar sist0;
  128. uchar sist1;
  129. uchar slpar; /* 44 */
  130. uchar slparpad0;
  131. uchar macntl;
  132. uchar gpcntl;
  133. uchar stime0; /* 48 */
  134. uchar stime1;
  135. uchar respid;
  136. uchar respidpad0;
  137. uchar stest0; /* 4c */
  138. uchar stest1;
  139. uchar stest2;
  140. uchar stest3;
  141. uchar sidl; /* 50 */
  142. uchar sidlpad[3];
  143. uchar sodl; /* 54 */
  144. uchar sodlpad[3];
  145. uchar sbdl; /* 58 */
  146. uchar sbdlpad[3];
  147. uchar scratchb[4]; /* 5c */
  148. } Ncr;
  149. typedef struct Movedata {
  150. uchar dbc[4];
  151. uchar pa[4];
  152. } Movedata;
  153. typedef enum NegoState {
  154. NeitherDone, WideInit, WideResponse, WideDone,
  155. SyncInit, SyncResponse, BothDone
  156. } NegoState;
  157. typedef enum State {
  158. Allocated, Queued, Active, Done
  159. } State;
  160. typedef struct Dsa {
  161. uchar stateb;
  162. uchar result;
  163. uchar dmablks;
  164. uchar flag; /* setbyte(state,3,...) */
  165. union {
  166. ulong dmancr; /* For block transfer: NCR order (little-endian) */
  167. uchar dmaaddr[4];
  168. };
  169. uchar target; /* Target */
  170. uchar pad0[3];
  171. uchar lun; /* Logical Unit Number */
  172. uchar pad1[3];
  173. uchar scntl3;
  174. uchar sxfer;
  175. uchar pad2[2];
  176. uchar next[4]; /* chaining for SCRIPT (NCR byte order) */
  177. struct Dsa *freechain; /* chaining for freelist */
  178. Rendez;
  179. uchar scsi_id_buf[4];
  180. Movedata msg_out_buf;
  181. Movedata cmd_buf;
  182. Movedata data_buf;
  183. Movedata status_buf;
  184. uchar msg_out[10]; /* enough to include SDTR */
  185. uchar status;
  186. int p9status;
  187. uchar parityerror;
  188. } Dsa;
  189. typedef enum Feature {
  190. BigFifo = 1, /* 536 byte fifo */
  191. BurstOpCodeFetch = 2, /* burst fetch opcodes */
  192. Prefetch = 4, /* prefetch 8 longwords */
  193. LocalRAM = 8, /* 4K longwords of local RAM */
  194. Differential = 16, /* Differential support */
  195. Wide = 32, /* Wide capable */
  196. Ultra = 64, /* Ultra capable */
  197. ClockDouble = 128, /* Has clock doubler */
  198. ClockQuad = 256, /* Has clock quadrupler (same as Ultra2) */
  199. Ultra2 = 256,
  200. } Feature;
  201. typedef enum Burst {
  202. Burst2 = 0,
  203. Burst4 = 1,
  204. Burst8 = 2,
  205. Burst16 = 3,
  206. Burst32 = 4,
  207. Burst64 = 5,
  208. Burst128 = 6
  209. } Burst;
  210. typedef struct Variant {
  211. ushort did;
  212. uchar maxrid; /* maximum allowed revision ID */
  213. char *name;
  214. Burst burst; /* codings for max burst */
  215. uchar maxsyncoff; /* max synchronous offset */
  216. uchar registers; /* number of 32 bit registers */
  217. unsigned feature;
  218. } Variant;
  219. static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
  220. #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
  221. #define NULTRASCF (NULTRA2SCF - 2)
  222. #define NSCF (NULTRASCF - 1)
  223. typedef struct Controller {
  224. Lock;
  225. struct {
  226. uchar scntl3;
  227. uchar stest2;
  228. } bios;
  229. uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
  230. NegoState s[MAXTARGET];
  231. uchar scntl3[MAXTARGET];
  232. uchar sxfer[MAXTARGET];
  233. uchar cap[MAXTARGET]; /* capabilities byte from Identify */
  234. ushort capvalid; /* bit per target for validity of cap[] */
  235. ushort wide; /* bit per target set if wide negotiated */
  236. ulong sclk; /* clock speed of controller */
  237. uchar clockmult; /* set by synctabinit */
  238. uchar ccf; /* CCF bits */
  239. uchar tpf; /* best tpf value for this controller */
  240. uchar feature; /* requested features */
  241. int running; /* is the script processor running? */
  242. int ssm; /* single step mode */
  243. Ncr *n; /* pointer to registers */
  244. Variant *v; /* pointer to variant type */
  245. ulong *script; /* where the real script is */
  246. ulong scriptpa; /* where the real script is */
  247. Pcidev* pcidev;
  248. SDev* sdev;
  249. struct {
  250. Lock;
  251. uchar head[4]; /* head of free list (NCR byte order) */
  252. Dsa *freechain;
  253. } dsalist;
  254. QLock q[MAXTARGET]; /* queues for each target */
  255. } Controller;
  256. #define SYNCOFFMASK(c) (((c)->v->maxsyncoff * 2) - 1)
  257. #define SSIDMASK(c) (((c)->v->feature & Wide) ? 15 : 7)
  258. /* ISTAT */
  259. enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
  260. /* DSTAT */
  261. enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
  262. /* SSTAT */
  263. enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
  264. static void setmovedata(Movedata*, ulong, ulong);
  265. static void advancedata(Movedata*, long);
  266. static int bios_set_differential(Controller *c);
  267. static char *phase[] = {
  268. "data out", "data in", "command", "status",
  269. "reserved out", "reserved in", "message out", "message in"
  270. };
  271. #ifdef BOOTDEBUG
  272. #define DEBUGSIZE 10240
  273. char debugbuf[DEBUGSIZE];
  274. char *debuglast;
  275. static void
  276. intrprint(char *format, ...)
  277. {
  278. if (debuglast == 0)
  279. debuglast = debugbuf;
  280. debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  281. }
  282. static void
  283. iflush()
  284. {
  285. int s;
  286. char *endp;
  287. s = splhi();
  288. if (debuglast == 0)
  289. debuglast = debugbuf;
  290. if (debuglast == debugbuf) {
  291. splx(s);
  292. return;
  293. }
  294. endp = debuglast;
  295. splx(s);
  296. screenputs(debugbuf, endp - debugbuf);
  297. s = splhi();
  298. memmove(debugbuf, endp, debuglast - endp);
  299. debuglast -= endp - debugbuf;
  300. splx(s);
  301. }
  302. static void
  303. oprint(char *format, ...)
  304. {
  305. int s;
  306. iflush();
  307. s = splhi();
  308. if (debuglast == 0)
  309. debuglast = debugbuf;
  310. debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  311. splx(s);
  312. iflush();
  313. }
  314. #endif
  315. #include "sd53c8xx.i"
  316. /*
  317. * We used to use a linked list of Dsas with nil as the terminator,
  318. * but occasionally the 896 card seems not to notice that the 0
  319. * is really a 0, and then it tries to reference the Dsa at address 0.
  320. * To address this, we use a sentinel dsa that links back to itself
  321. * and has state A_STATE_END. If the card takes an iteration or
  322. * two to notice that the state says A_STATE_END, that's no big
  323. * deal. Clearly this isn't the right approach, but I'm just
  324. * stumped. Even with this, we occasionally get prints about
  325. * "WSR set", usually with about the same frequency that the
  326. * card used to walk past 0.
  327. */
  328. static Dsa *dsaend;
  329. static Dsa*
  330. dsaallocnew(Controller *c)
  331. {
  332. Dsa *d;
  333. /* c->dsalist must be ilocked */
  334. d = xalloc(sizeof *d);
  335. lesetl(d->next, legetl(c->dsalist.head));
  336. lesetl(&d->stateb, A_STATE_FREE);
  337. coherence();
  338. lesetl(c->dsalist.head, DMASEG(d));
  339. coherence();
  340. return d;
  341. }
  342. static Dsa *
  343. dsaalloc(Controller *c, int target, int lun)
  344. {
  345. Dsa *d;
  346. ilock(&c->dsalist);
  347. if ((d = c->dsalist.freechain) != 0) {
  348. if (DEBUG(1))
  349. IPRINT(PRINTPREFIX "%d/%d: reused dsa %lux\n", target, lun, (ulong)d);
  350. } else {
  351. d = dsaallocnew(c);
  352. if (DEBUG(1))
  353. IPRINT(PRINTPREFIX "%d/%d: allocated dsa %lux\n", target, lun, (ulong)d);
  354. }
  355. c->dsalist.freechain = d->freechain;
  356. lesetl(&d->stateb, A_STATE_ALLOCATED);
  357. iunlock(&c->dsalist);
  358. d->target = target;
  359. d->lun = lun;
  360. return d;
  361. }
  362. static void
  363. dsafree(Controller *c, Dsa *d)
  364. {
  365. ilock(&c->dsalist);
  366. d->freechain = c->dsalist.freechain;
  367. c->dsalist.freechain = d;
  368. lesetl(&d->stateb, A_STATE_FREE);
  369. iunlock(&c->dsalist);
  370. }
  371. static void
  372. dsadump(Controller *c)
  373. {
  374. Dsa *d;
  375. u32int *a;
  376. iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
  377. for(d=KPTR(legetl(c->dsalist.head)); d != dsaend; d=KPTR(legetl(d->next))){
  378. if(d == (void*)-1){
  379. iprint("\t dsa %p\n", d);
  380. break;
  381. }
  382. a = (u32int*)d;
  383. iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
  384. }
  385. /*
  386. a = KPTR(c->scriptpa+E_dsa_addr);
  387. iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  388. a[0], a[1], a[2], a[3], a[4]);
  389. a = KPTR(c->scriptpa+E_issue_addr);
  390. iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  391. a[0], a[1], a[2], a[3], a[4]);
  392. a = KPTR(c->scriptpa+E_issue_test_begin);
  393. e = KPTR(c->scriptpa+E_issue_test_end);
  394. iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
  395. i = 0;
  396. for(; a<e; a++){
  397. iprint(" %.8ux", *a);
  398. if(++i%8 == 0)
  399. iprint("\n");
  400. }
  401. if(i%8)
  402. iprint("\n");
  403. */
  404. }
  405. static Dsa *
  406. dsafind(Controller *c, uchar target, uchar lun, uchar state)
  407. {
  408. Dsa *d;
  409. for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  410. if (d->target != 0xff && d->target != target)
  411. continue;
  412. if (lun != 0xff && d->lun != lun)
  413. continue;
  414. if (state != 0xff && d->stateb != state)
  415. continue;
  416. break;
  417. }
  418. return d;
  419. }
  420. static void
  421. dumpncrregs(Controller *c, int intr)
  422. {
  423. int i;
  424. Ncr *n = c->n;
  425. int depth = c->v->registers / 4;
  426. if (intr) {
  427. IPRINT("sa = %.8lux\n", c->scriptpa);
  428. }
  429. else {
  430. KPRINT("sa = %.8lux\n", c->scriptpa);
  431. }
  432. for (i = 0; i < depth; i++) {
  433. int j;
  434. for (j = 0; j < 4; j++) {
  435. int k = j * depth + i;
  436. uchar *p;
  437. /* display little-endian to make 32-bit values readable */
  438. p = (uchar*)n+k*4;
  439. if (intr) {
  440. IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  441. }
  442. else {
  443. KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  444. }
  445. USED(p);
  446. }
  447. if (intr) {
  448. IPRINT("\n");
  449. }
  450. else {
  451. KPRINT("\n");
  452. }
  453. }
  454. }
  455. static int
  456. chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
  457. {
  458. /* find lowest entry >= tpf */
  459. int besttpf = 1000;
  460. int bestscfi = 0;
  461. int bestxferp = 0;
  462. int scf, xferp;
  463. int maxscf;
  464. if (c->v->feature & Ultra2)
  465. maxscf = NULTRA2SCF;
  466. else if (c->v->feature & Ultra)
  467. maxscf = NULTRASCF;
  468. else
  469. maxscf = NSCF;
  470. /*
  471. * search large clock factors first since this should
  472. * result in more reliable transfers
  473. */
  474. for (scf = maxscf; scf >= 1; scf--) {
  475. for (xferp = 0; xferp < 8; xferp++) {
  476. unsigned char v = c->synctab[scf - 1][xferp];
  477. if (v == 0)
  478. continue;
  479. if (v >= tpf && v < besttpf) {
  480. besttpf = v;
  481. bestscfi = scf;
  482. bestxferp = xferp;
  483. }
  484. }
  485. }
  486. if (besttpf == 1000)
  487. return 0;
  488. if (scfp)
  489. *scfp = bestscfi;
  490. if (xferpp)
  491. *xferpp = bestxferp;
  492. return besttpf;
  493. }
  494. static void
  495. synctabinit(Controller *c)
  496. {
  497. int scf;
  498. unsigned long scsilimit;
  499. int xferp;
  500. unsigned long cr, sr;
  501. int tpf;
  502. int fast;
  503. int maxscf;
  504. if (c->v->feature & Ultra2)
  505. maxscf = NULTRA2SCF;
  506. else if (c->v->feature & Ultra)
  507. maxscf = NULTRASCF;
  508. else
  509. maxscf = NSCF;
  510. /*
  511. * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
  512. * first spin of the 875), assume 80MHz
  513. * otherwise use the internal (33 Mhz) or external (40MHz) default
  514. */
  515. if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
  516. c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
  517. else
  518. c->sclk = SCLK;
  519. /*
  520. * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
  521. * invoke the doubler
  522. */
  523. if (SCLK <= 40000000) {
  524. if (c->v->feature & ClockDouble) {
  525. c->sclk *= 2;
  526. c->clockmult = 1;
  527. }
  528. else if (c->v->feature & ClockQuad) {
  529. c->sclk *= 4;
  530. c->clockmult = 1;
  531. }
  532. else
  533. c->clockmult = 0;
  534. }
  535. else
  536. c->clockmult = 0;
  537. /* derive CCF from sclk */
  538. /* woebetide anyone with SCLK < 16.7 or > 80MHz */
  539. if (c->sclk <= 25 * MEGA)
  540. c->ccf = 1;
  541. else if (c->sclk <= 3750000)
  542. c->ccf = 2;
  543. else if (c->sclk <= 50 * MEGA)
  544. c->ccf = 3;
  545. else if (c->sclk <= 75 * MEGA)
  546. c->ccf = 4;
  547. else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
  548. c->ccf = 5;
  549. else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
  550. c->ccf = 6;
  551. else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
  552. c->ccf = 7;
  553. for (scf = 1; scf < maxscf; scf++) {
  554. /* check for legal core rate */
  555. /* round up so we run slower for safety */
  556. cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
  557. if (cr <= MAXSYNCCORERATE) {
  558. scsilimit = MAXSYNCSCSIRATE;
  559. fast = 0;
  560. }
  561. else if (cr <= MAXFASTSYNCCORERATE) {
  562. scsilimit = MAXFASTSYNCSCSIRATE;
  563. fast = 1;
  564. }
  565. else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
  566. scsilimit = MAXULTRASYNCSCSIRATE;
  567. fast = 2;
  568. }
  569. else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
  570. scsilimit = MAXULTRA2SYNCSCSIRATE;
  571. fast = 3;
  572. }
  573. else
  574. continue;
  575. for (xferp = 11; xferp >= 4; xferp--) {
  576. int ok;
  577. int tp;
  578. /* calculate scsi rate - round up again */
  579. /* start from sclk for accuracy */
  580. int totaldivide = xferp * cf2[scf];
  581. sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
  582. if (sr > scsilimit)
  583. break;
  584. /*
  585. * now work out transfer period
  586. * round down now so that period is pessimistic
  587. */
  588. tp = (MEGA * 1000) / sr;
  589. /*
  590. * bounds check it
  591. */
  592. if (tp < 25 || tp > 255 * 4)
  593. continue;
  594. /*
  595. * spot stupid special case for Ultra or Ultra2
  596. * while working out factor
  597. */
  598. if (tp == 25)
  599. tpf = 10;
  600. else if (tp == 50)
  601. tpf = 12;
  602. else if (tp < 52)
  603. continue;
  604. else
  605. tpf = tp / 4;
  606. /*
  607. * now check tpf looks sensible
  608. * given core rate
  609. */
  610. switch (fast) {
  611. case 0:
  612. /* scf must be ccf for SCSI 1 */
  613. ok = tpf >= 50 && scf == c->ccf;
  614. break;
  615. case 1:
  616. ok = tpf >= 25 && tpf < 50;
  617. break;
  618. case 2:
  619. /*
  620. * must use xferp of 4, or 5 at a pinch
  621. * for an Ultra transfer
  622. */
  623. ok = xferp <= 5 && tpf >= 12 && tpf < 25;
  624. break;
  625. case 3:
  626. ok = xferp == 4 && (tpf == 10 || tpf == 11);
  627. break;
  628. default:
  629. ok = 0;
  630. }
  631. if (!ok)
  632. continue;
  633. c->synctab[scf - 1][xferp - 4] = tpf;
  634. }
  635. }
  636. #ifndef NO_ULTRA2
  637. if (c->v->feature & Ultra2)
  638. tpf = 10;
  639. else
  640. #endif
  641. if (c->v->feature & Ultra)
  642. tpf = 12;
  643. else
  644. tpf = 25;
  645. for (; tpf < 256; tpf++) {
  646. if (chooserate(c, tpf, &scf, &xferp) == tpf) {
  647. unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
  648. unsigned long khz = (MEGA + tp - 1) / (tp);
  649. KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
  650. tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
  651. xferp + 4, khz / 1000, khz % 1000);
  652. USED(khz);
  653. if (c->tpf == 0)
  654. c->tpf = tpf; /* note lowest value for controller */
  655. }
  656. }
  657. }
  658. static void
  659. synctodsa(Dsa *dsa, Controller *c)
  660. {
  661. /*
  662. KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
  663. dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
  664. */
  665. dsa->scntl3 = c->scntl3[dsa->target];
  666. dsa->sxfer = c->sxfer[dsa->target];
  667. }
  668. static void
  669. setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
  670. {
  671. c->scntl3[target] =
  672. (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
  673. c->sxfer[target] = (xferp << 5) | reqack;
  674. c->s[target] = BothDone;
  675. if (dsa) {
  676. synctodsa(dsa, c);
  677. c->n->scntl3 = c->scntl3[target];
  678. c->n->sxfer = c->sxfer[target];
  679. }
  680. }
  681. static void
  682. setasync(Dsa *dsa, Controller *c, int target)
  683. {
  684. setsync(dsa, c, target, 0, c->ccf, 0, 0);
  685. }
  686. static void
  687. setwide(Dsa *dsa, Controller *c, int target, uchar wide)
  688. {
  689. c->scntl3[target] = wide ? (1 << 3) : 0;
  690. setasync(dsa, c, target);
  691. c->s[target] = WideDone;
  692. }
  693. static int
  694. buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
  695. {
  696. *buf++ = X_MSG;
  697. *buf++ = 3;
  698. *buf++ = X_MSG_SDTR;
  699. *buf++ = tpf;
  700. *buf = offset;
  701. return 5;
  702. }
  703. static int
  704. buildwdtrmsg(uchar *buf, uchar expo)
  705. {
  706. *buf++ = X_MSG;
  707. *buf++ = 2;
  708. *buf++ = X_MSG_WDTR;
  709. *buf = expo;
  710. return 4;
  711. }
  712. static void
  713. start(Controller *c, long entry)
  714. {
  715. ulong p;
  716. if (c->running)
  717. panic(PRINTPREFIX "start called while running");
  718. c->running = 1;
  719. p = c->scriptpa + entry;
  720. lesetl(c->n->dsp, p);
  721. coherence();
  722. if (c->ssm)
  723. c->n->dcntl |= 0x4; /* start DMA in SSI mode */
  724. }
  725. static void
  726. ncrcontinue(Controller *c)
  727. {
  728. if (c->running)
  729. panic(PRINTPREFIX "ncrcontinue called while running");
  730. /* set the start DMA bit to continue execution */
  731. c->running = 1;
  732. coherence();
  733. c->n->dcntl |= 0x4;
  734. }
  735. static void
  736. softreset(Controller *c)
  737. {
  738. Ncr *n = c->n;
  739. n->istat = Srst; /* software reset */
  740. n->istat = 0;
  741. /* general initialisation */
  742. n->scid = (1 << 6) | 7; /* respond to reselect, ID 7 */
  743. n->respid = 1 << 7; /* response ID = 7 */
  744. #ifdef INTERNAL_SCLK
  745. n->stest1 = 0x80; /* disable external scsi clock */
  746. #else
  747. n->stest1 = 0x00;
  748. #endif
  749. n->stime0 = 0xdd; /* about 0.5 second timeout on each device */
  750. n->scntl0 |= 0x8; /* Enable parity checking */
  751. /* continued setup */
  752. n->sien0 = 0x8f;
  753. n->sien1 = 0x04;
  754. n->dien = 0x7d;
  755. n->stest3 = 0x80; /* TolerANT enable */
  756. c->running = 0;
  757. if (c->v->feature & BigFifo)
  758. n->ctest5 = (1 << 5);
  759. n->dmode = c->v->burst << 6; /* set burst length bits */
  760. if (c->v->burst & 4)
  761. n->ctest5 |= (1 << 2); /* including overflow into ctest5 bit 2 */
  762. if (c->v->feature & Prefetch)
  763. n->dcntl |= (1 << 5); /* prefetch enable */
  764. else if (c->v->feature & BurstOpCodeFetch)
  765. n->dmode |= (1 << 1); /* burst opcode fetch */
  766. if (c->v->feature & Differential) {
  767. /* chip capable */
  768. if ((c->feature & Differential) || bios_set_differential(c)) {
  769. /* user enabled, or some evidence bios set differential */
  770. if (n->sstat2 & (1 << 2))
  771. print(PRINTPREFIX "can't go differential; wrong cable\n");
  772. else {
  773. n->stest2 = (1 << 5);
  774. print(PRINTPREFIX "differential mode set\n");
  775. }
  776. }
  777. }
  778. if (c->clockmult) {
  779. n->stest1 |= (1 << 3); /* power up doubler */
  780. delay(2);
  781. n->stest3 |= (1 << 5); /* stop clock */
  782. n->stest1 |= (1 << 2); /* enable doubler */
  783. n->stest3 &= ~(1 << 5); /* start clock */
  784. /* pray */
  785. }
  786. }
  787. static void
  788. msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
  789. {
  790. uchar histpf, hisreqack;
  791. int tpf;
  792. int scf, xferp;
  793. int len;
  794. Ncr *n = c->n;
  795. switch (c->s[dsa->target]) {
  796. case SyncInit:
  797. switch (msg) {
  798. case A_SIR_MSG_SDTR:
  799. /* reply to my SDTR */
  800. histpf = n->scratcha[2];
  801. hisreqack = n->scratcha[3];
  802. KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
  803. dsa->target, histpf, hisreqack);
  804. if (hisreqack == 0)
  805. setasync(dsa, c, dsa->target);
  806. else {
  807. /* hisreqack should be <= c->v->maxsyncoff */
  808. tpf = chooserate(c, histpf, &scf, &xferp);
  809. KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
  810. dsa->target, tpf, hisreqack);
  811. setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  812. }
  813. *cont = -2;
  814. return;
  815. case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  816. /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  817. KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  818. KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  819. setasync(dsa, c, dsa->target);
  820. *cont = E_to_decisions;
  821. return;
  822. case A_SIR_MSG_REJECT:
  823. /* rejection of my SDTR */
  824. KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
  825. //async:
  826. KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  827. setasync(dsa, c, dsa->target);
  828. *cont = -2;
  829. return;
  830. }
  831. break;
  832. case WideInit:
  833. switch (msg) {
  834. case A_SIR_MSG_WDTR:
  835. /* reply to my WDTR */
  836. KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
  837. dsa->target, n->scratcha[2]);
  838. setwide(dsa, c, dsa->target, n->scratcha[2]);
  839. *cont = -2;
  840. return;
  841. case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  842. /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  843. KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  844. setwide(dsa, c, dsa->target, 0);
  845. *cont = E_to_decisions;
  846. return;
  847. case A_SIR_MSG_REJECT:
  848. /* rejection of my SDTR */
  849. KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
  850. setwide(dsa, c, dsa->target, 0);
  851. *cont = -2;
  852. return;
  853. }
  854. break;
  855. case NeitherDone:
  856. case WideDone:
  857. case BothDone:
  858. switch (msg) {
  859. case A_SIR_MSG_WDTR: {
  860. uchar hiswide, mywide;
  861. hiswide = n->scratcha[2];
  862. mywide = (c->v->feature & Wide) != 0;
  863. KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
  864. dsa->target, hiswide);
  865. if (hiswide < mywide)
  866. mywide = hiswide;
  867. KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
  868. dsa->target, mywide);
  869. setwide(dsa, c, dsa->target, mywide);
  870. len = buildwdtrmsg(dsa->msg_out, mywide);
  871. setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  872. *cont = E_response;
  873. c->s[dsa->target] = WideResponse;
  874. return;
  875. }
  876. case A_SIR_MSG_SDTR:
  877. #ifdef ASYNC_ONLY
  878. *cont = E_reject;
  879. return;
  880. #else
  881. /* target decides to renegotiate */
  882. histpf = n->scratcha[2];
  883. hisreqack = n->scratcha[3];
  884. KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
  885. dsa->target, histpf, hisreqack);
  886. if (hisreqack == 0) {
  887. /* he wants asynchronous */
  888. setasync(dsa, c, dsa->target);
  889. tpf = 0;
  890. }
  891. else {
  892. /* he wants synchronous */
  893. tpf = chooserate(c, histpf, &scf, &xferp);
  894. if (hisreqack > c->v->maxsyncoff)
  895. hisreqack = c->v->maxsyncoff;
  896. KPRINT(PRINTPREFIX "%d: using %d %d\n",
  897. dsa->target, tpf, hisreqack);
  898. setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  899. }
  900. /* build my SDTR message */
  901. len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
  902. setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  903. *cont = E_response;
  904. c->s[dsa->target] = SyncResponse;
  905. return;
  906. #endif
  907. }
  908. break;
  909. case WideResponse:
  910. switch (msg) {
  911. case A_SIR_EV_RESPONSE_OK:
  912. c->s[dsa->target] = WideDone;
  913. KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
  914. *cont = -2;
  915. return;
  916. case A_SIR_MSG_REJECT:
  917. setwide(dsa, c, dsa->target, 0);
  918. KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
  919. *cont = -2;
  920. return;
  921. }
  922. break;
  923. case SyncResponse:
  924. switch (msg) {
  925. case A_SIR_EV_RESPONSE_OK:
  926. c->s[dsa->target] = BothDone;
  927. KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
  928. dsa->target, phase[n->sstat1 & 7]);
  929. *cont = -2;
  930. return; /* chf */
  931. case A_SIR_MSG_REJECT:
  932. setasync(dsa, c, dsa->target);
  933. KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
  934. *cont = -2;
  935. return;
  936. }
  937. break;
  938. }
  939. KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
  940. dsa->target, c->s[dsa->target], msg);
  941. *wakeme = 1;
  942. return;
  943. }
  944. static void
  945. calcblockdma(Dsa *d, ulong base, ulong count)
  946. {
  947. ulong blocks;
  948. if (DEBUG(3))
  949. blocks = 0;
  950. else {
  951. blocks = count / A_BSIZE;
  952. if (blocks > 255)
  953. blocks = 255;
  954. }
  955. d->dmablks = blocks;
  956. d->dmaaddr[0] = base;
  957. d->dmaaddr[1] = base >> 8;
  958. d->dmaaddr[2] = base >> 16;
  959. d->dmaaddr[3] = base >> 24;
  960. setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
  961. d->flag = legetl(d->data_buf.dbc) == 0;
  962. }
  963. static ulong
  964. read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
  965. {
  966. ulong dbc;
  967. uchar dfifo = n->dfifo;
  968. int inchip;
  969. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  970. if (n->ctest5 & (1 << 5))
  971. inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
  972. else
  973. inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
  974. if (inchip) {
  975. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
  976. dsa->target, dsa->lun, inchip);
  977. }
  978. if (n->sxfer & SYNCOFFMASK(c)) {
  979. /* SCSI FIFO */
  980. uchar fifo = n->sstat1 >> 4;
  981. if (c->v->maxsyncoff > 8)
  982. fifo |= (n->sstat2 & (1 << 4));
  983. if (fifo) {
  984. inchip += fifo;
  985. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
  986. dsa->target, dsa->lun, fifo);
  987. }
  988. }
  989. else {
  990. if (n->sstat0 & (1 << 7)) {
  991. inchip++;
  992. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
  993. dsa->target, dsa->lun);
  994. }
  995. if (n->sstat2 & (1 << 7)) {
  996. inchip++;
  997. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
  998. dsa->target, dsa->lun);
  999. }
  1000. }
  1001. USED(inchip);
  1002. return dbc;
  1003. }
  1004. static ulong
  1005. write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
  1006. {
  1007. ulong dbc;
  1008. uchar dfifo = n->dfifo;
  1009. int inchip;
  1010. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  1011. USED(dsa);
  1012. if (n->ctest5 & (1 << 5))
  1013. inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
  1014. else
  1015. inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
  1016. #ifdef WMR_DEBUG
  1017. if (inchip) {
  1018. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
  1019. dsa->target, dsa->lun, inchip);
  1020. }
  1021. #endif
  1022. if (n->sstat0 & (1 << 5)) {
  1023. inchip++;
  1024. #ifdef WMR_DEBUG
  1025. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
  1026. #endif
  1027. }
  1028. if (n->sstat2 & (1 << 5)) {
  1029. inchip++;
  1030. #ifdef WMR_DEBUG
  1031. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
  1032. #endif
  1033. }
  1034. if (n->sxfer & SYNCOFFMASK(c)) {
  1035. /* synchronous SODR */
  1036. if (n->sstat0 & (1 << 6)) {
  1037. inchip++;
  1038. #ifdef WMR_DEBUG
  1039. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
  1040. dsa->target, dsa->lun);
  1041. #endif
  1042. }
  1043. if (n->sstat2 & (1 << 6)) {
  1044. inchip++;
  1045. #ifdef WMR_DEBUG
  1046. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
  1047. dsa->target, dsa->lun);
  1048. #endif
  1049. }
  1050. }
  1051. /* clear the dma fifo */
  1052. n->ctest3 |= (1 << 2);
  1053. /* wait till done */
  1054. while ((n->dstat & Dfe) == 0)
  1055. ;
  1056. return dbc + inchip;
  1057. }
  1058. static void
  1059. sd53c8xxinterrupt(Ureg *ur, void *a)
  1060. {
  1061. uchar istat;
  1062. ushort sist;
  1063. uchar dstat;
  1064. int wakeme = 0;
  1065. int cont = -1;
  1066. Dsa *dsa;
  1067. ulong dsapa;
  1068. Controller *c = a;
  1069. Ncr *n = c->n;
  1070. USED(ur);
  1071. if (DEBUG(1)) {
  1072. IPRINT(PRINTPREFIX "int\n");
  1073. }
  1074. ilock(c);
  1075. istat = n->istat;
  1076. if (istat & Intf) {
  1077. Dsa *d;
  1078. int wokesomething = 0;
  1079. if (DEBUG(1)) {
  1080. IPRINT(PRINTPREFIX "Intfly\n");
  1081. }
  1082. n->istat = Intf;
  1083. /* search for structures in A_STATE_DONE */
  1084. for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  1085. if (d->stateb == A_STATE_DONE) {
  1086. d->p9status = d->status;
  1087. if (DEBUG(1)) {
  1088. IPRINT(PRINTPREFIX "waking up dsa %lux\n", (ulong)d);
  1089. }
  1090. wakeup(d);
  1091. wokesomething = 1;
  1092. }
  1093. }
  1094. if (!wokesomething) {
  1095. IPRINT(PRINTPREFIX "nothing to wake up\n");
  1096. }
  1097. }
  1098. if ((istat & (Sip | Dip)) == 0) {
  1099. if (DEBUG(1)) {
  1100. IPRINT(PRINTPREFIX "int end %x\n", istat);
  1101. }
  1102. iunlock(c);
  1103. return;
  1104. }
  1105. sist = (n->sist1<<8)|n->sist0; /* BUG? can two-byte read be inconsistent? */
  1106. dstat = n->dstat;
  1107. dsapa = legetl(n->dsa);
  1108. /*
  1109. * Can't compute dsa until we know that dsapa is valid.
  1110. */
  1111. if(dsapa < -KZERO)
  1112. dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
  1113. else{
  1114. dsa = nil;
  1115. /*
  1116. * happens at startup on some cards but we
  1117. * don't actually deref dsa because none of the
  1118. * flags we are about are set.
  1119. * still, print in case that changes and we're
  1120. * about to dereference nil.
  1121. */
  1122. iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
  1123. }
  1124. c->running = 0;
  1125. if (istat & Sip) {
  1126. if (DEBUG(1)) {
  1127. IPRINT("sist = %.4x\n", sist);
  1128. }
  1129. if (sist & 0x80) {
  1130. ulong addr;
  1131. ulong sa;
  1132. ulong dbc;
  1133. ulong tbc;
  1134. int dmablks;
  1135. ulong dmaaddr;
  1136. addr = legetl(n->dsp);
  1137. sa = addr - c->scriptpa;
  1138. if (DEBUG(1) || DEBUG(2)) {
  1139. IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
  1140. dsa->target, dsa->lun, sa);
  1141. }
  1142. /*
  1143. * now recover
  1144. */
  1145. if (sa == E_data_in_mismatch) {
  1146. /*
  1147. * though this is a failure in the residue, there may have been blocks
  1148. * as well. if so, dmablks will not have been zeroed, since the state
  1149. * was not saved by the microcode.
  1150. */
  1151. dbc = read_mismatch_recover(c, n, dsa);
  1152. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1153. dsa->dmablks = 0;
  1154. n->scratcha[2] = 0;
  1155. advancedata(&dsa->data_buf, tbc);
  1156. if (DEBUG(1) || DEBUG(2)) {
  1157. IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
  1158. dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
  1159. }
  1160. cont = E_data_mismatch_recover;
  1161. }
  1162. else if (sa == E_data_in_block_mismatch) {
  1163. dbc = read_mismatch_recover(c, n, dsa);
  1164. tbc = A_BSIZE - dbc;
  1165. /* recover current state from registers */
  1166. dmablks = n->scratcha[2];
  1167. dmaaddr = legetl(n->scratchb);
  1168. /* we have got to dmaaddr + tbc */
  1169. /* we have dmablks * A_BSIZE - tbc + residue left to do */
  1170. /* so remaining transfer is */
  1171. IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
  1172. dmaaddr, tbc, dmablks);
  1173. calcblockdma(dsa, dmaaddr + tbc,
  1174. dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
  1175. /* copy changes into scratch registers */
  1176. IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
  1177. dsa->dmablks, legetl(dsa->dmaaddr),
  1178. legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
  1179. n->scratcha[2] = dsa->dmablks;
  1180. lesetl(n->scratchb, dsa->dmancr);
  1181. cont = E_data_block_mismatch_recover;
  1182. }
  1183. else if (sa == E_data_out_mismatch) {
  1184. dbc = write_mismatch_recover(c, n, dsa);
  1185. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1186. dsa->dmablks = 0;
  1187. n->scratcha[2] = 0;
  1188. advancedata(&dsa->data_buf, tbc);
  1189. if (DEBUG(1) || DEBUG(2)) {
  1190. IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
  1191. dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
  1192. }
  1193. cont = E_data_mismatch_recover;
  1194. }
  1195. else if (sa == E_data_out_block_mismatch) {
  1196. dbc = write_mismatch_recover(c, n, dsa);
  1197. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1198. /* recover current state from registers */
  1199. dmablks = n->scratcha[2];
  1200. dmaaddr = legetl(n->scratchb);
  1201. /* we have got to dmaaddr + tbc */
  1202. /* we have dmablks blocks - tbc + residue left to do */
  1203. /* so remaining transfer is */
  1204. IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
  1205. dmaaddr, tbc, dmablks);
  1206. calcblockdma(dsa, dmaaddr + tbc,
  1207. dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
  1208. /* copy changes into scratch registers */
  1209. n->scratcha[2] = dsa->dmablks;
  1210. lesetl(n->scratchb, dsa->dmancr);
  1211. cont = E_data_block_mismatch_recover;
  1212. }
  1213. else if (sa == E_id_out_mismatch) {
  1214. /*
  1215. * target switched phases while attention held during
  1216. * message out. The possibilities are:
  1217. * 1. It didn't like the last message. This is indicated
  1218. * by the new phase being message_in. Use script to recover
  1219. *
  1220. * 2. It's not SCSI-II compliant. The new phase will be other
  1221. * than message_in. We should also indicate that the device
  1222. * is asynchronous, if it's the SDTR that got ignored
  1223. *
  1224. * For now, if the phase switch is not to message_in, and
  1225. * and it happens after IDENTIFY and before SDTR, we
  1226. * notify the negotiation state machine.
  1227. */
  1228. ulong lim = legetl(dsa->msg_out_buf.dbc);
  1229. uchar p = n->sstat1 & 7;
  1230. dbc = write_mismatch_recover(c, n, dsa);
  1231. tbc = lim - dbc;
  1232. IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
  1233. dsa->target, dsa->lun, tbc, lim, phase[p]);
  1234. if (p != MessageIn && tbc == 1) {
  1235. msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
  1236. }
  1237. else
  1238. cont = E_id_out_mismatch_recover;
  1239. }
  1240. else if (sa == E_cmd_out_mismatch) {
  1241. /*
  1242. * probably the command count is longer than the device wants ...
  1243. */
  1244. ulong lim = legetl(dsa->cmd_buf.dbc);
  1245. uchar p = n->sstat1 & 7;
  1246. dbc = write_mismatch_recover(c, n, dsa);
  1247. tbc = lim - dbc;
  1248. IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
  1249. dsa->target, dsa->lun, tbc, lim, phase[p]);
  1250. USED(p, tbc);
  1251. cont = E_to_decisions;
  1252. }
  1253. else {
  1254. IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
  1255. dsa->target, dsa->lun, sa,
  1256. phase[n->dcmd & 7],
  1257. phase[n->sstat1 & 7]);
  1258. dumpncrregs(c, 1);
  1259. dsa->p9status = SDeio; /* chf */
  1260. wakeme = 1;
  1261. }
  1262. }
  1263. /*else*/ if (sist & 0x400) {
  1264. if (DEBUG(0)) {
  1265. IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
  1266. }
  1267. dsa->p9status = SDtimeout;
  1268. dsa->stateb = A_STATE_DONE;
  1269. coherence();
  1270. softreset(c);
  1271. cont = E_issue_check;
  1272. wakeme = 1;
  1273. }
  1274. if (sist & 0x1) {
  1275. IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
  1276. dsa->parityerror = 1;
  1277. }
  1278. if (sist & 0x4) {
  1279. IPRINT(PRINTPREFIX "%d/%d: unexpected disconnect\n",
  1280. dsa->target, dsa->lun);
  1281. dumpncrregs(c, 1);
  1282. //wakeme = 1;
  1283. dsa->p9status = SDeio;
  1284. }
  1285. }
  1286. if (istat & Dip) {
  1287. if (DEBUG(1)) {
  1288. IPRINT("dstat = %.2x\n", dstat);
  1289. }
  1290. /*else*/ if (dstat & Ssi) {
  1291. ulong w = legetl(n->dsp) - c->scriptpa;
  1292. IPRINT("[%lux]", w);
  1293. USED(w);
  1294. cont = -2; /* restart */
  1295. }
  1296. if (dstat & Sir) {
  1297. switch (legetl(n->dsps)) {
  1298. case A_SIR_MSG_IO_COMPLETE:
  1299. dsa->p9status = dsa->status;
  1300. wakeme = 1;
  1301. break;
  1302. case A_SIR_MSG_SDTR:
  1303. case A_SIR_MSG_WDTR:
  1304. case A_SIR_MSG_REJECT:
  1305. case A_SIR_EV_RESPONSE_OK:
  1306. msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
  1307. break;
  1308. case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
  1309. /* back up one in the data transfer */
  1310. IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
  1311. dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
  1312. if (dsa->flag == 2) {
  1313. IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
  1314. dsa->target, dsa->lun);
  1315. }
  1316. else {
  1317. calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
  1318. dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
  1319. }
  1320. cont = -2;
  1321. break;
  1322. case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
  1323. IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
  1324. n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
  1325. dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
  1326. dumpncrregs(c, 1);
  1327. wakeme = 1;
  1328. break;
  1329. case A_SIR_NOTIFY_LOAD_STATE:
  1330. IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
  1331. if (dsa == (void*)KZERO || dsa == (void*)-1) {
  1332. dsadump(c);
  1333. dumpncrregs(c, 1);
  1334. panic("bad dsa in load_state");
  1335. }
  1336. cont = -2;
  1337. break;
  1338. case A_SIR_NOTIFY_MSG_IN:
  1339. IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
  1340. dsa->target, dsa->lun, n->sfbr);
  1341. cont = -2;
  1342. break;
  1343. case A_SIR_NOTIFY_DISC:
  1344. IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
  1345. goto dsadump;
  1346. case A_SIR_NOTIFY_STATUS:
  1347. IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
  1348. cont = -2;
  1349. break;
  1350. case A_SIR_NOTIFY_COMMAND:
  1351. IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
  1352. cont = -2;
  1353. break;
  1354. case A_SIR_NOTIFY_DATA_IN:
  1355. IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
  1356. dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
  1357. cont = -2;
  1358. break;
  1359. case A_SIR_NOTIFY_BLOCK_DATA_IN:
  1360. IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
  1361. dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
  1362. cont = -2;
  1363. break;
  1364. case A_SIR_NOTIFY_DATA_OUT:
  1365. IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
  1366. cont = -2;
  1367. break;
  1368. case A_SIR_NOTIFY_DUMP:
  1369. IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
  1370. dumpncrregs(c, 1);
  1371. cont = -2;
  1372. break;
  1373. case A_SIR_NOTIFY_DUMP2:
  1374. IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
  1375. IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
  1376. IPRINT(" dsa %lux", legetl(n->dsa));
  1377. IPRINT(" sfbr %ux", n->sfbr);
  1378. IPRINT(" a %lux", legetl(n->scratcha));
  1379. IPRINT(" b %lux", legetl(n->scratchb));
  1380. IPRINT(" ssid %ux", n->ssid);
  1381. IPRINT("\n");
  1382. cont = -2;
  1383. break;
  1384. case A_SIR_NOTIFY_WAIT_RESELECT:
  1385. IPRINT(PRINTPREFIX "wait reselect\n");
  1386. cont = -2;
  1387. break;
  1388. case A_SIR_NOTIFY_RESELECT:
  1389. IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
  1390. n->ssid, n->sfbr, TK2MS(m->ticks));
  1391. cont = -2;
  1392. break;
  1393. case A_SIR_NOTIFY_ISSUE:
  1394. IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
  1395. dsadump:
  1396. IPRINT(" tgt=%d", dsa->target);
  1397. IPRINT(" time=%ld", TK2MS(m->ticks));
  1398. IPRINT("\n");
  1399. cont = -2;
  1400. break;
  1401. case A_SIR_NOTIFY_ISSUE_CHECK:
  1402. IPRINT(PRINTPREFIX "issue check\n");
  1403. cont = -2;
  1404. break;
  1405. case A_SIR_NOTIFY_SIGP:
  1406. IPRINT(PRINTPREFIX "responded to SIGP\n");
  1407. cont = -2;
  1408. break;
  1409. case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
  1410. ulong *dsp = c->script + (legetl(n->dsp)-c->scriptpa)/4;
  1411. int x;
  1412. IPRINT(PRINTPREFIX "code at %lux", dsp - c->script);
  1413. for (x = 0; x < 6; x++) {
  1414. IPRINT(" %.8lux", dsp[x]);
  1415. }
  1416. IPRINT("\n");
  1417. USED(dsp);
  1418. cont = -2;
  1419. break;
  1420. }
  1421. case A_SIR_NOTIFY_WSR:
  1422. IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
  1423. cont = -2;
  1424. break;
  1425. case A_SIR_NOTIFY_LOAD_SYNC:
  1426. IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
  1427. dsa->target, dsa->lun, n->scntl3, n->sxfer);
  1428. cont = -2;
  1429. break;
  1430. case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
  1431. if (DEBUG(2)) {
  1432. IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
  1433. dsa->target, dsa->lun);
  1434. }
  1435. cont = -2;
  1436. break;
  1437. case A_error_reselected: /* dsa isn't valid here */
  1438. iprint(PRINTPREFIX "reselection error\n");
  1439. dumpncrregs(c, 1);
  1440. for (dsa = KPTR(legetl(c->dsalist.head)); dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
  1441. IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
  1442. }
  1443. break;
  1444. default:
  1445. IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
  1446. dsa->target, dsa->lun, legetl(n->dsps));
  1447. dumpncrregs(c, 1);
  1448. wakeme = 1;
  1449. }
  1450. }
  1451. /*else*/ if (dstat & Iid) {
  1452. int i, target, lun;
  1453. ulong addr, dbc, *v;
  1454. addr = legetl(n->dsp);
  1455. if(dsa){
  1456. target = dsa->target;
  1457. lun = dsa->lun;
  1458. }else{
  1459. target = -1;
  1460. lun = -1;
  1461. }
  1462. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  1463. // if(dsa == nil)
  1464. idebug++;
  1465. IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
  1466. target, lun,
  1467. addr, addr - c->scriptpa, dbc);
  1468. addr = (ulong)c->script + addr - c->scriptpa;
  1469. addr -= 64;
  1470. addr &= ~63;
  1471. v = (ulong*)addr;
  1472. for(i=0; i<8; i++){
  1473. IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n",
  1474. addr, v[0], v[1], v[2], v[3]);
  1475. addr += 4*4;
  1476. v += 4;
  1477. }
  1478. USED(addr, dbc);
  1479. if(dsa == nil){
  1480. dsadump(c);
  1481. dumpncrregs(c, 1);
  1482. panic("bad dsa");
  1483. }
  1484. dsa->p9status = SDeio;
  1485. wakeme = 1;
  1486. }
  1487. /*else*/ if (dstat & Bf) {
  1488. IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
  1489. dumpncrregs(c, 1);
  1490. dsa->p9status = SDeio;
  1491. wakeme = 1;
  1492. }
  1493. }
  1494. if (cont == -2)
  1495. ncrcontinue(c);
  1496. else if (cont >= 0)
  1497. start(c, cont);
  1498. if (wakeme){
  1499. if(dsa->p9status == SDnostatus)
  1500. dsa->p9status = SDeio;
  1501. wakeup(dsa);
  1502. }
  1503. iunlock(c);
  1504. if (DEBUG(1)) {
  1505. IPRINT(PRINTPREFIX "int end 1\n");
  1506. }
  1507. }
  1508. static int
  1509. done(void *arg)
  1510. {
  1511. return ((Dsa *)arg)->p9status != SDnostatus;
  1512. }
  1513. static void
  1514. setmovedata(Movedata *d, ulong pa, ulong bc)
  1515. {
  1516. d->pa[0] = pa;
  1517. d->pa[1] = pa>>8;
  1518. d->pa[2] = pa>>16;
  1519. d->pa[3] = pa>>24;
  1520. d->dbc[0] = bc;
  1521. d->dbc[1] = bc>>8;
  1522. d->dbc[2] = bc>>16;
  1523. d->dbc[3] = bc>>24;
  1524. }
  1525. static void
  1526. advancedata(Movedata *d, long v)
  1527. {
  1528. lesetl(d->pa, legetl(d->pa) + v);
  1529. lesetl(d->dbc, legetl(d->dbc) - v);
  1530. }
  1531. static void
  1532. dumpwritedata(uchar *data, int datalen)
  1533. {
  1534. int i;
  1535. uchar *bp;
  1536. if (!DEBUG(0)){
  1537. USED(data, datalen);
  1538. return;
  1539. }
  1540. if (datalen) {
  1541. KPRINT(PRINTPREFIX "write:");
  1542. for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
  1543. KPRINT("%.2ux", *bp);
  1544. }
  1545. if (i < datalen) {
  1546. KPRINT("...");
  1547. }
  1548. KPRINT("\n");
  1549. }
  1550. }
  1551. static void
  1552. dumpreaddata(uchar *data, int datalen)
  1553. {
  1554. int i;
  1555. uchar *bp;
  1556. if (!DEBUG(0)){
  1557. USED(data, datalen);
  1558. return;
  1559. }
  1560. if (datalen) {
  1561. KPRINT(PRINTPREFIX "read:");
  1562. for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
  1563. KPRINT("%.2ux", *bp);
  1564. }
  1565. if (i < datalen) {
  1566. KPRINT("...");
  1567. }
  1568. KPRINT("\n");
  1569. }
  1570. }
  1571. static void
  1572. busreset(Controller *c)
  1573. {
  1574. int x, ntarget;
  1575. /* bus reset */
  1576. c->n->scntl1 |= (1 << 3);
  1577. delay(500);
  1578. c->n->scntl1 &= ~(1 << 3);
  1579. if(!(c->v->feature & Wide))
  1580. ntarget = 8;
  1581. else
  1582. ntarget = MAXTARGET;
  1583. for (x = 0; x < ntarget; x++) {
  1584. setwide(0, c, x, 0);
  1585. #ifndef ASYNC_ONLY
  1586. c->s[x] = NeitherDone;
  1587. #endif
  1588. }
  1589. c->capvalid = 0;
  1590. }
  1591. static void
  1592. reset(Controller *c)
  1593. {
  1594. /* should wakeup all pending tasks */
  1595. softreset(c);
  1596. busreset(c);
  1597. }
  1598. static int
  1599. sd53c8xxrio(SDreq* r)
  1600. {
  1601. Dsa *d;
  1602. uchar *bp;
  1603. Controller *c;
  1604. uchar target_expo, my_expo;
  1605. int bc, check, i, status, target;
  1606. if((target = r->unit->subno) == 0x07)
  1607. return r->status = SDtimeout; /* assign */
  1608. c = r->unit->dev->ctlr;
  1609. check = 0;
  1610. d = dsaalloc(c, target, r->lun);
  1611. qlock(&c->q[target]); /* obtain access to target */
  1612. docheck:
  1613. /* load the transfer control stuff */
  1614. d->scsi_id_buf[0] = 0;
  1615. d->scsi_id_buf[1] = c->sxfer[target];
  1616. d->scsi_id_buf[2] = target;
  1617. d->scsi_id_buf[3] = c->scntl3[target];
  1618. synctodsa(d, c);
  1619. bc = 0;
  1620. d->msg_out[bc] = 0x80 | r->lun;
  1621. #ifndef NO_DISCONNECT
  1622. d->msg_out[bc] |= (1 << 6);
  1623. #endif
  1624. bc++;
  1625. /* work out what to do about negotiation */
  1626. switch (c->s[target]) {
  1627. default:
  1628. KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
  1629. c->s[target] = NeitherDone;
  1630. /* fall through */
  1631. case NeitherDone:
  1632. if ((c->capvalid & (1 << target)) == 0)
  1633. break;
  1634. target_expo = (c->cap[target] >> 5) & 3;
  1635. my_expo = (c->v->feature & Wide) != 0;
  1636. if (target_expo < my_expo)
  1637. my_expo = target_expo;
  1638. #ifdef ALWAYS_DO_WDTR
  1639. bc += buildwdtrmsg(d->msg_out + bc, my_expo);
  1640. KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
  1641. c->s[target] = WideInit;
  1642. break;
  1643. #else
  1644. if (my_expo) {
  1645. bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
  1646. KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
  1647. c->s[target] = WideInit;
  1648. break;
  1649. }
  1650. KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
  1651. /* fall through */
  1652. #endif
  1653. case WideDone:
  1654. if (c->cap[target] & (1 << 4)) {
  1655. KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
  1656. bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
  1657. c->s[target] = SyncInit;
  1658. break;
  1659. }
  1660. KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
  1661. c->s[target] = BothDone;
  1662. break;
  1663. case BothDone:
  1664. break;
  1665. }
  1666. setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
  1667. setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
  1668. calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
  1669. if (DEBUG(0)) {
  1670. KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
  1671. for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
  1672. KPRINT("%.2ux", *bp);
  1673. }
  1674. KPRINT("\n");
  1675. if (!r->write) {
  1676. KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
  1677. target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
  1678. }
  1679. else
  1680. dumpwritedata(r->data, r->dlen);
  1681. }
  1682. setmovedata(&d->status_buf, DMASEG(&d->status), 1);
  1683. d->p9status = SDnostatus;
  1684. d->parityerror = 0;
  1685. coherence();
  1686. d->stateb = A_STATE_ISSUE; /* start operation */
  1687. coherence();
  1688. ilock(c);
  1689. if (c->ssm)
  1690. c->n->dcntl |= 0x10; /* single step */
  1691. if (c->running) {
  1692. c->n->istat = Sigp;
  1693. }
  1694. else {
  1695. start(c, E_issue_check);
  1696. }
  1697. iunlock(c);
  1698. while(waserror())
  1699. ;
  1700. tsleep(d, done, d, 600 * 1000);
  1701. poperror();
  1702. if (!done(d)) {
  1703. KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
  1704. dumpncrregs(c, 0);
  1705. dsafree(c, d);
  1706. reset(c);
  1707. qunlock(&c->q[target]);
  1708. r->status = SDtimeout;
  1709. return r->status = SDtimeout; /* assign */
  1710. }
  1711. if((status = d->p9status) == SDeio)
  1712. c->s[target] = NeitherDone;
  1713. if (d->parityerror) {
  1714. status = SDeio;
  1715. }
  1716. /*
  1717. * adjust datalen
  1718. */
  1719. r->rlen = r->dlen;
  1720. if (DEBUG(0)) {
  1721. KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
  1722. target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
  1723. }
  1724. r->rlen = r->dlen;
  1725. if (d->flag != 2) {
  1726. r->rlen -= d->dmablks * A_BSIZE;
  1727. r->rlen -= legetl(d->data_buf.dbc);
  1728. }
  1729. if(!r->write)
  1730. dumpreaddata(r->data, r->rlen);
  1731. if (DEBUG(0)) {
  1732. KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
  1733. target, r->lun, d->p9status, status, r->rlen);
  1734. }
  1735. /*
  1736. * spot the identify
  1737. */
  1738. if ((c->capvalid & (1 << target)) == 0
  1739. && (status == SDok || status == SDcheck)
  1740. && r->cmd[0] == 0x12 && r->dlen >= 8) {
  1741. c->capvalid |= 1 << target;
  1742. bp = r->data;
  1743. c->cap[target] = bp[7];
  1744. KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
  1745. }
  1746. if(!check && status == SDcheck && !(r->flags & SDnosense)){
  1747. check = 1;
  1748. r->write = 0;
  1749. memset(r->cmd, 0, sizeof(r->cmd));
  1750. r->cmd[0] = 0x03;
  1751. r->cmd[1] = r->lun<<5;
  1752. r->cmd[4] = sizeof(r->sense)-1;
  1753. r->clen = 6;
  1754. r->data = r->sense;
  1755. r->dlen = sizeof(r->sense)-1;
  1756. /*
  1757. * Clear out the microcode state
  1758. * so the Dsa can be re-used.
  1759. */
  1760. lesetl(&d->stateb, A_STATE_ALLOCATED);
  1761. coherence();
  1762. goto docheck;
  1763. }
  1764. qunlock(&c->q[target]);
  1765. dsafree(c, d);
  1766. if(status == SDok && check){
  1767. status = SDcheck;
  1768. r->flags |= SDvalidsense;
  1769. }
  1770. if(DEBUG(0))
  1771. KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
  1772. target, r->flags, status, r->rlen);
  1773. if(r->flags & SDvalidsense){
  1774. if(!DEBUG(0))
  1775. KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
  1776. target, r->flags, status, r->rlen);
  1777. for(i = 0; i < r->rlen; i++)
  1778. KPRINT(" %2.2uX", r->sense[i]);
  1779. KPRINT("\n");
  1780. }
  1781. return r->status = status;
  1782. }
  1783. #define vpt ((ulong*)VPT)
  1784. #define VPTX(va) (((ulong)(va))>>12)
  1785. static void
  1786. cribbios(Controller *c)
  1787. {
  1788. c->bios.scntl3 = c->n->scntl3;
  1789. c->bios.stest2 = c->n->stest2;
  1790. print(PRINTPREFIX "bios scntl3(%.2x) stest2(%.2x)\n", c->bios.scntl3, c->bios.stest2);
  1791. }
  1792. static int
  1793. bios_set_differential(Controller *c)
  1794. {
  1795. /* Concept lifted from FreeBSD - thanks Gerard */
  1796. /* basically, if clock conversion factors are set, then there is
  1797. * evidence the bios had a go at the chip, and if so, it would
  1798. * have set the differential enable bit in stest2
  1799. */
  1800. return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
  1801. }
  1802. #define NCR_VID 0x1000
  1803. #define NCR_810_DID 0x0001
  1804. #define NCR_820_DID 0x0002 /* don't know enough about this one to support it */
  1805. #define NCR_825_DID 0x0003
  1806. #define NCR_815_DID 0x0004
  1807. #define SYM_810AP_DID 0x0005
  1808. #define SYM_860_DID 0x0006
  1809. #define SYM_896_DID 0x000b
  1810. #define SYM_895_DID 0x000c
  1811. #define SYM_885_DID 0x000d /* ditto */
  1812. #define SYM_875_DID 0x000f /* ditto */
  1813. #define SYM_1010_DID 0x0020
  1814. #define SYM_1011_DID 0x0021
  1815. #define SYM_875J_DID 0x008f
  1816. static Variant variant[] = {
  1817. { NCR_810_DID, 0x0f, "NCR53C810", Burst16, 8, 24, 0 },
  1818. { NCR_810_DID, 0x1f, "SYM53C810ALV", Burst16, 8, 24, Prefetch },
  1819. { NCR_810_DID, 0xff, "SYM53C810A", Burst16, 8, 24, Prefetch },
  1820. { SYM_810AP_DID, 0xff, "SYM53C810AP", Burst16, 8, 24, Prefetch },
  1821. { NCR_815_DID, 0xff, "NCR53C815", Burst16, 8, 24, BurstOpCodeFetch },
  1822. { NCR_825_DID, 0x0f, "NCR53C825", Burst16, 8, 24, Wide|BurstOpCodeFetch|Differential },
  1823. { NCR_825_DID, 0xff, "SYM53C825A", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
  1824. { SYM_860_DID, 0x0f, "SYM53C860", Burst16, 8, 24, Prefetch|Ultra },
  1825. { SYM_860_DID, 0xff, "SYM53C860LV", Burst16, 8, 24, Prefetch|Ultra },
  1826. { SYM_875_DID, 0x01, "SYM53C875r1", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
  1827. { SYM_875_DID, 0xff, "SYM53C875", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
  1828. { SYM_875J_DID, 0xff, "SYM53C875j", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
  1829. { SYM_885_DID, 0xff, "SYM53C885", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
  1830. { SYM_895_DID, 0xff, "SYM53C895", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1831. { SYM_896_DID, 0xff, "SYM53C896", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1832. { SYM_1010_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1833. { SYM_1011_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1834. };
  1835. static int
  1836. xfunc(Controller *c, enum na_external x, unsigned long *v)
  1837. {
  1838. switch (x)
  1839. {
  1840. case X_scsi_id_buf:
  1841. *v = offsetof(Dsa, scsi_id_buf[0]); return 1;
  1842. case X_msg_out_buf:
  1843. *v = offsetof(Dsa, msg_out_buf); return 1;
  1844. case X_cmd_buf:
  1845. *v = offsetof(Dsa, cmd_buf); return 1;
  1846. case X_data_buf:
  1847. *v = offsetof(Dsa, data_buf); return 1;
  1848. case X_status_buf:
  1849. *v = offsetof(Dsa, status_buf); return 1;
  1850. case X_dsa_head:
  1851. *v = DMASEG(&c->dsalist.head[0]); return 1;
  1852. case X_ssid_mask:
  1853. *v = SSIDMASK(c); return 1;
  1854. default:
  1855. print("xfunc: can't find external %d\n", x);
  1856. return 0;
  1857. }
  1858. return 1;
  1859. }
  1860. static int
  1861. na_fixup(Controller *c, ulong pa_reg,
  1862. struct na_patch *patch, int patches,
  1863. int (*externval)(Controller*, int, ulong*))
  1864. {
  1865. int p;
  1866. int v;
  1867. ulong *script, pa_script;
  1868. unsigned long lw, lv;
  1869. script = c->script;
  1870. pa_script = c->scriptpa;
  1871. for (p = 0; p < patches; p++) {
  1872. switch (patch[p].type) {
  1873. case 1:
  1874. /* script relative */
  1875. script[patch[p].lwoff] += pa_script;
  1876. break;
  1877. case 2:
  1878. /* register i/o relative */
  1879. script[patch[p].lwoff] += pa_reg;
  1880. break;
  1881. case 3:
  1882. /* data external */
  1883. lw = script[patch[p].lwoff];
  1884. v = (lw >> 8) & 0xff;
  1885. if (!(*externval)(c, v, &lv))
  1886. return 0;
  1887. v = lv & 0xff;
  1888. script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
  1889. break;
  1890. case 4:
  1891. /* 32 bit external */
  1892. lw = script[patch[p].lwoff];
  1893. if (!(*externval)(c, lw, &lv))
  1894. return 0;
  1895. script[patch[p].lwoff] = lv;
  1896. break;
  1897. case 5:
  1898. /* 24 bit external */
  1899. lw = script[patch[p].lwoff];
  1900. if (!(*externval)(c, lw & 0xffffff, &lv))
  1901. return 0;
  1902. script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
  1903. break;
  1904. }
  1905. }
  1906. return 1;
  1907. }
  1908. static SDev*
  1909. sd53c8xxpnp(void)
  1910. {
  1911. char *cp;
  1912. Pcidev *p;
  1913. Variant *v;
  1914. int ba, nctlr;
  1915. void *scriptma;
  1916. Controller *ctlr;
  1917. SDev *sdev, *head, *tail;
  1918. ulong regpa, *script, scriptpa;
  1919. void *regva, *scriptva;
  1920. if(cp = getconf("*maxsd53c8xx"))
  1921. nctlr = strtoul(cp, 0, 0);
  1922. else
  1923. nctlr = 32;
  1924. p = nil;
  1925. head = tail = nil;
  1926. while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
  1927. for(v = variant; v < &variant[nelem(variant)]; v++){
  1928. if(p->did == v->did && p->rid <= v->maxrid)
  1929. break;
  1930. }
  1931. if(v >= &variant[nelem(variant)]) {
  1932. print("no match\n");
  1933. continue;
  1934. }
  1935. print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
  1936. v->name, p->rid, p->intl, p->pcr);
  1937. regpa = p->mem[1].bar;
  1938. ba = 2;
  1939. if(regpa & 0x04){
  1940. if(p->mem[2].bar)
  1941. continue;
  1942. ba++;
  1943. }
  1944. if(regpa == 0)
  1945. print("regpa 0\n");
  1946. regpa &= ~0xF;
  1947. regva = vmap(regpa, p->mem[1].size);
  1948. if(regva == 0)
  1949. continue;
  1950. script = nil;
  1951. scriptpa = 0;
  1952. scriptva = nil;
  1953. scriptma = nil;
  1954. if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
  1955. scriptpa = p->mem[ba].bar;
  1956. if((scriptpa & 0x04) && p->mem[ba+1].bar){
  1957. vunmap(regva, p->mem[1].size);
  1958. continue;
  1959. }
  1960. scriptpa &= ~0x0F;
  1961. scriptva = vmap(scriptpa, p->mem[ba].size);
  1962. if(scriptva)
  1963. script = scriptva;
  1964. }
  1965. if(scriptpa == 0){
  1966. /*
  1967. * Either the map failed, or this chip does not have
  1968. * local RAM. It will need a copy of the microcode.
  1969. */
  1970. scriptma = malloc(sizeof(na_script));
  1971. if(scriptma == nil){
  1972. vunmap(regva, p->mem[1].size);
  1973. continue;
  1974. }
  1975. scriptpa = DMASEG(scriptma);
  1976. script = scriptma;
  1977. }
  1978. ctlr = malloc(sizeof(Controller));
  1979. sdev = malloc(sizeof(SDev));
  1980. if(ctlr == nil || sdev == nil){
  1981. buggery:
  1982. if(ctlr)
  1983. free(ctlr);
  1984. if(sdev)
  1985. free(sdev);
  1986. if(scriptma)
  1987. free(scriptma);
  1988. else if(scriptva)
  1989. vunmap(scriptva, p->mem[ba].size);
  1990. if(regva)
  1991. vunmap(regva, p->mem[1].size);
  1992. continue;
  1993. }
  1994. if(dsaend == nil)
  1995. dsaend = xalloc(sizeof *dsaend);
  1996. lesetl(&dsaend->stateb, A_STATE_END);
  1997. // lesetl(dsaend->next, DMASEG(dsaend));
  1998. coherence();
  1999. lesetl(ctlr->dsalist.head, DMASEG(dsaend));
  2000. coherence();
  2001. ctlr->dsalist.freechain = 0;
  2002. ctlr->n = regva;
  2003. ctlr->v = v;
  2004. ctlr->script = script;
  2005. memmove(ctlr->script, na_script, sizeof(na_script));
  2006. /*
  2007. * Because we don't yet have an abstraction for the
  2008. * addresses as seen from the controller side (and on
  2009. * the 386 it doesn't matter), the following three lines
  2010. * are different between the 386 and alpha copies of
  2011. * this driver.
  2012. */
  2013. USED(scriptpa);
  2014. ctlr->scriptpa = p->mem[ba].bar & ~0x0F;
  2015. if(!na_fixup(ctlr, p->mem[1].bar & ~0x0F, na_patches, NA_PATCHES, xfunc)){
  2016. print("script fixup failed\n");
  2017. goto buggery;
  2018. }
  2019. swabl(ctlr->script, ctlr->script, sizeof(na_script));
  2020. ctlr->pcidev = p;
  2021. sdev->ifc = &sd53c8xxifc;
  2022. sdev->ctlr = ctlr;
  2023. sdev->idno = '0';
  2024. if(!(v->feature & Wide))
  2025. sdev->nunit = 8;
  2026. else
  2027. sdev->nunit = MAXTARGET;
  2028. ctlr->sdev = sdev;
  2029. if(head != nil)
  2030. tail->next = sdev;
  2031. else
  2032. head = sdev;
  2033. tail = sdev;
  2034. nctlr--;
  2035. }
  2036. return head;
  2037. }
  2038. static int
  2039. sd53c8xxenable(SDev* sdev)
  2040. {
  2041. Pcidev *pcidev;
  2042. Controller *ctlr;
  2043. char name[32];
  2044. ctlr = sdev->ctlr;
  2045. pcidev = ctlr->pcidev;
  2046. pcisetbme(pcidev);
  2047. ilock(ctlr);
  2048. synctabinit(ctlr);
  2049. cribbios(ctlr);
  2050. reset(ctlr);
  2051. snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
  2052. intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
  2053. iunlock(ctlr);
  2054. return 1;
  2055. }
  2056. SDifc sd53c8xxifc = {
  2057. "53c8xx", /* name */
  2058. sd53c8xxpnp, /* pnp */
  2059. nil, /* legacy */
  2060. sd53c8xxenable, /* enable */
  2061. nil, /* disable */
  2062. scsiverify, /* verify */
  2063. scsionline, /* online */
  2064. sd53c8xxrio, /* rio */
  2065. nil, /* rctl */
  2066. nil, /* wctl */
  2067. scsibio, /* bio */
  2068. nil, /* probe */
  2069. nil, /* clear */
  2070. nil, /* stat */
  2071. };