devarch.c 19 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "ureg.h"
  8. #include "../port/error.h"
  9. typedef struct IOMap IOMap;
  10. struct IOMap
  11. {
  12. IOMap *next;
  13. int reserved;
  14. char tag[13];
  15. ulong start;
  16. ulong end;
  17. };
  18. static struct
  19. {
  20. Lock;
  21. IOMap *m;
  22. IOMap *free;
  23. IOMap maps[32]; // some initial free maps
  24. QLock ql; // lock for reading map
  25. } iomap;
  26. enum {
  27. Qdir = 0,
  28. Qioalloc = 1,
  29. Qiob,
  30. Qiow,
  31. Qiol,
  32. Qbase,
  33. Qmax = 16,
  34. };
  35. typedef long Rdwrfn(Chan*, void*, long, vlong);
  36. static Rdwrfn *readfn[Qmax];
  37. static Rdwrfn *writefn[Qmax];
  38. static Dirtab archdir[Qmax] = {
  39. ".", { Qdir, 0, QTDIR }, 0, 0555,
  40. "ioalloc", { Qioalloc, 0 }, 0, 0444,
  41. "iob", { Qiob, 0 }, 0, 0660,
  42. "iow", { Qiow, 0 }, 0, 0660,
  43. "iol", { Qiol, 0 }, 0, 0660,
  44. };
  45. Lock archwlock; /* the lock is only for changing archdir */
  46. int narchdir = Qbase;
  47. int (*_pcmspecial)(char*, ISAConf*);
  48. void (*_pcmspecialclose)(int);
  49. static int doi8253set = 1;
  50. /*
  51. * Add a file to the #P listing. Once added, you can't delete it.
  52. * You can't add a file with the same name as one already there,
  53. * and you get a pointer to the Dirtab entry so you can do things
  54. * like change the Qid version. Changing the Qid path is disallowed.
  55. */
  56. Dirtab*
  57. addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
  58. {
  59. int i;
  60. Dirtab d;
  61. Dirtab *dp;
  62. memset(&d, 0, sizeof d);
  63. strcpy(d.name, name);
  64. d.perm = perm;
  65. lock(&archwlock);
  66. if(narchdir >= Qmax){
  67. unlock(&archwlock);
  68. return nil;
  69. }
  70. for(i=0; i<narchdir; i++)
  71. if(strcmp(archdir[i].name, name) == 0){
  72. unlock(&archwlock);
  73. return nil;
  74. }
  75. d.qid.path = narchdir;
  76. archdir[narchdir] = d;
  77. readfn[narchdir] = rdfn;
  78. writefn[narchdir] = wrfn;
  79. dp = &archdir[narchdir++];
  80. unlock(&archwlock);
  81. return dp;
  82. }
  83. void
  84. ioinit(void)
  85. {
  86. char *excluded;
  87. int i;
  88. for(i = 0; i < nelem(iomap.maps)-1; i++)
  89. iomap.maps[i].next = &iomap.maps[i+1];
  90. iomap.maps[i].next = nil;
  91. iomap.free = iomap.maps;
  92. /*
  93. * This is necessary to make the IBM X20 boot.
  94. * Have not tracked down the reason.
  95. */
  96. ioalloc(0x0fff, 1, 0, "dummy"); // i82557 is at 0x1000, the dummy
  97. // entry is needed for swappable devs.
  98. if ((excluded = getconf("ioexclude")) != nil) {
  99. char *s;
  100. s = excluded;
  101. while (s && *s != '\0' && *s != '\n') {
  102. char *ends;
  103. int io_s, io_e;
  104. io_s = (int)strtol(s, &ends, 0);
  105. if (ends == nil || ends == s || *ends != '-') {
  106. print("ioinit: cannot parse option string\n");
  107. break;
  108. }
  109. s = ++ends;
  110. io_e = (int)strtol(s, &ends, 0);
  111. if (ends && *ends == ',')
  112. *ends++ = '\0';
  113. s = ends;
  114. ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
  115. }
  116. }
  117. }
  118. // Reserve a range to be ioalloced later.
  119. // This is in particular useful for exchangable cards, such
  120. // as pcmcia and cardbus cards.
  121. int
  122. ioreserve(int, int size, int align, char *tag)
  123. {
  124. IOMap *m, **l;
  125. int i, port;
  126. lock(&iomap);
  127. // find a free port above 0x400 and below 0x1000
  128. port = 0x400;
  129. for(l = &iomap.m; *l; l = &(*l)->next){
  130. m = *l;
  131. if (m->start < 0x400) continue;
  132. i = m->start - port;
  133. if(i > size)
  134. break;
  135. if(align > 0)
  136. port = ((port+align-1)/align)*align;
  137. else
  138. port = m->end;
  139. }
  140. if(*l == nil){
  141. unlock(&iomap);
  142. return -1;
  143. }
  144. m = iomap.free;
  145. if(m == nil){
  146. print("ioalloc: out of maps");
  147. unlock(&iomap);
  148. return port;
  149. }
  150. iomap.free = m->next;
  151. m->next = *l;
  152. m->start = port;
  153. m->end = port + size;
  154. m->reserved = 1;
  155. strncpy(m->tag, tag, sizeof(m->tag));
  156. m->tag[sizeof(m->tag)-1] = 0;
  157. *l = m;
  158. archdir[0].qid.vers++;
  159. unlock(&iomap);
  160. return m->start;
  161. }
  162. //
  163. // alloc some io port space and remember who it was
  164. // alloced to. if port < 0, find a free region.
  165. //
  166. int
  167. ioalloc(int port, int size, int align, char *tag)
  168. {
  169. IOMap *m, **l;
  170. int i;
  171. lock(&iomap);
  172. if(port < 0){
  173. // find a free port above 0x400 and below 0x1000
  174. port = 0x400;
  175. for(l = &iomap.m; *l; l = &(*l)->next){
  176. m = *l;
  177. if (m->start < 0x400) continue;
  178. i = m->start - port;
  179. if(i > size)
  180. break;
  181. if(align > 0)
  182. port = ((port+align-1)/align)*align;
  183. else
  184. port = m->end;
  185. }
  186. if(*l == nil){
  187. unlock(&iomap);
  188. return -1;
  189. }
  190. } else {
  191. // Only 64KB I/O space on the x86.
  192. if((port+size) > 0x10000){
  193. unlock(&iomap);
  194. return -1;
  195. }
  196. // see if the space clashes with previously allocated ports
  197. for(l = &iomap.m; *l; l = &(*l)->next){
  198. m = *l;
  199. if(m->end <= port)
  200. continue;
  201. if(m->reserved && m->start == port && m->end == port + size) {
  202. m->reserved = 0;
  203. unlock(&iomap);
  204. return m->start;
  205. }
  206. if(m->start >= port+size)
  207. break;
  208. unlock(&iomap);
  209. return -1;
  210. }
  211. }
  212. m = iomap.free;
  213. if(m == nil){
  214. print("ioalloc: out of maps");
  215. unlock(&iomap);
  216. return port;
  217. }
  218. iomap.free = m->next;
  219. m->next = *l;
  220. m->start = port;
  221. m->end = port + size;
  222. strncpy(m->tag, tag, sizeof(m->tag));
  223. m->tag[sizeof(m->tag)-1] = 0;
  224. *l = m;
  225. archdir[0].qid.vers++;
  226. unlock(&iomap);
  227. return m->start;
  228. }
  229. void
  230. iofree(int port)
  231. {
  232. IOMap *m, **l;
  233. lock(&iomap);
  234. for(l = &iomap.m; *l; l = &(*l)->next){
  235. if((*l)->start == port){
  236. m = *l;
  237. *l = m->next;
  238. m->next = iomap.free;
  239. iomap.free = m;
  240. break;
  241. }
  242. if((*l)->start > port)
  243. break;
  244. }
  245. archdir[0].qid.vers++;
  246. unlock(&iomap);
  247. }
  248. int
  249. iounused(int start, int end)
  250. {
  251. IOMap *m;
  252. for(m = iomap.m; m; m = m->next){
  253. if(start >= m->start && start < m->end
  254. || start <= m->start && end > m->start)
  255. return 0;
  256. }
  257. return 1;
  258. }
  259. static void
  260. checkport(int start, int end)
  261. {
  262. /* standard vga regs are OK */
  263. if(start >= 0x2b0 && end <= 0x2df+1)
  264. return;
  265. if(start >= 0x3c0 && end <= 0x3da+1)
  266. return;
  267. if(iounused(start, end))
  268. return;
  269. error(Eperm);
  270. }
  271. static Chan*
  272. archattach(char* spec)
  273. {
  274. return devattach('P', spec);
  275. }
  276. Walkqid*
  277. archwalk(Chan* c, Chan *nc, char** name, int nname)
  278. {
  279. return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
  280. }
  281. static int
  282. archstat(Chan* c, uchar* dp, int n)
  283. {
  284. return devstat(c, dp, n, archdir, narchdir, devgen);
  285. }
  286. static Chan*
  287. archopen(Chan* c, int omode)
  288. {
  289. return devopen(c, omode, archdir, narchdir, devgen);
  290. }
  291. static void
  292. archclose(Chan*)
  293. {
  294. }
  295. enum
  296. {
  297. Linelen= 31,
  298. };
  299. static long
  300. archread(Chan *c, void *a, long n, vlong offset)
  301. {
  302. char *buf, *p;
  303. int port;
  304. ushort *sp;
  305. ulong *lp;
  306. IOMap *m;
  307. Rdwrfn *fn;
  308. switch((ulong)c->qid.path){
  309. case Qdir:
  310. return devdirread(c, a, n, archdir, narchdir, devgen);
  311. case Qiob:
  312. port = offset;
  313. checkport(offset, offset+n);
  314. for(p = a; port < offset+n; port++)
  315. *p++ = inb(port);
  316. return n;
  317. case Qiow:
  318. if(n & 1)
  319. error(Ebadarg);
  320. checkport(offset, offset+n);
  321. sp = a;
  322. for(port = offset; port < offset+n; port += 2)
  323. *sp++ = ins(port);
  324. return n;
  325. case Qiol:
  326. if(n & 3)
  327. error(Ebadarg);
  328. checkport(offset, offset+n);
  329. lp = a;
  330. for(port = offset; port < offset+n; port += 4)
  331. *lp++ = inl(port);
  332. return n;
  333. case Qioalloc:
  334. break;
  335. default:
  336. if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
  337. return fn(c, a, n, offset);
  338. error(Eperm);
  339. break;
  340. }
  341. if((buf = malloc(n)) == nil)
  342. error(Enomem);
  343. p = buf;
  344. n = n/Linelen;
  345. offset = offset/Linelen;
  346. lock(&iomap);
  347. for(m = iomap.m; n > 0 && m != nil; m = m->next){
  348. if(offset-- > 0)
  349. continue;
  350. sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
  351. p += Linelen;
  352. n--;
  353. }
  354. unlock(&iomap);
  355. n = p - buf;
  356. memmove(a, buf, n);
  357. free(buf);
  358. return n;
  359. }
  360. static long
  361. archwrite(Chan *c, void *a, long n, vlong offset)
  362. {
  363. char *p;
  364. int port;
  365. ushort *sp;
  366. ulong *lp;
  367. Rdwrfn *fn;
  368. switch((ulong)c->qid.path){
  369. case Qiob:
  370. p = a;
  371. checkport(offset, offset+n);
  372. for(port = offset; port < offset+n; port++)
  373. outb(port, *p++);
  374. return n;
  375. case Qiow:
  376. if(n & 1)
  377. error(Ebadarg);
  378. checkport(offset, offset+n);
  379. sp = a;
  380. for(port = offset; port < offset+n; port += 2)
  381. outs(port, *sp++);
  382. return n;
  383. case Qiol:
  384. if(n & 3)
  385. error(Ebadarg);
  386. checkport(offset, offset+n);
  387. lp = a;
  388. for(port = offset; port < offset+n; port += 4)
  389. outl(port, *lp++);
  390. return n;
  391. default:
  392. if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
  393. return fn(c, a, n, offset);
  394. error(Eperm);
  395. break;
  396. }
  397. return 0;
  398. }
  399. Dev archdevtab = {
  400. 'P',
  401. "arch",
  402. devreset,
  403. devinit,
  404. devshutdown,
  405. archattach,
  406. archwalk,
  407. archstat,
  408. archopen,
  409. devcreate,
  410. archclose,
  411. archread,
  412. devbread,
  413. archwrite,
  414. devbwrite,
  415. devremove,
  416. devwstat,
  417. };
  418. /*
  419. * the following is a generic version of the
  420. * architecture specific stuff
  421. */
  422. static int
  423. unimplemented(int)
  424. {
  425. return 0;
  426. }
  427. static void
  428. nop(void)
  429. {
  430. }
  431. /*
  432. * 386 has no compare-and-swap instruction.
  433. * Run it with interrupts turned off instead.
  434. */
  435. static int
  436. cmpswap386(long *addr, long old, long new)
  437. {
  438. int r, s;
  439. s = splhi();
  440. if(r = (*addr == old))
  441. *addr = new;
  442. splx(s);
  443. return r;
  444. }
  445. /*
  446. * On a uniprocessor, you'd think that coherence could be nop,
  447. * but it can't. We still need a barrier when using coherence() in
  448. * device drivers.
  449. *
  450. * On VMware, it's safe (and a huge win) to set this to nop.
  451. * Aux/vmware does this via the #P/archctl file.
  452. */
  453. void (*coherence)(void) = nop;
  454. int (*cmpswap)(long*, long, long) = cmpswap386;
  455. PCArch* arch;
  456. extern PCArch* knownarch[];
  457. PCArch archgeneric = {
  458. .id= "generic",
  459. .ident= 0,
  460. .reset= i8042reset,
  461. .serialpower= unimplemented,
  462. .modempower= unimplemented,
  463. .intrinit= i8259init,
  464. .intrenable= i8259enable,
  465. .intrvecno= i8259vecno,
  466. .intrdisable= i8259disable,
  467. .intron= i8259on,
  468. .introff= i8259off,
  469. .clockenable= i8253enable,
  470. .fastclock= i8253read,
  471. .timerset= i8253timerset,
  472. };
  473. typedef struct X86type X86type;
  474. struct X86type {
  475. int family;
  476. int model;
  477. int aalcycles;
  478. char* name;
  479. };
  480. static X86type x86intel[] =
  481. {
  482. { 4, 0, 22, "486DX", }, /* known chips */
  483. { 4, 1, 22, "486DX50", },
  484. { 4, 2, 22, "486SX", },
  485. { 4, 3, 22, "486DX2", },
  486. { 4, 4, 22, "486SL", },
  487. { 4, 5, 22, "486SX2", },
  488. { 4, 7, 22, "DX2WB", }, /* P24D */
  489. { 4, 8, 22, "DX4", }, /* P24C */
  490. { 4, 9, 22, "DX4WB", }, /* P24CT */
  491. { 5, 0, 23, "P5", },
  492. { 5, 1, 23, "P5", },
  493. { 5, 2, 23, "P54C", },
  494. { 5, 3, 23, "P24T", },
  495. { 5, 4, 23, "P55C MMX", },
  496. { 5, 7, 23, "P54C VRT", },
  497. { 6, 1, 16, "PentiumPro", },/* trial and error */
  498. { 6, 3, 16, "PentiumII", },
  499. { 6, 5, 16, "PentiumII/Xeon", },
  500. { 6, 6, 16, "Celeron", },
  501. { 6, 7, 16, "PentiumIII/Xeon", },
  502. { 6, 8, 16, "PentiumIII/Xeon", },
  503. { 6, 0xB, 16, "PentiumIII/Xeon", },
  504. { 0xF, 1, 16, "P4", }, /* P4 */
  505. { 0xF, 2, 16, "PentiumIV/Xeon", },
  506. { 3, -1, 32, "386", }, /* family defaults */
  507. { 4, -1, 22, "486", },
  508. { 5, -1, 23, "P5", },
  509. { 6, -1, 16, "P6", },
  510. { 0xF, -1, 16, "P4", }, /* P4 */
  511. { -1, -1, 16, "unknown", }, /* total default */
  512. };
  513. /*
  514. * The AMD processors all implement the CPUID instruction.
  515. * The later ones also return the processor name via functions
  516. * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
  517. * and DX:
  518. * K5 "AMD-K5(tm) Processor"
  519. * K6 "AMD-K6tm w/ multimedia extensions"
  520. * K6 3D "AMD-K6(tm) 3D processor"
  521. * K6 3D+ ?
  522. */
  523. static X86type x86amd[] =
  524. {
  525. { 5, 0, 23, "AMD-K5", }, /* guesswork */
  526. { 5, 1, 23, "AMD-K5", }, /* guesswork */
  527. { 5, 2, 23, "AMD-K5", }, /* guesswork */
  528. { 5, 3, 23, "AMD-K5", }, /* guesswork */
  529. { 5, 6, 11, "AMD-K6", }, /* trial and error */
  530. { 5, 7, 11, "AMD-K6", }, /* trial and error */
  531. { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
  532. { 5, 9, 11, "AMD-K6-III", },/* trial and error */
  533. { 6, 1, 11, "AMD-Athlon", },/* trial and error */
  534. { 6, 2, 11, "AMD-Athlon", },/* trial and error */
  535. { 4, -1, 22, "Am486", }, /* guesswork */
  536. { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
  537. { 6, -1, 11, "AMD-Athlon", },/* guesswork */
  538. { 0xF, -1, 11, "AMD64", }, /* guesswork */
  539. { -1, -1, 11, "unknown", }, /* total default */
  540. };
  541. /*
  542. * WinChip 240MHz
  543. */
  544. static X86type x86winchip[] =
  545. {
  546. {5, 4, 23, "Winchip",}, /* guesswork */
  547. {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
  548. {6, 8, 23, "Via C3 Ezra-T",},
  549. {6, 9, 23, "Via C3 Eden-N",},
  550. { -1, -1, 23, "unknown", }, /* total default */
  551. };
  552. /*
  553. * SiS 55x
  554. */
  555. static X86type x86sis[] =
  556. {
  557. {5, 0, 23, "SiS 55x",}, /* guesswork */
  558. { -1, -1, 23, "unknown", }, /* total default */
  559. };
  560. static X86type *cputype;
  561. static void simplecycles(uvlong*);
  562. void (*cycles)(uvlong*) = simplecycles;
  563. void _cycles(uvlong*); /* in l.s */
  564. static void
  565. simplecycles(uvlong*x)
  566. {
  567. *x = m->ticks;
  568. }
  569. void
  570. cpuidprint(void)
  571. {
  572. int i;
  573. char buf[128];
  574. i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
  575. if(m->cpuidid[0])
  576. i += sprint(buf+i, "%12.12s ", m->cpuidid);
  577. seprint(buf+i, buf + sizeof buf - 1,
  578. "%s (cpuid: AX 0x%4.4uX DX 0x%4.4uX)\n",
  579. m->cpuidtype, m->cpuidax, m->cpuiddx);
  580. print(buf);
  581. }
  582. /*
  583. * figure out:
  584. * - cpu type
  585. * - whether or not we have a TSC (cycle counter)
  586. * - whether or not it supports page size extensions
  587. * (if so turn it on)
  588. * - whether or not it supports machine check exceptions
  589. * (if so turn it on)
  590. * - whether or not it supports the page global flag
  591. * (if so turn it on)
  592. */
  593. int
  594. cpuidentify(void)
  595. {
  596. char *p;
  597. int family, model, nomce;
  598. X86type *t, *tab;
  599. ulong cr4;
  600. vlong mca, mct;
  601. cpuid(m->cpuidid, &m->cpuidax, &m->cpuiddx);
  602. if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0)
  603. tab = x86amd;
  604. else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
  605. tab = x86winchip;
  606. else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
  607. tab = x86sis;
  608. else
  609. tab = x86intel;
  610. family = X86FAMILY(m->cpuidax);
  611. model = X86MODEL(m->cpuidax);
  612. for(t=tab; t->name; t++)
  613. if((t->family == family && t->model == model)
  614. || (t->family == family && t->model == -1)
  615. || (t->family == -1))
  616. break;
  617. m->cpuidtype = t->name;
  618. /*
  619. * if there is one, set tsc to a known value
  620. */
  621. if(m->cpuiddx & 0x10){
  622. m->havetsc = 1;
  623. cycles = _cycles;
  624. if(m->cpuiddx & 0x20)
  625. wrmsr(0x10, 0);
  626. }
  627. /*
  628. * use i8253 to guess our cpu speed
  629. */
  630. guesscpuhz(t->aalcycles);
  631. /*
  632. * If machine check exception, page size extensions or page global bit
  633. * are supported enable them in CR4 and clear any other set extensions.
  634. * If machine check was enabled clear out any lingering status.
  635. */
  636. if(m->cpuiddx & 0x2088){
  637. cr4 = 0;
  638. if(m->cpuiddx & 0x08)
  639. cr4 |= 0x10; /* page size extensions */
  640. if(p = getconf("*nomce"))
  641. nomce = strtoul(p, 0, 0);
  642. else
  643. nomce = 0;
  644. if((m->cpuiddx & 0x80) && !nomce){
  645. cr4 |= 0x40; /* machine check enable */
  646. if(family == 5){
  647. rdmsr(0x00, &mca);
  648. rdmsr(0x01, &mct);
  649. }
  650. }
  651. /*
  652. * Detect whether the chip supports the global bit
  653. * in page directory and page table entries. When set
  654. * in a particular entry, it means ``don't bother removing
  655. * this from the TLB when CR3 changes.''
  656. *
  657. * We flag all kernel pages with this bit. Doing so lessens the
  658. * overhead of switching processes on bare hardware,
  659. * even more so on VMware. See mmu.c:/^memglobal.
  660. *
  661. * For future reference, should we ever need to do a
  662. * full TLB flush, it can be accomplished by clearing
  663. * the PGE bit in CR4, writing to CR3, and then
  664. * restoring the PGE bit.
  665. */
  666. if(m->cpuiddx & 0x2000){
  667. cr4 |= 0x80; /* page global enable bit */
  668. m->havepge = 1;
  669. }
  670. putcr4(cr4);
  671. if(m->cpuiddx & 0x80)
  672. rdmsr(0x01, &mct);
  673. }
  674. cputype = t;
  675. return t->family;
  676. }
  677. static long
  678. cputyperead(Chan*, void *a, long n, vlong offset)
  679. {
  680. char str[32];
  681. ulong mhz;
  682. mhz = (m->cpuhz+999999)/1000000;
  683. snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
  684. return readstr(offset, a, n, str);
  685. }
  686. static long
  687. archctlread(Chan*, void *a, long nn, vlong offset)
  688. {
  689. char buf[256];
  690. int n;
  691. n = snprint(buf, sizeof buf, "cpu %s %lud%s\n",
  692. cputype->name, (ulong)(m->cpuhz+999999)/1000000,
  693. m->havepge ? " pge" : "");
  694. n += snprint(buf+n, sizeof buf-n, "pge %s\n", getcr4()&0x80 ? "on" : "off");
  695. n += snprint(buf+n, sizeof buf-n, "coherence ");
  696. if(coherence == mb386)
  697. n += snprint(buf+n, sizeof buf-n, "mb386\n");
  698. else if(coherence == mb586)
  699. n += snprint(buf+n, sizeof buf-n, "mb586\n");
  700. else if(coherence == nop)
  701. n += snprint(buf+n, sizeof buf-n, "nop\n");
  702. else
  703. n += snprint(buf+n, sizeof buf-n, "0x%p\n", coherence);
  704. n += snprint(buf+n, sizeof buf-n, "cmpswap ");
  705. if(cmpswap == cmpswap386)
  706. n += snprint(buf+n, sizeof buf-n, "cmpswap386\n");
  707. else if(cmpswap == cmpswap486)
  708. n += snprint(buf+n, sizeof buf-n, "cmpswap486\n");
  709. else
  710. n += snprint(buf+n, sizeof buf-n, "0x%p\n", cmpswap);
  711. n += snprint(buf+n, sizeof buf-n, "i8253set %s\n", doi8253set ? "on" : "off");
  712. buf[n] = 0;
  713. return readstr(offset, a, nn, buf);
  714. }
  715. enum
  716. {
  717. CMpge,
  718. CMcoherence,
  719. CMi8253set,
  720. };
  721. static Cmdtab archctlmsg[] =
  722. {
  723. CMpge, "pge", 2,
  724. CMcoherence, "coherence", 2,
  725. CMi8253set, "i8253set", 2,
  726. };
  727. static long
  728. archctlwrite(Chan*, void *a, long n, vlong)
  729. {
  730. Cmdbuf *cb;
  731. Cmdtab *ct;
  732. cb = parsecmd(a, n);
  733. if(waserror()){
  734. free(cb);
  735. nexterror();
  736. }
  737. ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
  738. switch(ct->index){
  739. case CMpge:
  740. if(!m->havepge)
  741. error("processor does not support pge");
  742. if(strcmp(cb->f[1], "on") == 0)
  743. putcr4(getcr4() | 0x80);
  744. else if(strcmp(cb->f[1], "off") == 0)
  745. putcr4(getcr4() & ~0x80);
  746. else
  747. cmderror(cb, "invalid pge ctl");
  748. break;
  749. case CMcoherence:
  750. if(strcmp(cb->f[1], "mb386") == 0)
  751. coherence = mb386;
  752. else if(strcmp(cb->f[1], "mb586") == 0){
  753. if(X86FAMILY(m->cpuidax) < 5)
  754. error("invalid coherence ctl on this cpu family");
  755. coherence = mb586;
  756. }
  757. else if(strcmp(cb->f[1], "nop") == 0){
  758. /* only safe on vmware */
  759. if(conf.nmach > 1)
  760. error("cannot disable coherence on a multiprocessor");
  761. coherence = nop;
  762. }else
  763. cmderror(cb, "invalid coherence ctl");
  764. break;
  765. case CMi8253set:
  766. if(strcmp(cb->f[1], "on") == 0)
  767. doi8253set = 1;
  768. else if(strcmp(cb->f[1], "off") == 0){
  769. doi8253set = 0;
  770. (*arch->timerset)(0);
  771. }else
  772. cmderror(cb, "invalid i2853set ctl");
  773. break;
  774. }
  775. free(cb);
  776. poperror();
  777. return n;
  778. }
  779. void
  780. archinit(void)
  781. {
  782. PCArch **p;
  783. arch = 0;
  784. for(p = knownarch; *p; p++){
  785. if((*p)->ident && (*p)->ident() == 0){
  786. arch = *p;
  787. break;
  788. }
  789. }
  790. if(arch == 0)
  791. arch = &archgeneric;
  792. else{
  793. if(arch->id == 0)
  794. arch->id = archgeneric.id;
  795. if(arch->reset == 0)
  796. arch->reset = archgeneric.reset;
  797. if(arch->serialpower == 0)
  798. arch->serialpower = archgeneric.serialpower;
  799. if(arch->modempower == 0)
  800. arch->modempower = archgeneric.modempower;
  801. if(arch->intrinit == 0)
  802. arch->intrinit = archgeneric.intrinit;
  803. if(arch->intrenable == 0)
  804. arch->intrenable = archgeneric.intrenable;
  805. }
  806. /*
  807. * Decide whether to use copy-on-reference (386 and mp).
  808. * We get another chance to set it in mpinit() for a
  809. * multiprocessor.
  810. */
  811. if(X86FAMILY(m->cpuidax) == 3)
  812. conf.copymode = 1;
  813. if(X86FAMILY(m->cpuidax) >= 4)
  814. cmpswap = cmpswap486;
  815. if(X86FAMILY(m->cpuidax) >= 5)
  816. coherence = mb586;
  817. addarchfile("cputype", 0444, cputyperead, nil);
  818. addarchfile("archctl", 0664, archctlread, archctlwrite);
  819. }
  820. /*
  821. * call either the pcmcia or pccard device setup
  822. */
  823. int
  824. pcmspecial(char *idstr, ISAConf *isa)
  825. {
  826. return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
  827. }
  828. /*
  829. * call either the pcmcia or pccard device teardown
  830. */
  831. void
  832. pcmspecialclose(int a)
  833. {
  834. if (_pcmspecialclose != nil)
  835. _pcmspecialclose(a);
  836. }
  837. /*
  838. * return value and speed of timer set in arch->clockenable
  839. */
  840. uvlong
  841. fastticks(uvlong *hz)
  842. {
  843. return (*arch->fastclock)(hz);
  844. }
  845. ulong
  846. µs(void)
  847. {
  848. return fastticks2us((*arch->fastclock)(nil));
  849. }
  850. /*
  851. * set next timer interrupt
  852. */
  853. void
  854. timerset(uvlong x)
  855. {
  856. if(doi8253set)
  857. (*arch->timerset)(x);
  858. }