ether2114x.c 41 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830
  1. /*
  2. * Digital Semiconductor DECchip 2114x PCI Fast Ethernet LAN Controller.
  3. * To do:
  4. * thresholds;
  5. * ring sizing;
  6. * handle more error conditions;
  7. * tidy setup packet mess;
  8. * push initialisation back to attach;
  9. * full SROM decoding.
  10. */
  11. #include "u.h"
  12. #include "../port/lib.h"
  13. #include "mem.h"
  14. #include "dat.h"
  15. #include "fns.h"
  16. #include "io.h"
  17. #include "../port/error.h"
  18. #include "../port/netif.h"
  19. #include "etherif.h"
  20. #define DEBUG (0)
  21. #define debug if(DEBUG)print
  22. enum {
  23. Nrde = 64,
  24. Ntde = 64,
  25. };
  26. #define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
  27. enum { /* CRS0 - Bus Mode */
  28. Swr = 0x00000001, /* Software Reset */
  29. Bar = 0x00000002, /* Bus Arbitration */
  30. Dsl = 0x0000007C, /* Descriptor Skip Length (field) */
  31. Ble = 0x00000080, /* Big/Little Endian */
  32. Pbl = 0x00003F00, /* Programmable Burst Length (field) */
  33. Cal = 0x0000C000, /* Cache Alignment (field) */
  34. Cal8 = 0x00004000, /* 8 longword boundary alignment */
  35. Cal16 = 0x00008000, /* 16 longword boundary alignment */
  36. Cal32 = 0x0000C000, /* 32 longword boundary alignment */
  37. Tap = 0x000E0000, /* Transmit Automatic Polling (field) */
  38. Dbo = 0x00100000, /* Descriptor Byte Ordering Mode */
  39. Rml = 0x00200000, /* Read Multiple */
  40. };
  41. enum { /* CSR[57] - Status and Interrupt Enable */
  42. Ti = 0x00000001, /* Transmit Interrupt */
  43. Tps = 0x00000002, /* Transmit Process Stopped */
  44. Tu = 0x00000004, /* Transmit buffer Unavailable */
  45. Tjt = 0x00000008, /* Transmit Jabber Timeout */
  46. Unf = 0x00000020, /* transmit UNderFlow */
  47. Ri = 0x00000040, /* Receive Interrupt */
  48. Ru = 0x00000080, /* Receive buffer Unavailable */
  49. Rps = 0x00000100, /* Receive Process Stopped */
  50. Rwt = 0x00000200, /* Receive Watchdog Timeout */
  51. Eti = 0x00000400, /* Early Transmit Interrupt */
  52. Gte = 0x00000800, /* General purpose Timer Expired */
  53. Fbe = 0x00002000, /* Fatal Bit Error */
  54. Ais = 0x00008000, /* Abnormal Interrupt Summary */
  55. Nis = 0x00010000, /* Normal Interrupt Summary */
  56. Rs = 0x000E0000, /* Receive process State (field) */
  57. Ts = 0x00700000, /* Transmit process State (field) */
  58. Eb = 0x03800000, /* Error bits */
  59. };
  60. enum { /* CSR6 - Operating Mode */
  61. Hp = 0x00000001, /* Hash/Perfect receive filtering mode */
  62. Sr = 0x00000002, /* Start/stop Receive */
  63. Ho = 0x00000004, /* Hash-Only filtering mode */
  64. Pb = 0x00000008, /* Pass Bad frames */
  65. If = 0x00000010, /* Inverse Filtering */
  66. Sb = 0x00000020, /* Start/stop Backoff counter */
  67. Pr = 0x00000040, /* Promiscuous Mode */
  68. Pm = 0x00000080, /* Pass all Multicast */
  69. Fd = 0x00000200, /* Full Duplex mode */
  70. Om = 0x00000C00, /* Operating Mode (field) */
  71. Fc = 0x00001000, /* Force Collision */
  72. St = 0x00002000, /* Start/stop Transmission Command */
  73. Tr = 0x0000C000, /* ThReshold control bits (field) */
  74. Tr128 = 0x00000000,
  75. Tr256 = 0x00004000,
  76. Tr512 = 0x00008000,
  77. Tr1024 = 0x0000C000,
  78. Ca = 0x00020000, /* CApture effect enable */
  79. Ps = 0x00040000, /* Port Select */
  80. Hbd = 0x00080000, /* HeartBeat Disable */
  81. Imm = 0x00100000, /* IMMediate mode */
  82. Sf = 0x00200000, /* Store and Forward */
  83. Ttm = 0x00400000, /* Transmit Threshold Mode */
  84. Pcs = 0x00800000, /* PCS function */
  85. Scr = 0x01000000, /* SCRambler mode */
  86. Mbo = 0x02000000, /* Must Be One */
  87. Ra = 0x40000000, /* Receive All */
  88. Sc = 0x80000000, /* Special Capture effect enable */
  89. TrMODE = Tr512, /* default transmission threshold */
  90. };
  91. enum { /* CSR9 - ROM and MII Management */
  92. Scs = 0x00000001, /* serial ROM chip select */
  93. Sclk = 0x00000002, /* serial ROM clock */
  94. Sdi = 0x00000004, /* serial ROM data in */
  95. Sdo = 0x00000008, /* serial ROM data out */
  96. Ss = 0x00000800, /* serial ROM select */
  97. Wr = 0x00002000, /* write */
  98. Rd = 0x00004000, /* read */
  99. Mdc = 0x00010000, /* MII management clock */
  100. Mdo = 0x00020000, /* MII management write data */
  101. Mii = 0x00040000, /* MII management operation mode (W) */
  102. Mdi = 0x00080000, /* MII management data in */
  103. };
  104. enum { /* CSR12 - General-Purpose Port */
  105. Gpc = 0x00000100, /* General Purpose Control */
  106. };
  107. typedef struct Des {
  108. int status;
  109. int control;
  110. ulong addr;
  111. Block* bp;
  112. } Des;
  113. enum { /* status */
  114. Of = 0x00000001, /* Rx: OverFlow */
  115. Ce = 0x00000002, /* Rx: CRC Error */
  116. Db = 0x00000004, /* Rx: Dribbling Bit */
  117. Re = 0x00000008, /* Rx: Report on MII Error */
  118. Rw = 0x00000010, /* Rx: Receive Watchdog */
  119. Ft = 0x00000020, /* Rx: Frame Type */
  120. Cs = 0x00000040, /* Rx: Collision Seen */
  121. Tl = 0x00000080, /* Rx: Frame too Long */
  122. Ls = 0x00000100, /* Rx: Last deScriptor */
  123. Fs = 0x00000200, /* Rx: First deScriptor */
  124. Mf = 0x00000400, /* Rx: Multicast Frame */
  125. Rf = 0x00000800, /* Rx: Runt Frame */
  126. Dt = 0x00003000, /* Rx: Data Type (field) */
  127. De = 0x00004000, /* Rx: Descriptor Error */
  128. Fl = 0x3FFF0000, /* Rx: Frame Length (field) */
  129. Ff = 0x40000000, /* Rx: Filtering Fail */
  130. Def = 0x00000001, /* Tx: DEFerred */
  131. Uf = 0x00000002, /* Tx: UnderFlow error */
  132. Lf = 0x00000004, /* Tx: Link Fail report */
  133. Cc = 0x00000078, /* Tx: Collision Count (field) */
  134. Hf = 0x00000080, /* Tx: Heartbeat Fail */
  135. Ec = 0x00000100, /* Tx: Excessive Collisions */
  136. Lc = 0x00000200, /* Tx: Late Collision */
  137. Nc = 0x00000400, /* Tx: No Carrier */
  138. Lo = 0x00000800, /* Tx: LOss of carrier */
  139. To = 0x00004000, /* Tx: Transmission jabber timeOut */
  140. Es = 0x00008000, /* [RT]x: Error Summary */
  141. Own = 0x80000000, /* [RT]x: OWN bit */
  142. };
  143. enum { /* control */
  144. Bs1 = 0x000007FF, /* [RT]x: Buffer 1 Size */
  145. Bs2 = 0x003FF800, /* [RT]x: Buffer 2 Size */
  146. Ch = 0x01000000, /* [RT]x: second address CHained */
  147. Er = 0x02000000, /* [RT]x: End of Ring */
  148. Ft0 = 0x00400000, /* Tx: Filtering Type 0 */
  149. Dpd = 0x00800000, /* Tx: Disabled PaDding */
  150. Ac = 0x04000000, /* Tx: Add CRC disable */
  151. Set = 0x08000000, /* Tx: SETup packet */
  152. Ft1 = 0x10000000, /* Tx: Filtering Type 1 */
  153. Fseg = 0x20000000, /* Tx: First SEGment */
  154. Lseg = 0x40000000, /* Tx: Last SEGment */
  155. Ic = 0x80000000, /* Tx: Interrupt on Completion */
  156. };
  157. enum { /* PHY registers */
  158. Bmcr = 0, /* Basic Mode Control */
  159. Bmsr = 1, /* Basic Mode Status */
  160. Phyidr1 = 2, /* PHY Identifier #1 */
  161. Phyidr2 = 3, /* PHY Identifier #2 */
  162. Anar = 4, /* Auto-Negotiation Advertisment */
  163. Anlpar = 5, /* Auto-Negotiation Link Partner Ability */
  164. Aner = 6, /* Auto-Negotiation Expansion */
  165. };
  166. enum { /* Variants */
  167. Tulip0 = (0x0009<<16)|0x1011,
  168. Tulip1 = (0x0014<<16)|0x1011,
  169. Tulip3 = (0x0019<<16)|0x1011,
  170. Pnic = (0x0002<<16)|0x11AD,
  171. Pnic2 = (0xC115<<16)|0x11AD,
  172. CentaurP = (0x0985<<16)|0x1317,
  173. CentaurPcb = (0x1985<<16)|0x1317,
  174. };
  175. typedef struct Ctlr Ctlr;
  176. typedef struct Ctlr {
  177. int port;
  178. Pcidev* pcidev;
  179. Ctlr* next;
  180. int active;
  181. int id; /* (pcidev->did<<16)|pcidev->vid */
  182. uchar* srom;
  183. int sromsz; /* address size in bits */
  184. uchar* sromea; /* MAC address */
  185. uchar* leaf;
  186. int sct; /* selected connection type */
  187. int k; /* info block count */
  188. uchar* infoblock[16];
  189. int sctk; /* sct block index */
  190. int curk; /* current block index */
  191. uchar* type5block;
  192. int phy[32]; /* logical to physical map */
  193. int phyreset; /* reset bitmap */
  194. int curphyad;
  195. int fdx;
  196. int ttm;
  197. uchar fd; /* option */
  198. int medium; /* option */
  199. int csr6; /* CSR6 - operating mode */
  200. int mask; /* CSR[57] - interrupt mask */
  201. int mbps;
  202. Lock lock;
  203. Des* rdr; /* receive descriptor ring */
  204. int nrdr; /* size of rdr */
  205. int rdrx; /* index into rdr */
  206. Lock tlock;
  207. Des* tdr; /* transmit descriptor ring */
  208. int ntdr; /* size of tdr */
  209. int tdrh; /* host index into tdr */
  210. int tdri; /* interface index into tdr */
  211. int ntq; /* descriptors active */
  212. int ntqmax;
  213. Block* setupbp;
  214. ulong of; /* receive statistics */
  215. ulong ce;
  216. ulong cs;
  217. ulong tl;
  218. ulong rf;
  219. ulong de;
  220. ulong ru;
  221. ulong rps;
  222. ulong rwt;
  223. ulong uf; /* transmit statistics */
  224. ulong ec;
  225. ulong lc;
  226. ulong nc;
  227. ulong lo;
  228. ulong to;
  229. ulong tps;
  230. ulong tu;
  231. ulong tjt;
  232. ulong unf;
  233. } Ctlr;
  234. static Ctlr* ctlrhead;
  235. static Ctlr* ctlrtail;
  236. #define csr32r(c, r) (inl((c)->port+((r)*8)))
  237. #define csr32w(c, r, l) (outl((c)->port+((r)*8), (ulong)(l)))
  238. static void
  239. promiscuous(void* arg, int on)
  240. {
  241. Ctlr *ctlr;
  242. ctlr = ((Ether*)arg)->ctlr;
  243. ilock(&ctlr->lock);
  244. if(on)
  245. ctlr->csr6 |= Pr;
  246. else
  247. ctlr->csr6 &= ~Pr;
  248. csr32w(ctlr, 6, ctlr->csr6);
  249. iunlock(&ctlr->lock);
  250. }
  251. /* multicast already on, don't need to do anything */
  252. static void
  253. multicast(void*, uchar*, int)
  254. {
  255. }
  256. static void
  257. attach(Ether* ether)
  258. {
  259. Ctlr *ctlr;
  260. ctlr = ether->ctlr;
  261. ilock(&ctlr->lock);
  262. if(!(ctlr->csr6 & Sr)){
  263. ctlr->csr6 |= Sr;
  264. csr32w(ctlr, 6, ctlr->csr6);
  265. }
  266. iunlock(&ctlr->lock);
  267. }
  268. static long
  269. ifstat(Ether* ether, void* a, long n, ulong offset)
  270. {
  271. Ctlr *ctlr;
  272. char *buf, *p;
  273. int i, l, len;
  274. ctlr = ether->ctlr;
  275. ether->crcs = ctlr->ce;
  276. ether->frames = ctlr->rf+ctlr->cs;
  277. ether->buffs = ctlr->de+ctlr->tl;
  278. ether->overflows = ctlr->of;
  279. if(n == 0)
  280. return 0;
  281. p = malloc(READSTR);
  282. l = snprint(p, READSTR, "Overflow: %lud\n", ctlr->of);
  283. l += snprint(p+l, READSTR-l, "Ru: %lud\n", ctlr->ru);
  284. l += snprint(p+l, READSTR-l, "Rps: %lud\n", ctlr->rps);
  285. l += snprint(p+l, READSTR-l, "Rwt: %lud\n", ctlr->rwt);
  286. l += snprint(p+l, READSTR-l, "Tps: %lud\n", ctlr->tps);
  287. l += snprint(p+l, READSTR-l, "Tu: %lud\n", ctlr->tu);
  288. l += snprint(p+l, READSTR-l, "Tjt: %lud\n", ctlr->tjt);
  289. l += snprint(p+l, READSTR-l, "Unf: %lud\n", ctlr->unf);
  290. l += snprint(p+l, READSTR-l, "CRC Error: %lud\n", ctlr->ce);
  291. l += snprint(p+l, READSTR-l, "Collision Seen: %lud\n", ctlr->cs);
  292. l += snprint(p+l, READSTR-l, "Frame Too Long: %lud\n", ctlr->tl);
  293. l += snprint(p+l, READSTR-l, "Runt Frame: %lud\n", ctlr->rf);
  294. l += snprint(p+l, READSTR-l, "Descriptor Error: %lud\n", ctlr->de);
  295. l += snprint(p+l, READSTR-l, "Underflow Error: %lud\n", ctlr->uf);
  296. l += snprint(p+l, READSTR-l, "Excessive Collisions: %lud\n", ctlr->ec);
  297. l += snprint(p+l, READSTR-l, "Late Collision: %lud\n", ctlr->lc);
  298. l += snprint(p+l, READSTR-l, "No Carrier: %lud\n", ctlr->nc);
  299. l += snprint(p+l, READSTR-l, "Loss of Carrier: %lud\n", ctlr->lo);
  300. l += snprint(p+l, READSTR-l, "Transmit Jabber Timeout: %lud\n",
  301. ctlr->to);
  302. l += snprint(p+l, READSTR-l, "csr6: %luX %uX\n", csr32r(ctlr, 6),
  303. ctlr->csr6);
  304. snprint(p+l, READSTR-l, "ntqmax: %d\n", ctlr->ntqmax);
  305. ctlr->ntqmax = 0;
  306. buf = a;
  307. len = readstr(offset, buf, n, p);
  308. if(offset > l)
  309. offset -= l;
  310. else
  311. offset = 0;
  312. buf += len;
  313. n -= len;
  314. l = snprint(p, READSTR, "srom:");
  315. for(i = 0; i < (1<<(ctlr->sromsz)*sizeof(ushort)); i++){
  316. if(i && ((i & 0x0F) == 0))
  317. l += snprint(p+l, READSTR-l, "\n ");
  318. l += snprint(p+l, READSTR-l, " %2.2uX", ctlr->srom[i]);
  319. }
  320. snprint(p+l, READSTR-l, "\n");
  321. len += readstr(offset, buf, n, p);
  322. free(p);
  323. return len;
  324. }
  325. static void
  326. txstart(Ether* ether)
  327. {
  328. Ctlr *ctlr;
  329. Block *bp;
  330. Des *des;
  331. int control;
  332. ctlr = ether->ctlr;
  333. while(ctlr->ntq < (ctlr->ntdr-1)){
  334. if(ctlr->setupbp){
  335. bp = ctlr->setupbp;
  336. ctlr->setupbp = 0;
  337. control = Ic|Set|BLEN(bp);
  338. }
  339. else{
  340. bp = qget(ether->oq);
  341. if(bp == nil)
  342. break;
  343. control = Ic|Lseg|Fseg|BLEN(bp);
  344. }
  345. ctlr->tdr[PREV(ctlr->tdrh, ctlr->ntdr)].control &= ~Ic;
  346. des = &ctlr->tdr[ctlr->tdrh];
  347. des->bp = bp;
  348. des->addr = PCIWADDR(bp->rp);
  349. des->control |= control;
  350. ctlr->ntq++;
  351. coherence();
  352. des->status = Own;
  353. csr32w(ctlr, 1, 0);
  354. ctlr->tdrh = NEXT(ctlr->tdrh, ctlr->ntdr);
  355. }
  356. if(ctlr->ntq > ctlr->ntqmax)
  357. ctlr->ntqmax = ctlr->ntq;
  358. }
  359. static void
  360. transmit(Ether* ether)
  361. {
  362. Ctlr *ctlr;
  363. ctlr = ether->ctlr;
  364. ilock(&ctlr->tlock);
  365. txstart(ether);
  366. iunlock(&ctlr->tlock);
  367. }
  368. static void
  369. interrupt(Ureg*, void* arg)
  370. {
  371. Ctlr *ctlr;
  372. Ether *ether;
  373. int len, status;
  374. Des *des;
  375. Block *bp;
  376. ether = arg;
  377. ctlr = ether->ctlr;
  378. while((status = csr32r(ctlr, 5)) & (Nis|Ais)){
  379. /*
  380. * Acknowledge the interrupts and mask-out
  381. * the ones that are implicitly handled.
  382. */
  383. csr32w(ctlr, 5, status);
  384. status &= (ctlr->mask & ~(Nis|Ti));
  385. if(status & Ais){
  386. if(status & Tps)
  387. ctlr->tps++;
  388. if(status & Tu)
  389. ctlr->tu++;
  390. if(status & Tjt)
  391. ctlr->tjt++;
  392. if(status & Ru)
  393. ctlr->ru++;
  394. if(status & Rps)
  395. ctlr->rps++;
  396. if(status & Rwt)
  397. ctlr->rwt++;
  398. status &= ~(Ais|Rwt|Rps|Ru|Tjt|Tu|Tps);
  399. }
  400. /*
  401. * Received packets.
  402. */
  403. if(status & Ri){
  404. des = &ctlr->rdr[ctlr->rdrx];
  405. while(!(des->status & Own)){
  406. if(des->status & Es){
  407. if(des->status & Of)
  408. ctlr->of++;
  409. if(des->status & Ce)
  410. ctlr->ce++;
  411. if(des->status & Cs)
  412. ctlr->cs++;
  413. if(des->status & Tl)
  414. ctlr->tl++;
  415. if(des->status & Rf)
  416. ctlr->rf++;
  417. if(des->status & De)
  418. ctlr->de++;
  419. }
  420. else if(bp = iallocb(Rbsz)){
  421. len = ((des->status & Fl)>>16)-4;
  422. des->bp->wp = des->bp->rp+len;
  423. etheriq(ether, des->bp, 1);
  424. des->bp = bp;
  425. des->addr = PCIWADDR(bp->rp);
  426. }
  427. des->control &= Er;
  428. des->control |= Rbsz;
  429. coherence();
  430. des->status = Own;
  431. ctlr->rdrx = NEXT(ctlr->rdrx, ctlr->nrdr);
  432. des = &ctlr->rdr[ctlr->rdrx];
  433. }
  434. status &= ~Ri;
  435. }
  436. /*
  437. * Check the transmit side:
  438. * check for Transmit Underflow and Adjust
  439. * the threshold upwards;
  440. * free any transmitted buffers and try to
  441. * top-up the ring.
  442. */
  443. if(status & Unf){
  444. ctlr->unf++;
  445. ilock(&ctlr->lock);
  446. csr32w(ctlr, 6, ctlr->csr6 & ~St);
  447. switch(ctlr->csr6 & Tr){
  448. case Tr128:
  449. len = Tr256;
  450. break;
  451. case Tr256:
  452. len = Tr512;
  453. break;
  454. case Tr512:
  455. len = Tr1024;
  456. break;
  457. default:
  458. case Tr1024:
  459. len = Sf;
  460. break;
  461. }
  462. ctlr->csr6 = (ctlr->csr6 & ~Tr)|len;
  463. csr32w(ctlr, 6, ctlr->csr6);
  464. iunlock(&ctlr->lock);
  465. csr32w(ctlr, 5, Tps);
  466. status &= ~(Unf|Tps);
  467. }
  468. ilock(&ctlr->tlock);
  469. while(ctlr->ntq){
  470. des = &ctlr->tdr[ctlr->tdri];
  471. if(des->status & Own)
  472. break;
  473. if(des->status & Es){
  474. if(des->status & Uf)
  475. ctlr->uf++;
  476. if(des->status & Ec)
  477. ctlr->ec++;
  478. if(des->status & Lc)
  479. ctlr->lc++;
  480. if(des->status & Nc)
  481. ctlr->nc++;
  482. if(des->status & Lo)
  483. ctlr->lo++;
  484. if(des->status & To)
  485. ctlr->to++;
  486. ether->oerrs++;
  487. }
  488. freeb(des->bp);
  489. des->control &= Er;
  490. ctlr->ntq--;
  491. ctlr->tdri = NEXT(ctlr->tdri, ctlr->ntdr);
  492. }
  493. txstart(ether);
  494. iunlock(&ctlr->tlock);
  495. /*
  496. * Anything left not catered for?
  497. */
  498. if(status)
  499. panic("#l%d: status %8.8uX\n", ether->ctlrno, status);
  500. }
  501. }
  502. static void
  503. ctlrinit(Ether* ether)
  504. {
  505. Ctlr *ctlr;
  506. Des *des;
  507. Block *bp;
  508. int i;
  509. uchar bi[Eaddrlen*2];
  510. ctlr = ether->ctlr;
  511. /*
  512. * Allocate and initialise the receive ring;
  513. * allocate and initialise the transmit ring;
  514. * unmask interrupts and start the transmit side;
  515. * create and post a setup packet to initialise
  516. * the physical ethernet address.
  517. */
  518. ctlr->rdr = xspanalloc(ctlr->nrdr*sizeof(Des), 8*sizeof(ulong), 0);
  519. for(des = ctlr->rdr; des < &ctlr->rdr[ctlr->nrdr]; des++){
  520. des->bp = iallocb(Rbsz);
  521. if(des->bp == nil)
  522. panic("can't allocate ethernet receive ring\n");
  523. des->status = Own;
  524. des->control = Rbsz;
  525. des->addr = PCIWADDR(des->bp->rp);
  526. }
  527. ctlr->rdr[ctlr->nrdr-1].control |= Er;
  528. ctlr->rdrx = 0;
  529. csr32w(ctlr, 3, PCIWADDR(ctlr->rdr));
  530. ctlr->tdr = xspanalloc(ctlr->ntdr*sizeof(Des), 8*sizeof(ulong), 0);
  531. ctlr->tdr[ctlr->ntdr-1].control |= Er;
  532. ctlr->tdrh = 0;
  533. ctlr->tdri = 0;
  534. csr32w(ctlr, 4, PCIWADDR(ctlr->tdr));
  535. /*
  536. * Clear any bits in the Status Register (CSR5) as
  537. * the PNIC has a different reset value from a true 2114x.
  538. */
  539. ctlr->mask = Nis|Ais|Fbe|Rwt|Rps|Ru|Ri|Unf|Tjt|Tps|Ti;
  540. csr32w(ctlr, 5, ctlr->mask);
  541. csr32w(ctlr, 7, ctlr->mask);
  542. ctlr->csr6 |= St|Pm;
  543. csr32w(ctlr, 6, ctlr->csr6);
  544. for(i = 0; i < Eaddrlen/2; i++){
  545. bi[i*4] = ether->ea[i*2];
  546. bi[i*4+1] = ether->ea[i*2+1];
  547. bi[i*4+2] = ether->ea[i*2+1];
  548. bi[i*4+3] = ether->ea[i*2];
  549. }
  550. bp = iallocb(Eaddrlen*2*16);
  551. if(bp == nil)
  552. panic("can't allocate ethernet setup buffer\n");
  553. memset(bp->rp, 0xFF, sizeof(bi));
  554. for(i = sizeof(bi); i < sizeof(bi)*16; i += sizeof(bi))
  555. memmove(bp->rp+i, bi, sizeof(bi));
  556. bp->wp += sizeof(bi)*16;
  557. ctlr->setupbp = bp;
  558. ether->oq = qopen(256*1024, Qmsg, 0, 0);
  559. transmit(ether);
  560. }
  561. static void
  562. csr9w(Ctlr* ctlr, int data)
  563. {
  564. csr32w(ctlr, 9, data);
  565. microdelay(1);
  566. }
  567. static int
  568. miimdi(Ctlr* ctlr, int n)
  569. {
  570. int data, i;
  571. /*
  572. * Read n bits from the MII Management Register.
  573. */
  574. data = 0;
  575. for(i = n-1; i >= 0; i--){
  576. if(csr32r(ctlr, 9) & Mdi)
  577. data |= (1<<i);
  578. csr9w(ctlr, Mii|Mdc);
  579. csr9w(ctlr, Mii);
  580. }
  581. csr9w(ctlr, 0);
  582. return data;
  583. }
  584. static void
  585. miimdo(Ctlr* ctlr, int bits, int n)
  586. {
  587. int i, mdo;
  588. /*
  589. * Write n bits to the MII Management Register.
  590. */
  591. for(i = n-1; i >= 0; i--){
  592. if(bits & (1<<i))
  593. mdo = Mdo;
  594. else
  595. mdo = 0;
  596. csr9w(ctlr, mdo);
  597. csr9w(ctlr, mdo|Mdc);
  598. csr9w(ctlr, mdo);
  599. }
  600. }
  601. static int
  602. miir(Ctlr* ctlr, int phyad, int regad)
  603. {
  604. int data, i;
  605. if(ctlr->id == Pnic){
  606. i = 1000;
  607. csr32w(ctlr, 20, 0x60020000|(phyad<<23)|(regad<<18));
  608. do{
  609. microdelay(1);
  610. data = csr32r(ctlr, 20);
  611. }while((data & 0x80000000) && --i);
  612. if(i == 0)
  613. return -1;
  614. return data & 0xFFFF;
  615. }
  616. /*
  617. * Preamble;
  618. * ST+OP+PHYAD+REGAD;
  619. * TA + 16 data bits.
  620. */
  621. miimdo(ctlr, 0xFFFFFFFF, 32);
  622. miimdo(ctlr, 0x1800|(phyad<<5)|regad, 14);
  623. data = miimdi(ctlr, 18);
  624. if(data & 0x10000)
  625. return -1;
  626. return data & 0xFFFF;
  627. }
  628. static void
  629. miiw(Ctlr* ctlr, int phyad, int regad, int data)
  630. {
  631. /*
  632. * Preamble;
  633. * ST+OP+PHYAD+REGAD+TA + 16 data bits;
  634. * Z.
  635. */
  636. miimdo(ctlr, 0xFFFFFFFF, 32);
  637. data &= 0xFFFF;
  638. data |= (0x05<<(5+5+2+16))|(phyad<<(5+2+16))|(regad<<(2+16))|(0x02<<16);
  639. miimdo(ctlr, data, 32);
  640. csr9w(ctlr, Mdc);
  641. csr9w(ctlr, 0);
  642. }
  643. static int
  644. sromr(Ctlr* ctlr, int r)
  645. {
  646. int i, op, data, size;
  647. if(ctlr->id == Pnic){
  648. i = 1000;
  649. csr32w(ctlr, 19, 0x600|r);
  650. do{
  651. microdelay(1);
  652. data = csr32r(ctlr, 19);
  653. }while((data & 0x80000000) && --i);
  654. if(ctlr->sromsz == 0)
  655. ctlr->sromsz = 6;
  656. return csr32r(ctlr, 9) & 0xFFFF;
  657. }
  658. /*
  659. * This sequence for reading a 16-bit register 'r'
  660. * in the EEPROM is taken (pretty much) straight from Section
  661. * 7.4 of the 21140 Hardware Reference Manual.
  662. */
  663. reread:
  664. csr9w(ctlr, Rd|Ss);
  665. csr9w(ctlr, Rd|Ss|Scs);
  666. csr9w(ctlr, Rd|Ss|Sclk|Scs);
  667. csr9w(ctlr, Rd|Ss);
  668. op = 0x06;
  669. for(i = 3-1; i >= 0; i--){
  670. data = Rd|Ss|(((op>>i) & 0x01)<<2)|Scs;
  671. csr9w(ctlr, data);
  672. csr9w(ctlr, data|Sclk);
  673. csr9w(ctlr, data);
  674. }
  675. /*
  676. * First time through must work out the EEPROM size.
  677. * This doesn't seem to work on the 21041 as implemented
  678. * in Virtual PC for the Mac, so wire any 21041 to 6,
  679. * it's the only 21041 this code will ever likely see.
  680. */
  681. if((size = ctlr->sromsz) == 0){
  682. if(ctlr->id == Tulip1)
  683. ctlr->sromsz = size = 6;
  684. else
  685. size = 8;
  686. }
  687. for(size = size-1; size >= 0; size--){
  688. data = Rd|Ss|(((r>>size) & 0x01)<<2)|Scs;
  689. csr9w(ctlr, data);
  690. csr9w(ctlr, data|Sclk);
  691. csr9w(ctlr, data);
  692. microdelay(1);
  693. if(ctlr->sromsz == 0 && !(csr32r(ctlr, 9) & Sdo))
  694. break;
  695. }
  696. data = 0;
  697. for(i = 16-1; i >= 0; i--){
  698. csr9w(ctlr, Rd|Ss|Sclk|Scs);
  699. if(csr32r(ctlr, 9) & Sdo)
  700. data |= (1<<i);
  701. csr9w(ctlr, Rd|Ss|Scs);
  702. }
  703. csr9w(ctlr, 0);
  704. if(ctlr->sromsz == 0){
  705. ctlr->sromsz = 8-size;
  706. goto reread;
  707. }
  708. return data & 0xFFFF;
  709. }
  710. static void
  711. shutdown(Ether* ether)
  712. {
  713. Ctlr *ctlr = ether->ctlr;
  714. print("ether2114x shutting down\n");
  715. csr32w(ctlr, 0, Swr);
  716. }
  717. static void
  718. softreset(Ctlr* ctlr)
  719. {
  720. /*
  721. * Soft-reset the controller and initialise bus mode.
  722. * Delay should be >= 50 PCI cycles (2×S @ 25MHz).
  723. */
  724. csr32w(ctlr, 0, Swr);
  725. microdelay(10);
  726. csr32w(ctlr, 0, Rml|Cal16);
  727. delay(1);
  728. }
  729. static int
  730. type5block(Ctlr* ctlr, uchar* block)
  731. {
  732. int csr15, i, len;
  733. /*
  734. * Reset or GPR sequence. Reset should be once only,
  735. * before the GPR sequence.
  736. * Note 'block' is not a pointer to the block head but
  737. * a pointer to the data in the block starting at the
  738. * reset length value so type5block can be used for the
  739. * sequences contained in type 1 and type 3 blocks.
  740. * The SROM docs state the 21140 type 5 block is the
  741. * same as that for the 21143, but the two controllers
  742. * use different registers and sequence-element lengths
  743. * so the 21140 code here is a guess for a real type 5
  744. * sequence.
  745. */
  746. len = *block++;
  747. if(ctlr->id != Tulip3){
  748. for(i = 0; i < len; i++){
  749. csr32w(ctlr, 12, *block);
  750. block++;
  751. }
  752. return len;
  753. }
  754. for(i = 0; i < len; i++){
  755. csr15 = *block++<<16;
  756. csr15 |= *block++<<24;
  757. csr32w(ctlr, 15, csr15);
  758. debug("%8.8uX ", csr15);
  759. }
  760. return 2*len;
  761. }
  762. static int
  763. typephylink(Ctlr* ctlr, uchar*)
  764. {
  765. int an, bmcr, bmsr, csr6, x;
  766. /*
  767. * Fail if
  768. * auto-negotiataion enabled but not complete;
  769. * no valid link established.
  770. */
  771. bmcr = miir(ctlr, ctlr->curphyad, Bmcr);
  772. miir(ctlr, ctlr->curphyad, Bmsr);
  773. bmsr = miir(ctlr, ctlr->curphyad, Bmsr);
  774. debug("bmcr 0x%2.2uX bmsr 0x%2.2uX\n", bmcr, bmsr);
  775. if(((bmcr & 0x1000) && !(bmsr & 0x0020)) || !(bmsr & 0x0004))
  776. return 0;
  777. if(bmcr & 0x1000){
  778. an = miir(ctlr, ctlr->curphyad, Anar);
  779. an &= miir(ctlr, ctlr->curphyad, Anlpar) & 0x3E0;
  780. debug("an 0x%2.uX 0x%2.2uX 0x%2.2uX\n",
  781. miir(ctlr, ctlr->curphyad, Anar),
  782. miir(ctlr, ctlr->curphyad, Anlpar),
  783. an);
  784. if(an & 0x0100)
  785. x = 0x4000;
  786. else if(an & 0x0080)
  787. x = 0x2000;
  788. else if(an & 0x0040)
  789. x = 0x1000;
  790. else if(an & 0x0020)
  791. x = 0x0800;
  792. else
  793. x = 0;
  794. }
  795. else if((bmcr & 0x2100) == 0x2100)
  796. x = 0x4000;
  797. else if(bmcr & 0x2000){
  798. /*
  799. * If FD capable, force it if necessary.
  800. */
  801. if((bmsr & 0x4000) && ctlr->fd){
  802. miiw(ctlr, ctlr->curphyad, Bmcr, 0x2100);
  803. x = 0x4000;
  804. }
  805. else
  806. x = 0x2000;
  807. }
  808. else if(bmcr & 0x0100)
  809. x = 0x1000;
  810. else
  811. x = 0x0800;
  812. csr6 = Sc|Mbo|Hbd|Ps|Ca|TrMODE|Sb;
  813. if(ctlr->fdx & x)
  814. csr6 |= Fd;
  815. if(ctlr->ttm & x)
  816. csr6 |= Ttm;
  817. debug("csr6 0x%8.8uX 0x%8.8uX 0x%8.8luX\n",
  818. csr6, ctlr->csr6, csr32r(ctlr, 6));
  819. if(csr6 != ctlr->csr6){
  820. ctlr->csr6 = csr6;
  821. csr32w(ctlr, 6, csr6);
  822. }
  823. return 1;
  824. }
  825. static int
  826. typephymode(Ctlr* ctlr, uchar* block, int wait)
  827. {
  828. uchar *p;
  829. int len, mc, nway, phyx, timeo;
  830. if(DEBUG){
  831. int i;
  832. len = (block[0] & ~0x80)+1;
  833. for(i = 0; i < len; i++)
  834. debug("%2.2uX ", block[i]);
  835. debug("\n");
  836. }
  837. if(block[1] == 1)
  838. len = 1;
  839. else if(block[1] == 3)
  840. len = 2;
  841. else
  842. return -1;
  843. /*
  844. * Snarf the media capabilities, nway advertisment,
  845. * FDX and TTM bitmaps.
  846. */
  847. p = &block[5+len*block[3]+len*block[4+len*block[3]]];
  848. mc = *p++;
  849. mc |= *p++<<8;
  850. nway = *p++;
  851. nway |= *p++<<8;
  852. ctlr->fdx = *p++;
  853. ctlr->fdx |= *p++<<8;
  854. ctlr->ttm = *p++;
  855. ctlr->ttm |= *p<<8;
  856. debug("mc %4.4uX nway %4.4uX fdx %4.4uX ttm %4.4uX\n",
  857. mc, nway, ctlr->fdx, ctlr->ttm);
  858. USED(mc);
  859. phyx = block[2];
  860. ctlr->curphyad = ctlr->phy[phyx];
  861. ctlr->csr6 = 0;//Sc|Mbo|Hbd|Ps|Ca|TrMODE|Sb;
  862. //csr32w(ctlr, 6, ctlr->csr6);
  863. if(typephylink(ctlr, block))
  864. return 0;
  865. if(!(ctlr->phyreset & (1<<phyx))){
  866. debug("reset seq: len %d: ", block[3]);
  867. if(ctlr->type5block)
  868. type5block(ctlr, &ctlr->type5block[2]);
  869. else
  870. type5block(ctlr, &block[4+len*block[3]]);
  871. debug("\n");
  872. ctlr->phyreset |= (1<<phyx);
  873. }
  874. /*
  875. * GPR sequence.
  876. */
  877. debug("gpr seq: len %d: ", block[3]);
  878. type5block(ctlr, &block[3]);
  879. debug("\n");
  880. ctlr->csr6 = 0;//Sc|Mbo|Hbd|Ps|Ca|TrMODE|Sb;
  881. //csr32w(ctlr, 6, ctlr->csr6);
  882. if(typephylink(ctlr, block))
  883. return 0;
  884. /*
  885. * Turn off auto-negotiation, set the auto-negotiation
  886. * advertisment register then start the auto-negotiation
  887. * process again.
  888. */
  889. miiw(ctlr, ctlr->curphyad, Bmcr, 0);
  890. miiw(ctlr, ctlr->curphyad, Anar, nway|1);
  891. miiw(ctlr, ctlr->curphyad, Bmcr, 0x1000);
  892. if(!wait)
  893. return 0;
  894. for(timeo = 0; timeo < 45; timeo++){
  895. if(typephylink(ctlr, block))
  896. return 0;
  897. delay(100);
  898. }
  899. return -1;
  900. }
  901. static int
  902. typesymmode(Ctlr *ctlr, uchar *block, int wait)
  903. {
  904. uint gpmode, gpdata, command;
  905. USED(wait);
  906. gpmode = block[3] | ((uint) block[4] << 8);
  907. gpdata = block[5] | ((uint) block[6] << 8);
  908. command = (block[7] | ((uint) block[8] << 8)) & 0x71;
  909. if (command & 0x8000) {
  910. print("ether2114x.c: FIXME: handle type 4 mode blocks where cmd.active_invalid != 0\n");
  911. return -1;
  912. }
  913. csr32w(ctlr, 15, gpmode);
  914. csr32w(ctlr, 15, gpdata);
  915. ctlr->csr6 = (command & 0x71) << 18;
  916. csr32w(ctlr, 6, ctlr->csr6);
  917. return 0;
  918. }
  919. static int
  920. type2mode(Ctlr* ctlr, uchar* block, int)
  921. {
  922. uchar *p;
  923. int csr6, csr13, csr14, csr15, gpc, gpd;
  924. csr6 = Sc|Mbo|Ca|TrMODE|Sb;
  925. debug("type2mode: medium 0x%2.2uX\n", block[2]);
  926. /*
  927. * Don't attempt full-duplex
  928. * unless explicitly requested.
  929. */
  930. if((block[2] & 0x3F) == 0x04){ /* 10BASE-TFD */
  931. if(!ctlr->fd)
  932. return -1;
  933. csr6 |= Fd;
  934. }
  935. /*
  936. * Operating mode programming values from the datasheet
  937. * unless media specific data is explicitly given.
  938. */
  939. p = &block[3];
  940. if(block[2] & 0x40){
  941. csr13 = (block[4]<<8)|block[3];
  942. csr14 = (block[6]<<8)|block[5];
  943. csr15 = (block[8]<<8)|block[7];
  944. p += 6;
  945. }
  946. else switch(block[2] & 0x3F){
  947. default:
  948. return -1;
  949. case 0x00: /* 10BASE-T */
  950. csr13 = 0x00000001;
  951. csr14 = 0x00007F3F;
  952. csr15 = 0x00000008;
  953. break;
  954. case 0x01: /* 10BASE-2 */
  955. csr13 = 0x00000009;
  956. csr14 = 0x00000705;
  957. csr15 = 0x00000006;
  958. break;
  959. case 0x02: /* 10BASE-5 (AUI) */
  960. csr13 = 0x00000009;
  961. csr14 = 0x00000705;
  962. csr15 = 0x0000000E;
  963. break;
  964. case 0x04: /* 10BASE-TFD */
  965. csr13 = 0x00000001;
  966. csr14 = 0x00007F3D;
  967. csr15 = 0x00000008;
  968. break;
  969. }
  970. gpc = *p++<<16;
  971. gpc |= *p++<<24;
  972. gpd = *p++<<16;
  973. gpd |= *p<<24;
  974. csr32w(ctlr, 13, 0);
  975. csr32w(ctlr, 14, csr14);
  976. csr32w(ctlr, 15, gpc|csr15);
  977. delay(10);
  978. csr32w(ctlr, 15, gpd|csr15);
  979. csr32w(ctlr, 13, csr13);
  980. ctlr->csr6 = csr6;
  981. csr32w(ctlr, 6, ctlr->csr6);
  982. debug("type2mode: csr13 %8.8uX csr14 %8.8uX csr15 %8.8uX\n",
  983. csr13, csr14, csr15);
  984. debug("type2mode: gpc %8.8uX gpd %8.8uX csr6 %8.8uX\n",
  985. gpc, gpd, csr6);
  986. return 0;
  987. }
  988. static int
  989. type0link(Ctlr* ctlr, uchar* block)
  990. {
  991. int m, polarity, sense;
  992. m = (block[3]<<8)|block[2];
  993. sense = 1<<((m & 0x000E)>>1);
  994. if(m & 0x0080)
  995. polarity = sense;
  996. else
  997. polarity = 0;
  998. return (csr32r(ctlr, 12) & sense)^polarity;
  999. }
  1000. static int
  1001. type0mode(Ctlr* ctlr, uchar* block, int wait)
  1002. {
  1003. int csr6, m, timeo;
  1004. csr6 = Sc|Mbo|Hbd|Ca|TrMODE|Sb;
  1005. debug("type0: medium 0x%uX, fd %d: 0x%2.2uX 0x%2.2uX 0x%2.2uX 0x%2.2uX\n",
  1006. ctlr->medium, ctlr->fd, block[0], block[1], block[2], block[3]);
  1007. switch(block[0]){
  1008. default:
  1009. break;
  1010. case 0x04: /* 10BASE-TFD */
  1011. case 0x05: /* 100BASE-TXFD */
  1012. case 0x08: /* 100BASE-FXFD */
  1013. /*
  1014. * Don't attempt full-duplex
  1015. * unless explicitly requested.
  1016. */
  1017. if(!ctlr->fd)
  1018. return -1;
  1019. csr6 |= Fd;
  1020. break;
  1021. }
  1022. m = (block[3]<<8)|block[2];
  1023. if(m & 0x0001)
  1024. csr6 |= Ps;
  1025. if(m & 0x0010)
  1026. csr6 |= Ttm;
  1027. if(m & 0x0020)
  1028. csr6 |= Pcs;
  1029. if(m & 0x0040)
  1030. csr6 |= Scr;
  1031. csr32w(ctlr, 12, block[1]);
  1032. microdelay(10);
  1033. csr32w(ctlr, 6, csr6);
  1034. ctlr->csr6 = csr6;
  1035. if(!wait)
  1036. return 0;
  1037. for(timeo = 0; timeo < 30; timeo++){
  1038. if(type0link(ctlr, block))
  1039. return 0;
  1040. delay(100);
  1041. }
  1042. return -1;
  1043. }
  1044. static int
  1045. media21041(Ether* ether, int wait)
  1046. {
  1047. Ctlr* ctlr;
  1048. uchar *block;
  1049. int csr6, csr13, csr14, csr15, medium, timeo;
  1050. ctlr = ether->ctlr;
  1051. block = ctlr->infoblock[ctlr->curk];
  1052. debug("media21041: block[0] %2.2uX, medium %4.4uX sct %4.4uX\n",
  1053. block[0], ctlr->medium, ctlr->sct);
  1054. medium = block[0] & 0x3F;
  1055. if(ctlr->medium >= 0 && medium != ctlr->medium)
  1056. return 0;
  1057. if(ctlr->sct != 0x0800 && (ctlr->sct & 0x3F) != medium)
  1058. return 0;
  1059. csr6 = Sc|Mbo|Ca|TrMODE|Sb;
  1060. if(block[0] & 0x40){
  1061. csr13 = (block[2]<<8)|block[1];
  1062. csr14 = (block[4]<<8)|block[3];
  1063. csr15 = (block[6]<<8)|block[5];
  1064. }
  1065. else switch(medium){
  1066. default:
  1067. return -1;
  1068. case 0x00: /* 10BASE-T */
  1069. csr13 = 0xEF01;
  1070. csr14 = 0xFF3F;
  1071. csr15 = 0x0008;
  1072. break;
  1073. case 0x01: /* 10BASE-2 */
  1074. csr13 = 0xEF09;
  1075. csr14 = 0xF73D;
  1076. csr15 = 0x0006;
  1077. break;
  1078. case 0x02: /* 10BASE-5 */
  1079. csr13 = 0xEF09;
  1080. csr14 = 0xF73D;
  1081. csr15 = 0x000E;
  1082. break;
  1083. case 0x04: /* 10BASE-TFD */
  1084. csr13 = 0xEF01;
  1085. csr14 = 0xFF3D;
  1086. csr15 = 0x0008;
  1087. break;
  1088. }
  1089. csr32w(ctlr, 13, 0);
  1090. csr32w(ctlr, 14, csr14);
  1091. csr32w(ctlr, 15, csr15);
  1092. csr32w(ctlr, 13, csr13);
  1093. delay(10);
  1094. if(medium == 0x04)
  1095. csr6 |= Fd;
  1096. ctlr->csr6 = csr6;
  1097. csr32w(ctlr, 6, ctlr->csr6);
  1098. debug("media21041: csr6 %8.8uX csr13 %4.4uX csr14 %4.4uX csr15 %4.4uX\n",
  1099. csr6, csr13, csr14, csr15);
  1100. if(!wait)
  1101. return 0;
  1102. for(timeo = 0; timeo < 30; timeo++){
  1103. if(!(csr32r(ctlr, 12) & 0x0002)){
  1104. debug("media21041: ok: csr12 %4.4luX timeo %d\n",
  1105. csr32r(ctlr, 12), timeo);
  1106. return 10;
  1107. }
  1108. delay(100);
  1109. }
  1110. debug("media21041: !ok: csr12 %4.4luX\n", csr32r(ctlr, 12));
  1111. return -1;
  1112. }
  1113. static int
  1114. mediaxx(Ether* ether, int wait)
  1115. {
  1116. Ctlr* ctlr;
  1117. uchar *block;
  1118. ctlr = ether->ctlr;
  1119. block = ctlr->infoblock[ctlr->curk];
  1120. if(block[0] & 0x80){
  1121. switch(block[1]){
  1122. default:
  1123. return -1;
  1124. case 0:
  1125. if(ctlr->medium >= 0 && block[2] != ctlr->medium)
  1126. return 0;
  1127. /* need this test? */ if(ctlr->sct != 0x0800 && (ctlr->sct & 0x3F) != block[2])
  1128. return 0;
  1129. if(type0mode(ctlr, block+2, wait))
  1130. return 0;
  1131. break;
  1132. case 1:
  1133. if(typephymode(ctlr, block, wait))
  1134. return 0;
  1135. break;
  1136. case 2:
  1137. debug("type2: medium %d block[2] %d\n",
  1138. ctlr->medium, block[2]);
  1139. if(ctlr->medium >= 0 && ((block[2] & 0x3F) != ctlr->medium))
  1140. return 0;
  1141. if(type2mode(ctlr, block, wait))
  1142. return 0;
  1143. break;
  1144. case 3:
  1145. if(typephymode(ctlr, block, wait))
  1146. return 0;
  1147. break;
  1148. case 4:
  1149. debug("type4: medium %d block[2] %d\n",
  1150. ctlr->medium, block[2]);
  1151. if(ctlr->medium >= 0 && ((block[2] & 0x3F) != ctlr->medium))
  1152. return 0;
  1153. if(typesymmode(ctlr, block, wait))
  1154. return 0;
  1155. break;
  1156. }
  1157. }
  1158. else{
  1159. if(ctlr->medium >= 0 && block[0] != ctlr->medium)
  1160. return 0;
  1161. /* need this test? */if(ctlr->sct != 0x0800 && (ctlr->sct & 0x3F) != block[0])
  1162. return 0;
  1163. if(type0mode(ctlr, block, wait))
  1164. return 0;
  1165. }
  1166. if(ctlr->csr6){
  1167. if(!(ctlr->csr6 & Ps) || (ctlr->csr6 & Ttm))
  1168. return 10;
  1169. return 100;
  1170. }
  1171. return 0;
  1172. }
  1173. static int
  1174. media(Ether* ether, int wait)
  1175. {
  1176. Ctlr* ctlr;
  1177. int k, mbps;
  1178. ctlr = ether->ctlr;
  1179. for(k = 0; k < ctlr->k; k++){
  1180. switch(ctlr->id){
  1181. default:
  1182. mbps = mediaxx(ether, wait);
  1183. break;
  1184. case Tulip1: /* 21041 */
  1185. mbps = media21041(ether, wait);
  1186. break;
  1187. }
  1188. if(mbps > 0)
  1189. return mbps;
  1190. if(ctlr->curk == 0)
  1191. ctlr->curk = ctlr->k-1;
  1192. else
  1193. ctlr->curk--;
  1194. }
  1195. return 0;
  1196. }
  1197. static char* mediatable[9] = {
  1198. "10BASE-T", /* TP */
  1199. "10BASE-2", /* BNC */
  1200. "10BASE-5", /* AUI */
  1201. "100BASE-TX",
  1202. "10BASE-TFD",
  1203. "100BASE-TXFD",
  1204. "100BASE-T4",
  1205. "100BASE-FX",
  1206. "100BASE-FXFD",
  1207. };
  1208. static uchar en1207[] = { /* Accton EN1207-COMBO */
  1209. 0x00, 0x00, 0xE8, /* [0] vendor ethernet code */
  1210. 0x00, /* [3] spare */
  1211. 0x00, 0x08, /* [4] connection (LSB+MSB = 0x0800) */
  1212. 0x1F, /* [6] general purpose control */
  1213. 2, /* [7] block count */
  1214. 0x00, /* [8] media code (10BASE-TX) */
  1215. 0x0B, /* [9] general purpose port data */
  1216. 0x9E, 0x00, /* [10] command (LSB+MSB = 0x009E) */
  1217. 0x03, /* [8] media code (100BASE-TX) */
  1218. 0x1B, /* [9] general purpose port data */
  1219. 0x6D, 0x00, /* [10] command (LSB+MSB = 0x006D) */
  1220. /* There is 10BASE-2 as well, but... */
  1221. };
  1222. static uchar ana6910fx[] = { /* Adaptec (Cogent) ANA-6910FX */
  1223. 0x00, 0x00, 0x92, /* [0] vendor ethernet code */
  1224. 0x00, /* [3] spare */
  1225. 0x00, 0x08, /* [4] connection (LSB+MSB = 0x0800) */
  1226. 0x3F, /* [6] general purpose control */
  1227. 1, /* [7] block count */
  1228. 0x07, /* [8] media code (100BASE-FX) */
  1229. 0x03, /* [9] general purpose port data */
  1230. 0x2D, 0x00 /* [10] command (LSB+MSB = 0x000D) */
  1231. };
  1232. static uchar smc9332[] = { /* SMC 9332 */
  1233. 0x00, 0x00, 0xC0, /* [0] vendor ethernet code */
  1234. 0x00, /* [3] spare */
  1235. 0x00, 0x08, /* [4] connection (LSB+MSB = 0x0800) */
  1236. 0x1F, /* [6] general purpose control */
  1237. 2, /* [7] block count */
  1238. 0x00, /* [8] media code (10BASE-TX) */
  1239. 0x00, /* [9] general purpose port data */
  1240. 0x9E, 0x00, /* [10] command (LSB+MSB = 0x009E) */
  1241. 0x03, /* [8] media code (100BASE-TX) */
  1242. 0x09, /* [9] general purpose port data */
  1243. 0x6D, 0x00, /* [10] command (LSB+MSB = 0x006D) */
  1244. };
  1245. static uchar* leaf21140[] = {
  1246. en1207, /* Accton EN1207-COMBO */
  1247. ana6910fx, /* Adaptec (Cogent) ANA-6910FX */
  1248. smc9332, /* SMC 9332 */
  1249. nil,
  1250. };
  1251. /*
  1252. * Copied to ctlr->srom at offset 20.
  1253. */
  1254. static uchar leafpnic[] = {
  1255. 0x00, 0x00, 0x00, 0x00, /* MAC address */
  1256. 0x00, 0x00,
  1257. 0x00, /* controller 0 device number */
  1258. 0x1E, 0x00, /* controller 0 info leaf offset */
  1259. 0x00, /* reserved */
  1260. 0x00, 0x08, /* selected connection type */
  1261. 0x00, /* general purpose control */
  1262. 0x01, /* block count */
  1263. 0x8C, /* format indicator and count */
  1264. 0x01, /* block type */
  1265. 0x00, /* PHY number */
  1266. 0x00, /* GPR sequence length */
  1267. 0x00, /* reset sequence length */
  1268. 0x00, 0x78, /* media capabilities */
  1269. 0xE0, 0x01, /* Nway advertisment */
  1270. 0x00, 0x50, /* FDX bitmap */
  1271. 0x00, 0x18, /* TTM bitmap */
  1272. };
  1273. static int
  1274. srom(Ctlr* ctlr)
  1275. {
  1276. int i, k, oui, phy, x;
  1277. uchar *p;
  1278. /*
  1279. * This is a partial decoding of the SROM format described in
  1280. * 'Digital Semiconductor 21X4 Serial ROM Format, Version 4.05,
  1281. * 2-Mar-98'. Only the 2114[03] are handled, support for other
  1282. * controllers can be added as needed.
  1283. * Do a dummy read first to get the size and allocate ctlr->srom.
  1284. */
  1285. sromr(ctlr, 0);
  1286. if(ctlr->srom == nil)
  1287. ctlr->srom = malloc((1<<ctlr->sromsz)*sizeof(ushort));
  1288. for(i = 0; i < (1<<ctlr->sromsz); i++){
  1289. x = sromr(ctlr, i);
  1290. ctlr->srom[2*i] = x;
  1291. ctlr->srom[2*i+1] = x>>8;
  1292. }
  1293. if(DEBUG){
  1294. print("srom:");
  1295. for(i = 0; i < ((1<<ctlr->sromsz)*sizeof(ushort)); i++){
  1296. if(i && ((i & 0x0F) == 0))
  1297. print("\n ");
  1298. print(" %2.2uX", ctlr->srom[i]);
  1299. }
  1300. print("\n");
  1301. }
  1302. /*
  1303. * There are at least 2 SROM layouts:
  1304. * e.g. Digital EtherWORKS station address at offset 20;
  1305. * this complies with the 21140A SROM
  1306. * application note from Digital;
  1307. * e.g. SMC9332 station address at offset 0 followed by
  1308. * 2 additional bytes, repeated at offset
  1309. * 6; the 8 bytes are also repeated in
  1310. * reverse order at offset 8.
  1311. * To check which it is, read the SROM and check for the repeating
  1312. * patterns of the non-compliant cards; if that fails use the one at
  1313. * offset 20.
  1314. */
  1315. ctlr->sromea = ctlr->srom;
  1316. for(i = 0; i < 8; i++){
  1317. x = ctlr->srom[i];
  1318. if(x != ctlr->srom[15-i] || x != ctlr->srom[16+i]){
  1319. ctlr->sromea = &ctlr->srom[20];
  1320. break;
  1321. }
  1322. }
  1323. /*
  1324. * Fake up the SROM for the PNIC and AMDtek.
  1325. * They look like a 21140 with a PHY.
  1326. * The MAC address is byte-swapped in the orginal
  1327. * PNIC SROM data.
  1328. */
  1329. if(ctlr->id == Pnic){
  1330. memmove(&ctlr->srom[20], leafpnic, sizeof(leafpnic));
  1331. for(i = 0; i < Eaddrlen; i += 2){
  1332. ctlr->srom[20+i] = ctlr->srom[i+1];
  1333. ctlr->srom[20+i+1] = ctlr->srom[i];
  1334. }
  1335. }
  1336. if(ctlr->id == CentaurP || ctlr->id == CentaurPcb){
  1337. memmove(&ctlr->srom[20], leafpnic, sizeof(leafpnic));
  1338. for(i = 0; i < Eaddrlen; i += 2){
  1339. ctlr->srom[20+i] = ctlr->srom[8+i];
  1340. ctlr->srom[20+i+1] = ctlr->srom[8+i+1];
  1341. }
  1342. }
  1343. /*
  1344. * Next, try to find the info leaf in the SROM for media detection.
  1345. * If it's a non-conforming card try to match the vendor ethernet code
  1346. * and point p at a fake info leaf with compact 21140 entries.
  1347. */
  1348. if(ctlr->sromea == ctlr->srom){
  1349. p = nil;
  1350. for(i = 0; leaf21140[i] != nil; i++){
  1351. if(memcmp(leaf21140[i], ctlr->sromea, 3) == 0){
  1352. p = &leaf21140[i][4];
  1353. break;
  1354. }
  1355. }
  1356. if(p == nil)
  1357. return -1;
  1358. }
  1359. else
  1360. p = &ctlr->srom[(ctlr->srom[28]<<8)|ctlr->srom[27]];
  1361. /*
  1362. * Set up the info needed for later media detection.
  1363. * For the 21140, set the general-purpose mask in CSR12.
  1364. * The info block entries are stored in order of increasing
  1365. * precedence, so detection will work backwards through the
  1366. * stored indexes into ctlr->srom.
  1367. * If an entry is found which matches the selected connection
  1368. * type, save the index. Otherwise, start at the last entry.
  1369. * If any MII entries are found (type 1 and 3 blocks), scan
  1370. * for PHYs.
  1371. */
  1372. ctlr->leaf = p;
  1373. ctlr->sct = *p++;
  1374. ctlr->sct |= *p++<<8;
  1375. if(ctlr->id != Tulip3 && ctlr->id != Tulip1){
  1376. csr32w(ctlr, 12, Gpc|*p++);
  1377. delay(200);
  1378. }
  1379. ctlr->k = *p++;
  1380. if(ctlr->k >= nelem(ctlr->infoblock))
  1381. ctlr->k = nelem(ctlr->infoblock)-1;
  1382. ctlr->sctk = ctlr->k-1;
  1383. phy = 0;
  1384. for(k = 0; k < ctlr->k; k++){
  1385. ctlr->infoblock[k] = p;
  1386. if(ctlr->id == Tulip1){
  1387. debug("type21041: 0x%2.2uX\n", p[0]);
  1388. if(ctlr->sct != 0x0800 && *p == (ctlr->sct & 0xFF))
  1389. ctlr->sctk = k;
  1390. if(*p & 0x40)
  1391. p += 7;
  1392. else
  1393. p += 1;
  1394. }
  1395. /*
  1396. * The RAMIX PMC665 has a badly-coded SROM,
  1397. * hence the test for 21143 and type 3.
  1398. */
  1399. else if((*p & 0x80) || (ctlr->id == Tulip3 && *(p+1) == 3)){
  1400. *p |= 0x80;
  1401. if(*(p+1) == 1 || *(p+1) == 3)
  1402. phy = 1;
  1403. if(*(p+1) == 5)
  1404. ctlr->type5block = p;
  1405. p += (*p & ~0x80)+1;
  1406. }
  1407. else{
  1408. debug("type0: 0x%2.2uX 0x%2.2uX 0x%2.2uX 0x%2.2uX\n",
  1409. p[0], p[1], p[2], p[3]);
  1410. if(ctlr->sct != 0x0800 && *p == (ctlr->sct & 0xFF))
  1411. ctlr->sctk = k;
  1412. p += 4;
  1413. }
  1414. }
  1415. ctlr->curk = ctlr->sctk;
  1416. debug("sct 0x%uX medium 0x%uX k %d curk %d phy %d\n",
  1417. ctlr->sct, ctlr->medium, ctlr->k, ctlr->curk, phy);
  1418. if(phy){
  1419. x = 0;
  1420. for(k = 0; k < nelem(ctlr->phy); k++){
  1421. if((ctlr->id == CentaurP || ctlr->id == CentaurPcb) && k != 1)
  1422. continue;
  1423. if((oui = miir(ctlr, k, 2)) == -1 || oui == 0)
  1424. continue;
  1425. debug("phy reg 2 %4.4uX\n", oui);
  1426. if(DEBUG){
  1427. oui = (oui & 0x3FF)<<6;
  1428. oui |= miir(ctlr, k, 3)>>10;
  1429. miir(ctlr, k, 1);
  1430. debug("phy%d: index %d oui %uX reg1 %uX\n",
  1431. x, k, oui, miir(ctlr, k, 1));
  1432. USED(oui);
  1433. }
  1434. ctlr->phy[x] = k;
  1435. }
  1436. }
  1437. ctlr->fd = 0;
  1438. ctlr->medium = -1;
  1439. return 0;
  1440. }
  1441. static void
  1442. dec2114xpci(void)
  1443. {
  1444. Ctlr *ctlr;
  1445. Pcidev *p;
  1446. int x;
  1447. p = nil;
  1448. while(p = pcimatch(p, 0, 0)){
  1449. if(p->ccrb != 0x02 || p->ccru != 0)
  1450. continue;
  1451. switch((p->did<<16)|p->vid){
  1452. default:
  1453. continue;
  1454. case Tulip3: /* 21143 */
  1455. /*
  1456. * Exit sleep mode.
  1457. */
  1458. x = pcicfgr32(p, 0x40);
  1459. x &= ~0xC0000000;
  1460. pcicfgw32(p, 0x40, x);
  1461. /*FALLTHROUGH*/
  1462. case Tulip0: /* 21140 */
  1463. case Tulip1: /* 21041 */
  1464. case Pnic: /* PNIC */
  1465. case Pnic2: /* PNIC-II */
  1466. case CentaurP: /* ADMtek */
  1467. case CentaurPcb: /* ADMtek CardBus */
  1468. break;
  1469. }
  1470. /*
  1471. * bar[0] is the I/O port register address and
  1472. * bar[1] is the memory-mapped register address.
  1473. */
  1474. ctlr = malloc(sizeof(Ctlr));
  1475. ctlr->port = p->mem[0].bar & ~0x01;
  1476. ctlr->pcidev = p;
  1477. ctlr->id = (p->did<<16)|p->vid;
  1478. if(ioalloc(ctlr->port, p->mem[0].size, 0, "dec2114x") < 0){
  1479. print("dec2114x: port 0x%uX in use\n", ctlr->port);
  1480. free(ctlr);
  1481. continue;
  1482. }
  1483. /*
  1484. * Some cards (e.g. ANA-6910FX) seem to need the Ps bit
  1485. * set or they don't always work right after a hardware
  1486. * reset.
  1487. */
  1488. csr32w(ctlr, 6, Mbo|Ps);
  1489. softreset(ctlr);
  1490. if(srom(ctlr)){
  1491. iofree(ctlr->port);
  1492. free(ctlr);
  1493. continue;
  1494. }
  1495. switch(ctlr->id){
  1496. default:
  1497. break;
  1498. case Pnic: /* PNIC */
  1499. /*
  1500. * Turn off the jabber timer.
  1501. */
  1502. csr32w(ctlr, 15, 0x00000001);
  1503. break;
  1504. case CentaurP:
  1505. case CentaurPcb:
  1506. /*
  1507. * Nice - the register offsets change from *8 to *4
  1508. * for CSR16 and up...
  1509. * CSR25/26 give the MAC address read from the SROM.
  1510. * Don't really need to use this other than as a check,
  1511. * the SROM will be read in anyway so the value there
  1512. * can be used directly.
  1513. */
  1514. debug("csr25 %8.8luX csr26 %8.8luX\n",
  1515. inl(ctlr->port+0xA4), inl(ctlr->port+0xA8));
  1516. debug("phyidr1 %4.4luX phyidr2 %4.4luX\n",
  1517. inl(ctlr->port+0xBC), inl(ctlr->port+0xC0));
  1518. break;
  1519. }
  1520. if(ctlrhead != nil)
  1521. ctlrtail->next = ctlr;
  1522. else
  1523. ctlrhead = ctlr;
  1524. ctlrtail = ctlr;
  1525. }
  1526. }
  1527. static int
  1528. reset(Ether* ether)
  1529. {
  1530. Ctlr *ctlr;
  1531. int i, x;
  1532. uchar ea[Eaddrlen];
  1533. static int scandone;
  1534. if(scandone == 0){
  1535. dec2114xpci();
  1536. scandone = 1;
  1537. }
  1538. /*
  1539. * Any adapter matches if no ether->port is supplied,
  1540. * otherwise the ports must match.
  1541. */
  1542. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  1543. if(ctlr->active)
  1544. continue;
  1545. if(ether->port == 0 || ether->port == ctlr->port){
  1546. ctlr->active = 1;
  1547. break;
  1548. }
  1549. }
  1550. if(ctlr == nil)
  1551. return -1;
  1552. ether->ctlr = ctlr;
  1553. ether->port = ctlr->port;
  1554. ether->irq = ctlr->pcidev->intl;
  1555. ether->tbdf = ctlr->pcidev->tbdf;
  1556. /*
  1557. * Check if the adapter's station address is to be overridden.
  1558. * If not, read it from the EEPROM and set in ether->ea prior to
  1559. * loading the station address in the hardware.
  1560. */
  1561. memset(ea, 0, Eaddrlen);
  1562. if(memcmp(ea, ether->ea, Eaddrlen) == 0)
  1563. memmove(ether->ea, ctlr->sromea, Eaddrlen);
  1564. /*
  1565. * Look for a medium override in case there's no autonegotiation
  1566. * (no MII) or the autonegotiation fails.
  1567. */
  1568. for(i = 0; i < ether->nopt; i++){
  1569. if(cistrcmp(ether->opt[i], "FD") == 0){
  1570. ctlr->fd = 1;
  1571. continue;
  1572. }
  1573. for(x = 0; x < nelem(mediatable); x++){
  1574. debug("compare <%s> <%s>\n", mediatable[x],
  1575. ether->opt[i]);
  1576. if(cistrcmp(mediatable[x], ether->opt[i]))
  1577. continue;
  1578. ctlr->medium = x;
  1579. switch(ctlr->medium){
  1580. default:
  1581. ctlr->fd = 0;
  1582. break;
  1583. case 0x04: /* 10BASE-TFD */
  1584. case 0x05: /* 100BASE-TXFD */
  1585. case 0x08: /* 100BASE-FXFD */
  1586. ctlr->fd = 1;
  1587. break;
  1588. }
  1589. break;
  1590. }
  1591. }
  1592. ether->mbps = media(ether, 1);
  1593. /*
  1594. * Initialise descriptor rings, ethernet address.
  1595. */
  1596. ctlr->nrdr = Nrde;
  1597. ctlr->ntdr = Ntde;
  1598. pcisetbme(ctlr->pcidev);
  1599. ctlrinit(ether);
  1600. /*
  1601. * Linkage to the generic ethernet driver.
  1602. */
  1603. ether->attach = attach;
  1604. ether->transmit = transmit;
  1605. ether->interrupt = interrupt;
  1606. ether->ifstat = ifstat;
  1607. ether->arg = ether;
  1608. ether->shutdown = shutdown;
  1609. ether->multicast = multicast;
  1610. ether->promiscuous = promiscuous;
  1611. return 0;
  1612. }
  1613. void
  1614. ether2114xlink(void)
  1615. {
  1616. addethercard("2114x", reset);
  1617. addethercard("21140", reset);
  1618. }