pci.c 29 KB

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  1. /*
  2. * PCI support code.
  3. * Needs a massive rewrite.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #define DBG if(0) pcilog
  13. struct
  14. {
  15. char output[16384];
  16. int ptr;
  17. }PCICONS;
  18. int
  19. pcilog(char *fmt, ...)
  20. {
  21. int n;
  22. va_list arg;
  23. char buf[PRINTSIZE];
  24. va_start(arg, fmt);
  25. n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;
  26. va_end(arg);
  27. memmove(PCICONS.output+PCICONS.ptr, buf, n);
  28. PCICONS.ptr += n;
  29. return n;
  30. }
  31. enum
  32. { /* configuration mechanism #1 */
  33. PciADDR = 0xCF8, /* CONFIG_ADDRESS */
  34. PciDATA = 0xCFC, /* CONFIG_DATA */
  35. /* configuration mechanism #2 */
  36. PciCSE = 0xCF8, /* configuration space enable */
  37. PciFORWARD = 0xCFA, /* which bus */
  38. MaxFNO = 7,
  39. MaxUBN = 255,
  40. };
  41. enum
  42. { /* command register */
  43. IOen = (1<<0),
  44. MEMen = (1<<1),
  45. MASen = (1<<2),
  46. MemWrInv = (1<<4),
  47. PErrEn = (1<<6),
  48. SErrEn = (1<<8),
  49. };
  50. static Lock pcicfglock;
  51. static Lock pcicfginitlock;
  52. static int pcicfgmode = -1;
  53. static int pcimaxbno = 7;
  54. static int pcimaxdno;
  55. static Pcidev* pciroot;
  56. static Pcidev* pcilist;
  57. static Pcidev* pcitail;
  58. static int nobios, nopcirouting;
  59. static BIOS32si* pcibiossi;
  60. static int pcicfgrw8raw(int, int, int, int);
  61. static int pcicfgrw16raw(int, int, int, int);
  62. static int pcicfgrw32raw(int, int, int, int);
  63. static int (*pcicfgrw8)(int, int, int, int) = pcicfgrw8raw;
  64. static int (*pcicfgrw16)(int, int, int, int) = pcicfgrw16raw;
  65. static int (*pcicfgrw32)(int, int, int, int) = pcicfgrw32raw;
  66. static char* bustypes[] = {
  67. "CBUSI",
  68. "CBUSII",
  69. "EISA",
  70. "FUTURE",
  71. "INTERN",
  72. "ISA",
  73. "MBI",
  74. "MBII",
  75. "MCA",
  76. "MPI",
  77. "MPSA",
  78. "NUBUS",
  79. "PCI",
  80. "PCMCIA",
  81. "TC",
  82. "VL",
  83. "VME",
  84. "XPRESS",
  85. };
  86. #pragma varargck type "T" int
  87. static int
  88. tbdffmt(Fmt* fmt)
  89. {
  90. char *p;
  91. int l, r, type, tbdf;
  92. if((p = malloc(READSTR)) == nil)
  93. return fmtstrcpy(fmt, "(tbdfconv)");
  94. switch(fmt->r){
  95. case 'T':
  96. tbdf = va_arg(fmt->args, int);
  97. type = BUSTYPE(tbdf);
  98. if(type < nelem(bustypes))
  99. l = snprint(p, READSTR, bustypes[type]);
  100. else
  101. l = snprint(p, READSTR, "%d", type);
  102. snprint(p+l, READSTR-l, ".%d.%d.%d",
  103. BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
  104. break;
  105. default:
  106. snprint(p, READSTR, "(tbdfconv)");
  107. break;
  108. }
  109. r = fmtstrcpy(fmt, p);
  110. free(p);
  111. return r;
  112. }
  113. ulong
  114. pcibarsize(Pcidev *p, int rno)
  115. {
  116. ulong v, size;
  117. v = pcicfgrw32(p->tbdf, rno, 0, 1);
  118. pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
  119. size = pcicfgrw32(p->tbdf, rno, 0, 1);
  120. if(v & 1)
  121. size |= 0xFFFF0000;
  122. pcicfgrw32(p->tbdf, rno, v, 0);
  123. return -(size & ~0x0F);
  124. }
  125. static int
  126. pcisizcmp(void *a, void *b)
  127. {
  128. Pcisiz *aa, *bb;
  129. aa = a;
  130. bb = b;
  131. return aa->siz - bb->siz;
  132. }
  133. static ulong
  134. pcimask(ulong v)
  135. {
  136. ulong m;
  137. m = BI2BY*sizeof(v);
  138. for(m = 1<<(m-1); m != 0; m >>= 1) {
  139. if(m & v)
  140. break;
  141. }
  142. m--;
  143. if((v & m) == 0)
  144. return v;
  145. v |= m;
  146. return v+1;
  147. }
  148. static void
  149. pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
  150. {
  151. Pcidev *p;
  152. int ntb, i, size, rno, hole;
  153. ulong v, mema, ioa, sioa, smema, base, limit;
  154. Pcisiz *table, *tptr, *mtb, *itb;
  155. if(!nobios)
  156. return;
  157. ioa = *pioa;
  158. mema = *pmema;
  159. DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
  160. wrreg, root->tbdf, mema, ioa);
  161. ntb = 0;
  162. for(p = root; p != nil; p = p->link)
  163. ntb++;
  164. ntb *= (PciCIS-PciBAR0)/4;
  165. table = malloc(2*ntb*sizeof(Pcisiz));
  166. itb = table;
  167. mtb = table+ntb;
  168. /*
  169. * Build a table of sizes
  170. */
  171. for(p = root; p != nil; p = p->link) {
  172. if(p->ccrb == 0x06) {
  173. if(p->ccru != 0x04 || p->bridge == nil) {
  174. // DBG("pci: ignored bridge %T\n", p->tbdf);
  175. continue;
  176. }
  177. sioa = ioa;
  178. smema = mema;
  179. pcibusmap(p->bridge, &smema, &sioa, 0);
  180. hole = pcimask(smema-mema);
  181. if(hole < (1<<20))
  182. hole = 1<<20;
  183. p->mema.size = hole;
  184. hole = pcimask(sioa-ioa);
  185. if(hole < (1<<12))
  186. hole = 1<<12;
  187. p->ioa.size = hole;
  188. itb->dev = p;
  189. itb->bar = -1;
  190. itb->siz = p->ioa.size;
  191. itb++;
  192. mtb->dev = p;
  193. mtb->bar = -1;
  194. mtb->siz = p->mema.size;
  195. mtb++;
  196. continue;
  197. }
  198. for(i = 0; i <= 5; i++) {
  199. rno = PciBAR0 + i*4;
  200. v = pcicfgrw32(p->tbdf, rno, 0, 1);
  201. size = pcibarsize(p, rno);
  202. if(size == 0)
  203. continue;
  204. if(v & 1) {
  205. itb->dev = p;
  206. itb->bar = i;
  207. itb->siz = size;
  208. itb++;
  209. }
  210. else {
  211. mtb->dev = p;
  212. mtb->bar = i;
  213. mtb->siz = size;
  214. mtb++;
  215. }
  216. p->mem[i].size = size;
  217. }
  218. }
  219. /*
  220. * Sort both tables IO smallest first, Memory largest
  221. */
  222. qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp);
  223. tptr = table+ntb;
  224. qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
  225. /*
  226. * Allocate IO address space on this bus
  227. */
  228. for(tptr = table; tptr < itb; tptr++) {
  229. hole = tptr->siz;
  230. if(tptr->bar == -1)
  231. hole = 1<<12;
  232. ioa = (ioa+hole-1) & ~(hole-1);
  233. p = tptr->dev;
  234. if(tptr->bar == -1)
  235. p->ioa.bar = ioa;
  236. else {
  237. p->pcr |= IOen;
  238. p->mem[tptr->bar].bar = ioa|1;
  239. if(wrreg)
  240. pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
  241. }
  242. ioa += tptr->siz;
  243. }
  244. /*
  245. * Allocate Memory address space on this bus
  246. */
  247. for(tptr = table+ntb; tptr < mtb; tptr++) {
  248. hole = tptr->siz;
  249. if(tptr->bar == -1)
  250. hole = 1<<20;
  251. mema = (mema+hole-1) & ~(hole-1);
  252. p = tptr->dev;
  253. if(tptr->bar == -1)
  254. p->mema.bar = mema;
  255. else {
  256. p->pcr |= MEMen;
  257. p->mem[tptr->bar].bar = mema;
  258. if(wrreg)
  259. pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0);
  260. }
  261. mema += tptr->siz;
  262. }
  263. *pmema = mema;
  264. *pioa = ioa;
  265. free(table);
  266. if(wrreg == 0)
  267. return;
  268. /*
  269. * Finally set all the bridge addresses & registers
  270. */
  271. for(p = root; p != nil; p = p->link) {
  272. if(p->bridge == nil) {
  273. pcicfgrw8(p->tbdf, PciLTR, 64, 0);
  274. p->pcr |= MASen;
  275. pcicfgrw16(p->tbdf, PciPCR, p->pcr, 0);
  276. continue;
  277. }
  278. base = p->ioa.bar;
  279. limit = base+p->ioa.size-1;
  280. v = pcicfgrw32(p->tbdf, PciIBR, 0, 1);
  281. v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8);
  282. pcicfgrw32(p->tbdf, PciIBR, v, 0);
  283. v = (limit & 0xFFFF0000)|(base>>16);
  284. pcicfgrw32(p->tbdf, PciIUBR, v, 0);
  285. base = p->mema.bar;
  286. limit = base+p->mema.size-1;
  287. v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16);
  288. pcicfgrw32(p->tbdf, PciMBR, v, 0);
  289. /*
  290. * Disable memory prefetch
  291. */
  292. pcicfgrw32(p->tbdf, PciPMBR, 0x0000FFFF, 0);
  293. pcicfgrw8(p->tbdf, PciLTR, 64, 0);
  294. /*
  295. * Enable the bridge
  296. */
  297. p->pcr |= IOen|MEMen|MASen;
  298. pcicfgrw32(p->tbdf, PciPCR, 0xFFFF0000|p->pcr , 0);
  299. sioa = p->ioa.bar;
  300. smema = p->mema.bar;
  301. pcibusmap(p->bridge, &smema, &sioa, 1);
  302. }
  303. }
  304. static int
  305. pcilscan(int bno, Pcidev** list)
  306. {
  307. Pcidev *p, *head, *tail;
  308. int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
  309. maxubn = bno;
  310. head = nil;
  311. tail = nil;
  312. for(dno = 0; dno <= pcimaxdno; dno++){
  313. maxfno = 0;
  314. for(fno = 0; fno <= maxfno; fno++){
  315. /*
  316. * For this possible device, form the
  317. * bus+device+function triplet needed to address it
  318. * and try to read the vendor and device ID.
  319. * If successful, allocate a device struct and
  320. * start to fill it in with some useful information
  321. * from the device's configuration space.
  322. */
  323. tbdf = MKBUS(BusPCI, bno, dno, fno);
  324. l = pcicfgrw32(tbdf, PciVID, 0, 1);
  325. if(l == 0xFFFFFFFF || l == 0)
  326. continue;
  327. p = malloc(sizeof(*p));
  328. p->tbdf = tbdf;
  329. p->vid = l;
  330. p->did = l>>16;
  331. if(pcilist != nil)
  332. pcitail->list = p;
  333. else
  334. pcilist = p;
  335. pcitail = p;
  336. p->pcr = pcicfgr16(p, PciPCR);
  337. p->rid = pcicfgr8(p, PciRID);
  338. p->ccrp = pcicfgr8(p, PciCCRp);
  339. p->ccru = pcicfgr8(p, PciCCRu);
  340. p->ccrb = pcicfgr8(p, PciCCRb);
  341. p->cls = pcicfgr8(p, PciCLS);
  342. p->ltr = pcicfgr8(p, PciLTR);
  343. p->intl = pcicfgr8(p, PciINTL);
  344. /*
  345. * If the device is a multi-function device adjust the
  346. * loop count so all possible functions are checked.
  347. */
  348. hdt = pcicfgr8(p, PciHDT);
  349. if(hdt & 0x80)
  350. maxfno = MaxFNO;
  351. /*
  352. * If appropriate, read the base address registers
  353. * and work out the sizes.
  354. */
  355. switch(p->ccrb) {
  356. case 0x01: /* mass storage controller */
  357. case 0x02: /* network controller */
  358. case 0x03: /* display controller */
  359. case 0x04: /* multimedia device */
  360. case 0x07: /* simple comm. controllers */
  361. case 0x08: /* base system peripherals */
  362. case 0x09: /* input devices */
  363. case 0x0A: /* docking stations */
  364. case 0x0B: /* processors */
  365. case 0x0C: /* serial bus controllers */
  366. if((hdt & 0x7F) != 0)
  367. break;
  368. rno = PciBAR0 - 4;
  369. for(i = 0; i < nelem(p->mem); i++) {
  370. rno += 4;
  371. p->mem[i].bar = pcicfgr32(p, rno);
  372. p->mem[i].size = pcibarsize(p, rno);
  373. }
  374. break;
  375. case 0x00:
  376. case 0x05: /* memory controller */
  377. case 0x06: /* bridge device */
  378. default:
  379. break;
  380. }
  381. if(head != nil)
  382. tail->link = p;
  383. else
  384. head = p;
  385. tail = p;
  386. }
  387. }
  388. *list = head;
  389. for(p = head; p != nil; p = p->link){
  390. /*
  391. * Find PCI-PCI bridges and recursively descend the tree.
  392. */
  393. if(p->ccrb != 0x06 || p->ccru != 0x04)
  394. continue;
  395. /*
  396. * If the secondary or subordinate bus number is not
  397. * initialised try to do what the PCI BIOS should have
  398. * done and fill in the numbers as the tree is descended.
  399. * On the way down the subordinate bus number is set to
  400. * the maximum as it's not known how many buses are behind
  401. * this one; the final value is set on the way back up.
  402. */
  403. sbn = pcicfgr8(p, PciSBN);
  404. ubn = pcicfgr8(p, PciUBN);
  405. if(sbn == 0 || ubn == 0 || nobios) {
  406. sbn = maxubn+1;
  407. /*
  408. * Make sure memory, I/O and master enables are
  409. * off, set the primary, secondary and subordinate
  410. * bus numbers and clear the secondary status before
  411. * attempting to scan the secondary bus.
  412. *
  413. * Initialisation of the bridge should be done here.
  414. */
  415. pcicfgw32(p, PciPCR, 0xFFFF0000);
  416. l = (MaxUBN<<16)|(sbn<<8)|bno;
  417. pcicfgw32(p, PciPBN, l);
  418. pcicfgw16(p, PciSPSR, 0xFFFF);
  419. maxubn = pcilscan(sbn, &p->bridge);
  420. l = (maxubn<<16)|(sbn<<8)|bno;
  421. pcicfgw32(p, PciPBN, l);
  422. }
  423. else {
  424. if(ubn > maxubn)
  425. maxubn = ubn;
  426. pcilscan(sbn, &p->bridge);
  427. }
  428. }
  429. return maxubn;
  430. }
  431. int
  432. pciscan(int bno, Pcidev **list)
  433. {
  434. int ubn;
  435. lock(&pcicfginitlock);
  436. ubn = pcilscan(bno, list);
  437. unlock(&pcicfginitlock);
  438. return ubn;
  439. }
  440. static uchar
  441. pIIxget(Pcidev *router, uchar link)
  442. {
  443. uchar pirq;
  444. /* link should be 0x60, 0x61, 0x62, 0x63 */
  445. pirq = pcicfgr8(router, link);
  446. return (pirq < 16)? pirq: 0;
  447. }
  448. static void
  449. pIIxset(Pcidev *router, uchar link, uchar irq)
  450. {
  451. pcicfgw8(router, link, irq);
  452. }
  453. static uchar
  454. viaget(Pcidev *router, uchar link)
  455. {
  456. uchar pirq;
  457. /* link should be 1, 2, 3, 5 */
  458. pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
  459. return (link & 1)? (pirq >> 4): (pirq & 15);
  460. }
  461. static void
  462. viaset(Pcidev *router, uchar link, uchar irq)
  463. {
  464. uchar pirq;
  465. pirq = pcicfgr8(router, 0x55 + (link >> 1));
  466. pirq &= (link & 1)? 0x0f: 0xf0;
  467. pirq |= (link & 1)? (irq << 4): (irq & 15);
  468. pcicfgw8(router, 0x55 + (link>>1), pirq);
  469. }
  470. static uchar
  471. optiget(Pcidev *router, uchar link)
  472. {
  473. uchar pirq = 0;
  474. /* link should be 0x02, 0x12, 0x22, 0x32 */
  475. if ((link & 0xcf) == 0x02)
  476. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  477. return (link & 0x10)? (pirq >> 4): (pirq & 15);
  478. }
  479. static void
  480. optiset(Pcidev *router, uchar link, uchar irq)
  481. {
  482. uchar pirq;
  483. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  484. pirq &= (link & 0x10)? 0x0f : 0xf0;
  485. pirq |= (link & 0x10)? (irq << 4): (irq & 15);
  486. pcicfgw8(router, 0xb8 + (link >> 5), pirq);
  487. }
  488. static uchar
  489. aliget(Pcidev *router, uchar link)
  490. {
  491. /* No, you're not dreaming */
  492. static const uchar map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
  493. uchar pirq;
  494. /* link should be 0x01..0x08 */
  495. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  496. return (link & 1)? map[pirq&15]: map[pirq>>4];
  497. }
  498. static void
  499. aliset(Pcidev *router, uchar link, uchar irq)
  500. {
  501. /* Inverse of map in aliget */
  502. static const uchar map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
  503. uchar pirq;
  504. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  505. pirq &= (link & 1)? 0x0f: 0xf0;
  506. pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
  507. pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
  508. }
  509. static uchar
  510. cyrixget(Pcidev *router, uchar link)
  511. {
  512. uchar pirq;
  513. /* link should be 1, 2, 3, 4 */
  514. pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
  515. return ((link & 1)? pirq >> 4: pirq & 15);
  516. }
  517. static void
  518. cyrixset(Pcidev *router, uchar link, uchar irq)
  519. {
  520. uchar pirq;
  521. pirq = pcicfgr8(router, 0x5c + (link>>1));
  522. pirq &= (link & 1)? 0x0f: 0xf0;
  523. pirq |= (link & 1)? (irq << 4): (irq & 15);
  524. pcicfgw8(router, 0x5c + (link>>1), pirq);
  525. }
  526. typedef struct Bridge Bridge;
  527. struct Bridge
  528. {
  529. ushort vid;
  530. ushort did;
  531. uchar (*get)(Pcidev *, uchar);
  532. void (*set)(Pcidev *, uchar, uchar);
  533. };
  534. static Bridge southbridges[] = {
  535. { 0x8086, 0x122e, pIIxget, pIIxset }, // Intel 82371FB
  536. { 0x8086, 0x1234, pIIxget, pIIxset }, // Intel 82371MX
  537. { 0x8086, 0x7000, pIIxget, pIIxset }, // Intel 82371SB
  538. { 0x8086, 0x7110, pIIxget, pIIxset }, // Intel 82371AB
  539. { 0x8086, 0x7198, pIIxget, pIIxset }, // Intel 82443MX (fn 1)
  540. { 0x8086, 0x2410, pIIxget, pIIxset }, // Intel 82801AA
  541. { 0x8086, 0x2420, pIIxget, pIIxset }, // Intel 82801AB
  542. { 0x8086, 0x2440, pIIxget, pIIxset }, // Intel 82801BA
  543. { 0x8086, 0x244c, pIIxget, pIIxset }, // Intel 82801BAM
  544. { 0x8086, 0x2480, pIIxget, pIIxset }, // Intel 82801CA
  545. { 0x8086, 0x248c, pIIxget, pIIxset }, // Intel 82801CAM
  546. { 0x8086, 0x24c0, pIIxget, pIIxset }, // Intel 82801DBL
  547. { 0x8086, 0x24cc, pIIxget, pIIxset }, // Intel 82801DBM
  548. { 0x8086, 0x24d0, pIIxget, pIIxset }, // Intel 82801EB
  549. { 0x8086, 0x2640, pIIxget, pIIxset }, // Intel 82801FB
  550. { 0x8086, 0x27b8, pIIxget, pIIxset }, // Intel 82801GB
  551. { 0x8086, 0x27b9, pIIxget, pIIxset }, // Intel 82801GBM
  552. { 0x1106, 0x0586, viaget, viaset }, // Viatech 82C586
  553. { 0x1106, 0x0596, viaget, viaset }, // Viatech 82C596
  554. { 0x1106, 0x0686, viaget, viaset }, // Viatech 82C686
  555. { 0x1106, 0x3227, viaget, viaset }, // Viatech VT8237
  556. { 0x1045, 0xc700, optiget, optiset }, // Opti 82C700
  557. { 0x10b9, 0x1533, aliget, aliset }, // Al M1533
  558. { 0x1039, 0x0008, pIIxget, pIIxset }, // SI 503
  559. { 0x1039, 0x0496, pIIxget, pIIxset }, // SI 496
  560. { 0x1078, 0x0100, cyrixget, cyrixset }, // Cyrix 5530 Legacy
  561. { 0x1022, 0x746B, nil, nil }, // AMD 8111
  562. { 0x10DE, 0x00D1, nil, nil }, // NVIDIA nForce 3
  563. { 0x1166, 0x0200, nil, nil }, // ServerWorks ServerSet III LE
  564. { 0x1002, 0x4377, nil, nil }, // ATI Radeon Xpress 200M
  565. { 0x1002, 0x4372, nil, nil }, // ATI SB400
  566. };
  567. typedef struct Slot Slot;
  568. struct Slot {
  569. uchar bus; // Pci bus number
  570. uchar dev; // Pci device number
  571. uchar maps[12]; // Avoid structs! Link and mask.
  572. uchar slot; // Add-in/built-in slot
  573. uchar reserved;
  574. };
  575. typedef struct Router Router;
  576. struct Router {
  577. uchar signature[4]; // Routing table signature
  578. uchar version[2]; // Version number
  579. uchar size[2]; // Total table size
  580. uchar bus; // Interrupt router bus number
  581. uchar devfn; // Router's devfunc
  582. uchar pciirqs[2]; // Exclusive PCI irqs
  583. uchar compat[4]; // Compatible PCI interrupt router
  584. uchar miniport[4]; // Miniport data
  585. uchar reserved[11];
  586. uchar checksum;
  587. };
  588. static ushort pciirqs; // Exclusive PCI irqs
  589. static Bridge *southbridge; // Which southbridge to use.
  590. static void
  591. pcirouting(void)
  592. {
  593. Slot *e;
  594. Router *r;
  595. int size, i, fn, tbdf;
  596. Pcidev *sbpci, *pci;
  597. uchar *p, pin, irq, link, *map;
  598. // Search for PCI interrupt routing table in BIOS
  599. for(p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
  600. if(p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
  601. break;
  602. if(p >= (uchar *)KADDR(0xfffff))
  603. return;
  604. r = (Router *)p;
  605. // print("PCI interrupt routing table version %d.%d at %.6uX\n",
  606. // r->version[0], r->version[1], (ulong)r & 0xfffff);
  607. tbdf = (BusPCI << 24)|(r->bus << 16)|(r->devfn << 8);
  608. sbpci = pcimatchtbdf(tbdf);
  609. if(sbpci == nil) {
  610. print("pcirouting: Cannot find south bridge %T\n", tbdf);
  611. return;
  612. }
  613. for(i = 0; i != nelem(southbridges); i++)
  614. if(sbpci->vid == southbridges[i].vid && sbpci->did == southbridges[i].did)
  615. break;
  616. if(i == nelem(southbridges)) {
  617. print("pcirouting: ignoring south bridge %T %.4uX/%.4uX\n", tbdf, sbpci->vid, sbpci->did);
  618. return;
  619. }
  620. southbridge = &southbridges[i];
  621. if(southbridge->get == nil || southbridge->set == nil)
  622. return;
  623. pciirqs = (r->pciirqs[1] << 8)|r->pciirqs[0];
  624. size = (r->size[1] << 8)|r->size[0];
  625. for(e = (Slot *)&r[1]; (uchar *)e < p + size; e++) {
  626. // print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
  627. // for (i = 0; i != 4; i++) {
  628. // uchar *m = &e->maps[i * 3];
  629. // print("[%d] %.2uX %.4uX ",
  630. // i, m[0], (m[2] << 8)|m[1]);
  631. // }
  632. // print("\n");
  633. for(fn = 0; fn != 8; fn++) {
  634. tbdf = (BusPCI << 24)|(e->bus << 16)|((e->dev | fn) << 8);
  635. pci = pcimatchtbdf(tbdf);
  636. if(pci == nil)
  637. continue;
  638. pin = pcicfgr8(pci, PciINTP);
  639. if(pin == 0 || pin == 0xff)
  640. continue;
  641. map = &e->maps[(pin - 1) * 3];
  642. link = map[0];
  643. irq = southbridge->get(sbpci, link);
  644. if(irq == 0 || irq == pci->intl)
  645. continue;
  646. if(pci->intl != 0 && pci->intl != 0xFF) {
  647. print("pcirouting: BIOS workaround: %T at pin %d link %d irq %d -> %d\n",
  648. tbdf, pin, link, irq, pci->intl);
  649. southbridge->set(sbpci, link, pci->intl);
  650. continue;
  651. }
  652. print("pcirouting: %T at pin %d link %d irq %d\n", tbdf, pin, link, irq);
  653. pcicfgw8(pci, PciINTL, irq);
  654. pci->intl = irq;
  655. }
  656. }
  657. }
  658. static void pcireservemem(void);
  659. static int
  660. pcicfgrw8bios(int tbdf, int rno, int data, int read)
  661. {
  662. BIOS32ci ci;
  663. if(pcibiossi == nil)
  664. return -1;
  665. memset(&ci, 0, sizeof(BIOS32ci));
  666. ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
  667. ci.edi = rno;
  668. if(read){
  669. ci.eax = 0xB108;
  670. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  671. return ci.ecx & 0xFF;
  672. }
  673. else{
  674. ci.eax = 0xB10B;
  675. ci.ecx = data & 0xFF;
  676. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  677. return 0;
  678. }
  679. return -1;
  680. }
  681. static int
  682. pcicfgrw16bios(int tbdf, int rno, int data, int read)
  683. {
  684. BIOS32ci ci;
  685. if(pcibiossi == nil)
  686. return -1;
  687. memset(&ci, 0, sizeof(BIOS32ci));
  688. ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
  689. ci.edi = rno;
  690. if(read){
  691. ci.eax = 0xB109;
  692. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  693. return ci.ecx & 0xFFFF;
  694. }
  695. else{
  696. ci.eax = 0xB10C;
  697. ci.ecx = data & 0xFFFF;
  698. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  699. return 0;
  700. }
  701. return -1;
  702. }
  703. static int
  704. pcicfgrw32bios(int tbdf, int rno, int data, int read)
  705. {
  706. BIOS32ci ci;
  707. if(pcibiossi == nil)
  708. return -1;
  709. memset(&ci, 0, sizeof(BIOS32ci));
  710. ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
  711. ci.edi = rno;
  712. if(read){
  713. ci.eax = 0xB10A;
  714. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  715. return ci.ecx;
  716. }
  717. else{
  718. ci.eax = 0xB10D;
  719. ci.ecx = data;
  720. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  721. return 0;
  722. }
  723. return -1;
  724. }
  725. static BIOS32si*
  726. pcibiosinit(void)
  727. {
  728. BIOS32ci ci;
  729. BIOS32si *si;
  730. if((si = bios32open("$PCI")) == nil)
  731. return nil;
  732. memset(&ci, 0, sizeof(BIOS32ci));
  733. ci.eax = 0xB101;
  734. if(bios32ci(si, &ci) || ci.edx != ((' '<<24)|('I'<<16)|('C'<<8)|'P')){
  735. free(si);
  736. return nil;
  737. }
  738. if(ci.eax & 0x01)
  739. pcimaxdno = 31;
  740. else
  741. pcimaxdno = 15;
  742. pcimaxbno = ci.ecx & 0xff;
  743. return si;
  744. }
  745. void
  746. pcibussize(Pcidev *root, ulong *msize, ulong *iosize)
  747. {
  748. *msize = 0;
  749. *iosize = 0;
  750. pcibusmap(root, msize, iosize, 0);
  751. }
  752. static void
  753. pcicfginit(void)
  754. {
  755. char *p;
  756. Pcidev **list;
  757. ulong mema, ioa;
  758. int bno, n, pcibios;
  759. lock(&pcicfginitlock);
  760. if(pcicfgmode != -1)
  761. goto out;
  762. pcibios = 0;
  763. if(getconf("*nobios"))
  764. nobios = 1;
  765. else if(getconf("*pcibios"))
  766. pcibios = 1;
  767. if(getconf("*nopcirouting"))
  768. nopcirouting = 1;
  769. /*
  770. * Try to determine which PCI configuration mode is implemented.
  771. * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
  772. * a DWORD at 0xCF8 and another at 0xCFC and will pass through
  773. * any non-DWORD accesses as normal I/O cycles. There shouldn't be
  774. * a device behind these addresses so if Mode1 accesses fail try
  775. * for Mode2 (Mode2 is deprecated).
  776. */
  777. if(!pcibios){
  778. /*
  779. * Bits [30:24] of PciADDR must be 0,
  780. * according to the spec.
  781. */
  782. n = inl(PciADDR);
  783. if(!(n & 0x7FF00000)){
  784. outl(PciADDR, 0x80000000);
  785. outb(PciADDR+3, 0);
  786. if(inl(PciADDR) & 0x80000000){
  787. pcicfgmode = 1;
  788. pcimaxdno = 31;
  789. }
  790. }
  791. outl(PciADDR, n);
  792. if(pcicfgmode < 0){
  793. /*
  794. * The 'key' part of PciCSE should be 0.
  795. */
  796. n = inb(PciCSE);
  797. if(!(n & 0xF0)){
  798. outb(PciCSE, 0x0E);
  799. if(inb(PciCSE) == 0x0E){
  800. pcicfgmode = 2;
  801. pcimaxdno = 15;
  802. }
  803. }
  804. outb(PciCSE, n);
  805. }
  806. }
  807. if(pcicfgmode < 0 || pcibios) {
  808. if((pcibiossi = pcibiosinit()) == nil)
  809. goto out;
  810. pcicfgrw8 = pcicfgrw8bios;
  811. pcicfgrw16 = pcicfgrw16bios;
  812. pcicfgrw32 = pcicfgrw32bios;
  813. pcicfgmode = 3;
  814. }
  815. fmtinstall('T', tbdffmt);
  816. if(p = getconf("*pcimaxbno")){
  817. n = strtoul(p, 0, 0);
  818. if(n < pcimaxbno)
  819. pcimaxbno = n;
  820. }
  821. if(p = getconf("*pcimaxdno")){
  822. n = strtoul(p, 0, 0);
  823. if(n < pcimaxdno)
  824. pcimaxdno = n;
  825. }
  826. list = &pciroot;
  827. for(bno = 0; bno <= pcimaxbno; bno++) {
  828. int sbno = bno;
  829. bno = pcilscan(bno, list);
  830. while(*list)
  831. list = &(*list)->link;
  832. if (sbno == 0) {
  833. Pcidev *pci;
  834. /*
  835. * If we have found a PCI-to-Cardbus bridge, make sure
  836. * it has no valid mappings anymore.
  837. */
  838. for(pci = pciroot; pci != nil; pci = pci->link){
  839. if (pci->ccrb == 6 && pci->ccru == 7) {
  840. ushort bcr;
  841. /* reset the cardbus */
  842. bcr = pcicfgr16(pci, PciBCR);
  843. pcicfgw16(pci, PciBCR, 0x40 | bcr);
  844. delay(50);
  845. }
  846. }
  847. }
  848. }
  849. if(pciroot == nil)
  850. goto out;
  851. if(nobios) {
  852. /*
  853. * Work out how big the top bus is
  854. */
  855. pcibussize(pciroot, &mema, &ioa);
  856. /*
  857. * Align the windows and map it
  858. */
  859. ioa = 0x1000;
  860. mema = 0x90000000;
  861. pcilog("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
  862. pcibusmap(pciroot, &mema, &ioa, 1);
  863. DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
  864. unlock(&pcicfginitlock);
  865. return;
  866. }
  867. if (!nopcirouting)
  868. pcirouting();
  869. out:
  870. pcireservemem();
  871. unlock(&pcicfginitlock);
  872. if(getconf("*pcihinv"))
  873. pcihinv(nil);
  874. }
  875. static void
  876. pcireservemem(void)
  877. {
  878. int i;
  879. Pcidev *p;
  880. /*
  881. * mark all the physical address space claimed by pci devices
  882. * as in use, so that upaalloc doesn't give it out.
  883. */
  884. for(p=pciroot; p; p=p->list)
  885. for(i=0; i<nelem(p->mem); i++)
  886. if(p->mem[i].bar && (p->mem[i].bar&1) == 0)
  887. upareserve(p->mem[i].bar&~0x0F, p->mem[i].size);
  888. }
  889. static int
  890. pcicfgrw8raw(int tbdf, int rno, int data, int read)
  891. {
  892. int o, type, x;
  893. if(pcicfgmode == -1)
  894. pcicfginit();
  895. if(BUSBNO(tbdf))
  896. type = 0x01;
  897. else
  898. type = 0x00;
  899. x = -1;
  900. if(BUSDNO(tbdf) > pcimaxdno)
  901. return x;
  902. lock(&pcicfglock);
  903. switch(pcicfgmode){
  904. case 1:
  905. o = rno & 0x03;
  906. rno &= ~0x03;
  907. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  908. if(read)
  909. x = inb(PciDATA+o);
  910. else
  911. outb(PciDATA+o, data);
  912. outl(PciADDR, 0);
  913. break;
  914. case 2:
  915. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  916. outb(PciFORWARD, BUSBNO(tbdf));
  917. if(read)
  918. x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  919. else
  920. outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  921. outb(PciCSE, 0);
  922. break;
  923. }
  924. unlock(&pcicfglock);
  925. return x;
  926. }
  927. int
  928. pcicfgr8(Pcidev* pcidev, int rno)
  929. {
  930. return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
  931. }
  932. void
  933. pcicfgw8(Pcidev* pcidev, int rno, int data)
  934. {
  935. pcicfgrw8(pcidev->tbdf, rno, data, 0);
  936. }
  937. static int
  938. pcicfgrw16raw(int tbdf, int rno, int data, int read)
  939. {
  940. int o, type, x;
  941. if(pcicfgmode == -1)
  942. pcicfginit();
  943. if(BUSBNO(tbdf))
  944. type = 0x01;
  945. else
  946. type = 0x00;
  947. x = -1;
  948. if(BUSDNO(tbdf) > pcimaxdno)
  949. return x;
  950. lock(&pcicfglock);
  951. switch(pcicfgmode){
  952. case 1:
  953. o = rno & 0x02;
  954. rno &= ~0x03;
  955. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  956. if(read)
  957. x = ins(PciDATA+o);
  958. else
  959. outs(PciDATA+o, data);
  960. outl(PciADDR, 0);
  961. break;
  962. case 2:
  963. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  964. outb(PciFORWARD, BUSBNO(tbdf));
  965. if(read)
  966. x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  967. else
  968. outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  969. outb(PciCSE, 0);
  970. break;
  971. }
  972. unlock(&pcicfglock);
  973. return x;
  974. }
  975. int
  976. pcicfgr16(Pcidev* pcidev, int rno)
  977. {
  978. return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
  979. }
  980. void
  981. pcicfgw16(Pcidev* pcidev, int rno, int data)
  982. {
  983. pcicfgrw16(pcidev->tbdf, rno, data, 0);
  984. }
  985. static int
  986. pcicfgrw32raw(int tbdf, int rno, int data, int read)
  987. {
  988. int type, x;
  989. if(pcicfgmode == -1)
  990. pcicfginit();
  991. if(BUSBNO(tbdf))
  992. type = 0x01;
  993. else
  994. type = 0x00;
  995. x = -1;
  996. if(BUSDNO(tbdf) > pcimaxdno)
  997. return x;
  998. lock(&pcicfglock);
  999. switch(pcicfgmode){
  1000. case 1:
  1001. rno &= ~0x03;
  1002. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  1003. if(read)
  1004. x = inl(PciDATA);
  1005. else
  1006. outl(PciDATA, data);
  1007. outl(PciADDR, 0);
  1008. break;
  1009. case 2:
  1010. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  1011. outb(PciFORWARD, BUSBNO(tbdf));
  1012. if(read)
  1013. x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  1014. else
  1015. outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  1016. outb(PciCSE, 0);
  1017. break;
  1018. }
  1019. unlock(&pcicfglock);
  1020. return x;
  1021. }
  1022. int
  1023. pcicfgr32(Pcidev* pcidev, int rno)
  1024. {
  1025. return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
  1026. }
  1027. void
  1028. pcicfgw32(Pcidev* pcidev, int rno, int data)
  1029. {
  1030. pcicfgrw32(pcidev->tbdf, rno, data, 0);
  1031. }
  1032. Pcidev*
  1033. pcimatch(Pcidev* prev, int vid, int did)
  1034. {
  1035. if(pcicfgmode == -1)
  1036. pcicfginit();
  1037. if(prev == nil)
  1038. prev = pcilist;
  1039. else
  1040. prev = prev->list;
  1041. while(prev != nil){
  1042. if((vid == 0 || prev->vid == vid)
  1043. && (did == 0 || prev->did == did))
  1044. break;
  1045. prev = prev->list;
  1046. }
  1047. return prev;
  1048. }
  1049. Pcidev*
  1050. pcimatchtbdf(int tbdf)
  1051. {
  1052. Pcidev *pcidev;
  1053. if(pcicfgmode == -1)
  1054. pcicfginit();
  1055. for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
  1056. if(pcidev->tbdf == tbdf)
  1057. break;
  1058. }
  1059. return pcidev;
  1060. }
  1061. uchar
  1062. pciipin(Pcidev *pci, uchar pin)
  1063. {
  1064. if (pci == nil)
  1065. pci = pcilist;
  1066. while (pci) {
  1067. uchar intl;
  1068. if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
  1069. return pci->intl;
  1070. if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
  1071. return intl;
  1072. pci = pci->list;
  1073. }
  1074. return 0;
  1075. }
  1076. static void
  1077. pcilhinv(Pcidev* p)
  1078. {
  1079. int i;
  1080. Pcidev *t;
  1081. if(p == nil) {
  1082. putstrn(PCICONS.output, PCICONS.ptr);
  1083. p = pciroot;
  1084. print("bus dev type vid did intl memory\n");
  1085. }
  1086. for(t = p; t != nil; t = t->link) {
  1087. print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
  1088. BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
  1089. t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
  1090. for(i = 0; i < nelem(p->mem); i++) {
  1091. if(t->mem[i].size == 0)
  1092. continue;
  1093. print("%d:%.8lux %d ", i,
  1094. t->mem[i].bar, t->mem[i].size);
  1095. }
  1096. if(t->ioa.bar || t->ioa.size)
  1097. print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size);
  1098. if(t->mema.bar || t->mema.size)
  1099. print("mema:%.8lux %d ", t->mema.bar, t->mema.size);
  1100. if(t->bridge)
  1101. print("->%d", BUSBNO(t->bridge->tbdf));
  1102. print("\n");
  1103. }
  1104. while(p != nil) {
  1105. if(p->bridge != nil)
  1106. pcilhinv(p->bridge);
  1107. p = p->link;
  1108. }
  1109. }
  1110. void
  1111. pcihinv(Pcidev* p)
  1112. {
  1113. if(pcicfgmode == -1)
  1114. pcicfginit();
  1115. lock(&pcicfginitlock);
  1116. pcilhinv(p);
  1117. unlock(&pcicfginitlock);
  1118. }
  1119. void
  1120. pcireset(void)
  1121. {
  1122. Pcidev *p;
  1123. if(pcicfgmode == -1)
  1124. pcicfginit();
  1125. for(p = pcilist; p != nil; p = p->list) {
  1126. /* don't mess with the bridges */
  1127. if(p->ccrb == 0x06)
  1128. continue;
  1129. pciclrbme(p);
  1130. }
  1131. }
  1132. void
  1133. pcisetioe(Pcidev* p)
  1134. {
  1135. p->pcr |= IOen;
  1136. pcicfgw16(p, PciPCR, p->pcr);
  1137. }
  1138. void
  1139. pciclrioe(Pcidev* p)
  1140. {
  1141. p->pcr &= ~IOen;
  1142. pcicfgw16(p, PciPCR, p->pcr);
  1143. }
  1144. void
  1145. pcisetbme(Pcidev* p)
  1146. {
  1147. p->pcr |= MASen;
  1148. pcicfgw16(p, PciPCR, p->pcr);
  1149. }
  1150. void
  1151. pciclrbme(Pcidev* p)
  1152. {
  1153. p->pcr &= ~MASen;
  1154. pcicfgw16(p, PciPCR, p->pcr);
  1155. }
  1156. void
  1157. pcisetmwi(Pcidev* p)
  1158. {
  1159. p->pcr |= MemWrInv;
  1160. pcicfgw16(p, PciPCR, p->pcr);
  1161. }
  1162. void
  1163. pciclrmwi(Pcidev* p)
  1164. {
  1165. p->pcr &= ~MemWrInv;
  1166. pcicfgw16(p, PciPCR, p->pcr);
  1167. }
  1168. static int
  1169. pcigetpmrb(Pcidev* p)
  1170. {
  1171. int ptr;
  1172. if(p->pmrb != 0)
  1173. return p->pmrb;
  1174. p->pmrb = -1;
  1175. /*
  1176. * If there are no extended capabilities implemented,
  1177. * (bit 4 in the status register) assume there's no standard
  1178. * power management method.
  1179. * Find the capabilities pointer based on PCI header type.
  1180. */
  1181. if(!(pcicfgr16(p, PciPSR) & 0x0010))
  1182. return -1;
  1183. switch(pcicfgr8(p, PciHDT)){
  1184. default:
  1185. return -1;
  1186. case 0: /* all other */
  1187. case 1: /* PCI to PCI bridge */
  1188. ptr = 0x34;
  1189. break;
  1190. case 2: /* CardBus bridge */
  1191. ptr = 0x14;
  1192. break;
  1193. }
  1194. ptr = pcicfgr32(p, ptr);
  1195. while(ptr != 0){
  1196. /*
  1197. * Check for validity.
  1198. * Can't be in standard header and must be double
  1199. * word aligned.
  1200. */
  1201. if(ptr < 0x40 || (ptr & ~0xFC))
  1202. return -1;
  1203. if(pcicfgr8(p, ptr) == 0x01){
  1204. p->pmrb = ptr;
  1205. return ptr;
  1206. }
  1207. ptr = pcicfgr8(p, ptr+1);
  1208. }
  1209. return -1;
  1210. }
  1211. int
  1212. pcigetpms(Pcidev* p)
  1213. {
  1214. int pmcsr, ptr;
  1215. if((ptr = pcigetpmrb(p)) == -1)
  1216. return -1;
  1217. /*
  1218. * Power Management Register Block:
  1219. * offset 0: Capability ID
  1220. * 1: next item pointer
  1221. * 2: capabilities
  1222. * 4: control/status
  1223. * 6: bridge support extensions
  1224. * 7: data
  1225. */
  1226. pmcsr = pcicfgr16(p, ptr+4);
  1227. return pmcsr & 0x0003;
  1228. }
  1229. int
  1230. pcisetpms(Pcidev* p, int state)
  1231. {
  1232. int ostate, pmc, pmcsr, ptr;
  1233. if((ptr = pcigetpmrb(p)) == -1)
  1234. return -1;
  1235. pmc = pcicfgr16(p, ptr+2);
  1236. pmcsr = pcicfgr16(p, ptr+4);
  1237. ostate = pmcsr & 0x0003;
  1238. pmcsr &= ~0x0003;
  1239. switch(state){
  1240. default:
  1241. return -1;
  1242. case 0:
  1243. break;
  1244. case 1:
  1245. if(!(pmc & 0x0200))
  1246. return -1;
  1247. break;
  1248. case 2:
  1249. if(!(pmc & 0x0400))
  1250. return -1;
  1251. break;
  1252. case 3:
  1253. break;
  1254. }
  1255. pmcsr |= state;
  1256. pcicfgw16(p, ptr+4, pmcsr);
  1257. return ostate;
  1258. }