sd53c8xx.c 54 KB

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  1. /*
  2. * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
  3. * Nigel Roles (nigel@9fs.org)
  4. *
  5. * 27/5/02 Fixed problems with transfers >= 256 * 512
  6. *
  7. * 13/3/01 Fixed microcode to support targets > 7
  8. *
  9. * 01/12/00 Removed previous comments. Fixed a small problem in
  10. * mismatch recovery for targets with synchronous offsets of >=16
  11. * connected to >=875s. Thanks, Jean.
  12. *
  13. * Known problems
  14. *
  15. * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
  16. */
  17. #define MAXTARGET 16 /* can be 8 or 16 */
  18. #include "u.h"
  19. #include "../port/lib.h"
  20. #include "mem.h"
  21. #include "dat.h"
  22. #include "fns.h"
  23. #include "io.h"
  24. #include "../port/sd.h"
  25. extern SDifc sd53c8xxifc;
  26. /**********************************/
  27. /* Portable configuration macros */
  28. /**********************************/
  29. //#define BOOTDEBUG
  30. //#define ASYNC_ONLY
  31. //#define INTERNAL_SCLK
  32. //#define ALWAYS_DO_WDTR
  33. #define WMR_DEBUG
  34. /**********************************/
  35. /* CPU specific macros */
  36. /**********************************/
  37. #define PRINTPREFIX "sd53c8xx: "
  38. #ifdef BOOTDEBUG
  39. #define KPRINT oprint
  40. #define IPRINT intrprint
  41. #define DEBUG(n) 1
  42. #define IFLUSH() iflush()
  43. #else
  44. static int idebug = 1;
  45. #define KPRINT if(0) iprint
  46. #define IPRINT if(idebug) iprint
  47. #define DEBUG(n) (0)
  48. #define IFLUSH()
  49. #endif /* BOOTDEBUG */
  50. /*******************************/
  51. /* General */
  52. /*******************************/
  53. #ifndef DMASEG
  54. #define DMASEG(x) PCIWADDR(x)
  55. #define legetl(x) (*(ulong*)(x))
  56. #define lesetl(x,v) (*(ulong*)(x) = (v))
  57. #define swabl(a,b,c)
  58. #else
  59. #endif /*DMASEG */
  60. #define DMASEG_TO_KADDR(x) KADDR((x)-PCIWINDOW)
  61. #define KPTR(x) ((x) == 0 ? 0 : DMASEG_TO_KADDR(x))
  62. #define MEGA 1000000L
  63. #ifdef INTERNAL_SCLK
  64. #define SCLK (33 * MEGA)
  65. #else
  66. #define SCLK (40 * MEGA)
  67. #endif /* INTERNAL_SCLK */
  68. #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
  69. #define MAXSYNCSCSIRATE (5 * MEGA)
  70. #define MAXFASTSYNCSCSIRATE (10 * MEGA)
  71. #define MAXULTRASYNCSCSIRATE (20 * MEGA)
  72. #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
  73. #define MAXASYNCCORERATE (25 * MEGA)
  74. #define MAXSYNCCORERATE (25 * MEGA)
  75. #define MAXFASTSYNCCORERATE (50 * MEGA)
  76. #define MAXULTRASYNCCORERATE (80 * MEGA)
  77. #define MAXULTRA2SYNCCORERATE (160 * MEGA)
  78. #define X_MSG 1
  79. #define X_MSG_SDTR 1
  80. #define X_MSG_WDTR 3
  81. struct na_patch {
  82. unsigned lwoff;
  83. unsigned char type;
  84. };
  85. typedef struct Ncr {
  86. uchar scntl0; /* 00 */
  87. uchar scntl1;
  88. uchar scntl2;
  89. uchar scntl3;
  90. uchar scid; /* 04 */
  91. uchar sxfer;
  92. uchar sdid;
  93. uchar gpreg;
  94. uchar sfbr; /* 08 */
  95. uchar socl;
  96. uchar ssid;
  97. uchar sbcl;
  98. uchar dstat; /* 0c */
  99. uchar sstat0;
  100. uchar sstat1;
  101. uchar sstat2;
  102. uchar dsa[4]; /* 10 */
  103. uchar istat; /* 14 */
  104. uchar istatpad[3];
  105. uchar ctest0; /* 18 */
  106. uchar ctest1;
  107. uchar ctest2;
  108. uchar ctest3;
  109. uchar temp[4]; /* 1c */
  110. uchar dfifo; /* 20 */
  111. uchar ctest4;
  112. uchar ctest5;
  113. uchar ctest6;
  114. uchar dbc[3]; /* 24 */
  115. uchar dcmd; /* 27 */
  116. uchar dnad[4]; /* 28 */
  117. uchar dsp[4]; /* 2c */
  118. uchar dsps[4]; /* 30 */
  119. uchar scratcha[4]; /* 34 */
  120. uchar dmode; /* 38 */
  121. uchar dien;
  122. uchar dwt;
  123. uchar dcntl;
  124. uchar adder[4]; /* 3c */
  125. uchar sien0; /* 40 */
  126. uchar sien1;
  127. uchar sist0;
  128. uchar sist1;
  129. uchar slpar; /* 44 */
  130. uchar slparpad0;
  131. uchar macntl;
  132. uchar gpcntl;
  133. uchar stime0; /* 48 */
  134. uchar stime1;
  135. uchar respid;
  136. uchar respidpad0;
  137. uchar stest0; /* 4c */
  138. uchar stest1;
  139. uchar stest2;
  140. uchar stest3;
  141. uchar sidl; /* 50 */
  142. uchar sidlpad[3];
  143. uchar sodl; /* 54 */
  144. uchar sodlpad[3];
  145. uchar sbdl; /* 58 */
  146. uchar sbdlpad[3];
  147. uchar scratchb[4]; /* 5c */
  148. } Ncr;
  149. typedef struct Movedata {
  150. uchar dbc[4];
  151. uchar pa[4];
  152. } Movedata;
  153. typedef enum NegoState {
  154. NeitherDone, WideInit, WideResponse, WideDone,
  155. SyncInit, SyncResponse, BothDone
  156. } NegoState;
  157. typedef enum State {
  158. Allocated, Queued, Active, Done
  159. } State;
  160. typedef struct Dsa {
  161. uchar stateb;
  162. uchar result;
  163. uchar dmablks;
  164. uchar flag; /* setbyte(state,3,...) */
  165. union {
  166. ulong dmancr; /* For block transfer: NCR order (little-endian) */
  167. uchar dmaaddr[4];
  168. };
  169. uchar target; /* Target */
  170. uchar pad0[3];
  171. uchar lun; /* Logical Unit Number */
  172. uchar pad1[3];
  173. uchar scntl3;
  174. uchar sxfer;
  175. uchar pad2[2];
  176. uchar next[4]; /* chaining for SCRIPT (NCR byte order) */
  177. struct Dsa *freechain; /* chaining for freelist */
  178. Rendez;
  179. uchar scsi_id_buf[4];
  180. Movedata msg_out_buf;
  181. Movedata cmd_buf;
  182. Movedata data_buf;
  183. Movedata status_buf;
  184. uchar msg_out[10]; /* enough to include SDTR */
  185. uchar status;
  186. int p9status;
  187. uchar parityerror;
  188. } Dsa;
  189. typedef enum Feature {
  190. BigFifo = 1, /* 536 byte fifo */
  191. BurstOpCodeFetch = 2, /* burst fetch opcodes */
  192. Prefetch = 4, /* prefetch 8 longwords */
  193. LocalRAM = 8, /* 4K longwords of local RAM */
  194. Differential = 16, /* Differential support */
  195. Wide = 32, /* Wide capable */
  196. Ultra = 64, /* Ultra capable */
  197. ClockDouble = 128, /* Has clock doubler */
  198. ClockQuad = 256, /* Has clock quadrupler (same as Ultra2) */
  199. Ultra2 = 256,
  200. } Feature;
  201. typedef enum Burst {
  202. Burst2 = 0,
  203. Burst4 = 1,
  204. Burst8 = 2,
  205. Burst16 = 3,
  206. Burst32 = 4,
  207. Burst64 = 5,
  208. Burst128 = 6
  209. } Burst;
  210. typedef struct Variant {
  211. ushort did;
  212. uchar maxrid; /* maximum allowed revision ID */
  213. char *name;
  214. Burst burst; /* codings for max burst */
  215. uchar maxsyncoff; /* max synchronous offset */
  216. uchar registers; /* number of 32 bit registers */
  217. unsigned feature;
  218. } Variant;
  219. static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
  220. #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
  221. #define NULTRASCF (NULTRA2SCF - 2)
  222. #define NSCF (NULTRASCF - 1)
  223. typedef struct Controller {
  224. Lock;
  225. struct {
  226. uchar scntl3;
  227. uchar stest2;
  228. } bios;
  229. uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
  230. NegoState s[MAXTARGET];
  231. uchar scntl3[MAXTARGET];
  232. uchar sxfer[MAXTARGET];
  233. uchar cap[MAXTARGET]; /* capabilities byte from Identify */
  234. ushort capvalid; /* bit per target for validity of cap[] */
  235. ushort wide; /* bit per target set if wide negotiated */
  236. ulong sclk; /* clock speed of controller */
  237. uchar clockmult; /* set by synctabinit */
  238. uchar ccf; /* CCF bits */
  239. uchar tpf; /* best tpf value for this controller */
  240. uchar feature; /* requested features */
  241. int running; /* is the script processor running? */
  242. int ssm; /* single step mode */
  243. Ncr *n; /* pointer to registers */
  244. Variant *v; /* pointer to variant type */
  245. ulong *script; /* where the real script is */
  246. ulong scriptpa; /* where the real script is */
  247. Pcidev* pcidev;
  248. SDev* sdev;
  249. struct {
  250. Lock;
  251. uchar head[4]; /* head of free list (NCR byte order) */
  252. Dsa *freechain;
  253. } dsalist;
  254. QLock q[MAXTARGET]; /* queues for each target */
  255. } Controller;
  256. #define SYNCOFFMASK(c) (((c)->v->maxsyncoff * 2) - 1)
  257. #define SSIDMASK(c) (((c)->v->feature & Wide) ? 15 : 7)
  258. /* ISTAT */
  259. enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
  260. /* DSTAT */
  261. enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
  262. /* SSTAT */
  263. enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
  264. static void setmovedata(Movedata*, ulong, ulong);
  265. static void advancedata(Movedata*, long);
  266. static int bios_set_differential(Controller *c);
  267. static char *phase[] = {
  268. "data out", "data in", "command", "status",
  269. "reserved out", "reserved in", "message out", "message in"
  270. };
  271. #ifdef BOOTDEBUG
  272. #define DEBUGSIZE 10240
  273. char debugbuf[DEBUGSIZE];
  274. char *debuglast;
  275. static void
  276. intrprint(char *format, ...)
  277. {
  278. if (debuglast == 0)
  279. debuglast = debugbuf;
  280. debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  281. }
  282. static void
  283. iflush()
  284. {
  285. int s;
  286. char *endp;
  287. s = splhi();
  288. if (debuglast == 0)
  289. debuglast = debugbuf;
  290. if (debuglast == debugbuf) {
  291. splx(s);
  292. return;
  293. }
  294. endp = debuglast;
  295. splx(s);
  296. screenputs(debugbuf, endp - debugbuf);
  297. s = splhi();
  298. memmove(debugbuf, endp, debuglast - endp);
  299. debuglast -= endp - debugbuf;
  300. splx(s);
  301. }
  302. static void
  303. oprint(char *format, ...)
  304. {
  305. int s;
  306. iflush();
  307. s = splhi();
  308. if (debuglast == 0)
  309. debuglast = debugbuf;
  310. debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  311. splx(s);
  312. iflush();
  313. }
  314. #endif
  315. #include "sd53c8xx.i"
  316. /*
  317. * We used to use a linked list of Dsas with nil as the terminator,
  318. * but occasionally the 896 card seems not to notice that the 0
  319. * is really a 0, and then it tries to reference the Dsa at address 0.
  320. * To address this, we use a sentinel dsa that links back to itself
  321. * and has state A_STATE_END. If the card takes an iteration or
  322. * two to notice that the state says A_STATE_END, that's no big
  323. * deal. Clearly this isn't the right approach, but I'm just
  324. * stumped. Even with this, we occasionally get prints about
  325. * "WSR set", usually with about the same frequency that the
  326. * card used to walk past 0.
  327. */
  328. static Dsa *dsaend;
  329. static Dsa*
  330. dsaallocnew(Controller *c)
  331. {
  332. Dsa *d;
  333. /* c->dsalist must be ilocked */
  334. d = xalloc(sizeof *d);
  335. if (d == nil)
  336. panic("sd53c8xx dsaallocnew: no memory");
  337. lesetl(d->next, legetl(c->dsalist.head));
  338. lesetl(&d->stateb, A_STATE_FREE);
  339. coherence();
  340. lesetl(c->dsalist.head, DMASEG(d));
  341. coherence();
  342. return d;
  343. }
  344. static Dsa *
  345. dsaalloc(Controller *c, int target, int lun)
  346. {
  347. Dsa *d;
  348. ilock(&c->dsalist);
  349. if ((d = c->dsalist.freechain) != 0) {
  350. if (DEBUG(1))
  351. IPRINT(PRINTPREFIX "%d/%d: reused dsa %lux\n", target, lun, (ulong)d);
  352. } else {
  353. d = dsaallocnew(c);
  354. if (DEBUG(1))
  355. IPRINT(PRINTPREFIX "%d/%d: allocated dsa %lux\n", target, lun, (ulong)d);
  356. }
  357. c->dsalist.freechain = d->freechain;
  358. lesetl(&d->stateb, A_STATE_ALLOCATED);
  359. iunlock(&c->dsalist);
  360. d->target = target;
  361. d->lun = lun;
  362. return d;
  363. }
  364. static void
  365. dsafree(Controller *c, Dsa *d)
  366. {
  367. ilock(&c->dsalist);
  368. d->freechain = c->dsalist.freechain;
  369. c->dsalist.freechain = d;
  370. lesetl(&d->stateb, A_STATE_FREE);
  371. iunlock(&c->dsalist);
  372. }
  373. static void
  374. dsadump(Controller *c)
  375. {
  376. Dsa *d;
  377. u32int *a;
  378. iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
  379. for(d=KPTR(legetl(c->dsalist.head)); d != dsaend; d=KPTR(legetl(d->next))){
  380. if(d == (void*)-1){
  381. iprint("\t dsa %p\n", d);
  382. break;
  383. }
  384. a = (u32int*)d;
  385. iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
  386. }
  387. /*
  388. a = KPTR(c->scriptpa+E_dsa_addr);
  389. iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  390. a[0], a[1], a[2], a[3], a[4]);
  391. a = KPTR(c->scriptpa+E_issue_addr);
  392. iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  393. a[0], a[1], a[2], a[3], a[4]);
  394. a = KPTR(c->scriptpa+E_issue_test_begin);
  395. e = KPTR(c->scriptpa+E_issue_test_end);
  396. iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
  397. i = 0;
  398. for(; a<e; a++){
  399. iprint(" %.8ux", *a);
  400. if(++i%8 == 0)
  401. iprint("\n");
  402. }
  403. if(i%8)
  404. iprint("\n");
  405. */
  406. }
  407. static Dsa *
  408. dsafind(Controller *c, uchar target, uchar lun, uchar state)
  409. {
  410. Dsa *d;
  411. for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  412. if (d->target != 0xff && d->target != target)
  413. continue;
  414. if (lun != 0xff && d->lun != lun)
  415. continue;
  416. if (state != 0xff && d->stateb != state)
  417. continue;
  418. break;
  419. }
  420. return d;
  421. }
  422. static void
  423. dumpncrregs(Controller *c, int intr)
  424. {
  425. int i;
  426. Ncr *n = c->n;
  427. int depth = c->v->registers / 4;
  428. if (intr) {
  429. IPRINT("sa = %.8lux\n", c->scriptpa);
  430. }
  431. else {
  432. KPRINT("sa = %.8lux\n", c->scriptpa);
  433. }
  434. for (i = 0; i < depth; i++) {
  435. int j;
  436. for (j = 0; j < 4; j++) {
  437. int k = j * depth + i;
  438. uchar *p;
  439. /* display little-endian to make 32-bit values readable */
  440. p = (uchar*)n+k*4;
  441. if (intr) {
  442. IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  443. }
  444. else {
  445. KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  446. }
  447. USED(p);
  448. }
  449. if (intr) {
  450. IPRINT("\n");
  451. }
  452. else {
  453. KPRINT("\n");
  454. }
  455. }
  456. }
  457. static int
  458. chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
  459. {
  460. /* find lowest entry >= tpf */
  461. int besttpf = 1000;
  462. int bestscfi = 0;
  463. int bestxferp = 0;
  464. int scf, xferp;
  465. int maxscf;
  466. if (c->v->feature & Ultra2)
  467. maxscf = NULTRA2SCF;
  468. else if (c->v->feature & Ultra)
  469. maxscf = NULTRASCF;
  470. else
  471. maxscf = NSCF;
  472. /*
  473. * search large clock factors first since this should
  474. * result in more reliable transfers
  475. */
  476. for (scf = maxscf; scf >= 1; scf--) {
  477. for (xferp = 0; xferp < 8; xferp++) {
  478. unsigned char v = c->synctab[scf - 1][xferp];
  479. if (v == 0)
  480. continue;
  481. if (v >= tpf && v < besttpf) {
  482. besttpf = v;
  483. bestscfi = scf;
  484. bestxferp = xferp;
  485. }
  486. }
  487. }
  488. if (besttpf == 1000)
  489. return 0;
  490. if (scfp)
  491. *scfp = bestscfi;
  492. if (xferpp)
  493. *xferpp = bestxferp;
  494. return besttpf;
  495. }
  496. static void
  497. synctabinit(Controller *c)
  498. {
  499. int scf;
  500. unsigned long scsilimit;
  501. int xferp;
  502. unsigned long cr, sr;
  503. int tpf;
  504. int fast;
  505. int maxscf;
  506. if (c->v->feature & Ultra2)
  507. maxscf = NULTRA2SCF;
  508. else if (c->v->feature & Ultra)
  509. maxscf = NULTRASCF;
  510. else
  511. maxscf = NSCF;
  512. /*
  513. * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
  514. * first spin of the 875), assume 80MHz
  515. * otherwise use the internal (33 Mhz) or external (40MHz) default
  516. */
  517. if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
  518. c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
  519. else
  520. c->sclk = SCLK;
  521. /*
  522. * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
  523. * invoke the doubler
  524. */
  525. if (SCLK <= 40000000) {
  526. if (c->v->feature & ClockDouble) {
  527. c->sclk *= 2;
  528. c->clockmult = 1;
  529. }
  530. else if (c->v->feature & ClockQuad) {
  531. c->sclk *= 4;
  532. c->clockmult = 1;
  533. }
  534. else
  535. c->clockmult = 0;
  536. }
  537. else
  538. c->clockmult = 0;
  539. /* derive CCF from sclk */
  540. /* woebetide anyone with SCLK < 16.7 or > 80MHz */
  541. if (c->sclk <= 25 * MEGA)
  542. c->ccf = 1;
  543. else if (c->sclk <= 3750000)
  544. c->ccf = 2;
  545. else if (c->sclk <= 50 * MEGA)
  546. c->ccf = 3;
  547. else if (c->sclk <= 75 * MEGA)
  548. c->ccf = 4;
  549. else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
  550. c->ccf = 5;
  551. else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
  552. c->ccf = 6;
  553. else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
  554. c->ccf = 7;
  555. for (scf = 1; scf < maxscf; scf++) {
  556. /* check for legal core rate */
  557. /* round up so we run slower for safety */
  558. cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
  559. if (cr <= MAXSYNCCORERATE) {
  560. scsilimit = MAXSYNCSCSIRATE;
  561. fast = 0;
  562. }
  563. else if (cr <= MAXFASTSYNCCORERATE) {
  564. scsilimit = MAXFASTSYNCSCSIRATE;
  565. fast = 1;
  566. }
  567. else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
  568. scsilimit = MAXULTRASYNCSCSIRATE;
  569. fast = 2;
  570. }
  571. else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
  572. scsilimit = MAXULTRA2SYNCSCSIRATE;
  573. fast = 3;
  574. }
  575. else
  576. continue;
  577. for (xferp = 11; xferp >= 4; xferp--) {
  578. int ok;
  579. int tp;
  580. /* calculate scsi rate - round up again */
  581. /* start from sclk for accuracy */
  582. int totaldivide = xferp * cf2[scf];
  583. sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
  584. if (sr > scsilimit)
  585. break;
  586. /*
  587. * now work out transfer period
  588. * round down now so that period is pessimistic
  589. */
  590. tp = (MEGA * 1000) / sr;
  591. /*
  592. * bounds check it
  593. */
  594. if (tp < 25 || tp > 255 * 4)
  595. continue;
  596. /*
  597. * spot stupid special case for Ultra or Ultra2
  598. * while working out factor
  599. */
  600. if (tp == 25)
  601. tpf = 10;
  602. else if (tp == 50)
  603. tpf = 12;
  604. else if (tp < 52)
  605. continue;
  606. else
  607. tpf = tp / 4;
  608. /*
  609. * now check tpf looks sensible
  610. * given core rate
  611. */
  612. switch (fast) {
  613. case 0:
  614. /* scf must be ccf for SCSI 1 */
  615. ok = tpf >= 50 && scf == c->ccf;
  616. break;
  617. case 1:
  618. ok = tpf >= 25 && tpf < 50;
  619. break;
  620. case 2:
  621. /*
  622. * must use xferp of 4, or 5 at a pinch
  623. * for an Ultra transfer
  624. */
  625. ok = xferp <= 5 && tpf >= 12 && tpf < 25;
  626. break;
  627. case 3:
  628. ok = xferp == 4 && (tpf == 10 || tpf == 11);
  629. break;
  630. default:
  631. ok = 0;
  632. }
  633. if (!ok)
  634. continue;
  635. c->synctab[scf - 1][xferp - 4] = tpf;
  636. }
  637. }
  638. #ifndef NO_ULTRA2
  639. if (c->v->feature & Ultra2)
  640. tpf = 10;
  641. else
  642. #endif
  643. if (c->v->feature & Ultra)
  644. tpf = 12;
  645. else
  646. tpf = 25;
  647. for (; tpf < 256; tpf++) {
  648. if (chooserate(c, tpf, &scf, &xferp) == tpf) {
  649. unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
  650. unsigned long khz = (MEGA + tp - 1) / (tp);
  651. KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
  652. tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
  653. xferp + 4, khz / 1000, khz % 1000);
  654. USED(khz);
  655. if (c->tpf == 0)
  656. c->tpf = tpf; /* note lowest value for controller */
  657. }
  658. }
  659. }
  660. static void
  661. synctodsa(Dsa *dsa, Controller *c)
  662. {
  663. /*
  664. KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
  665. dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
  666. */
  667. dsa->scntl3 = c->scntl3[dsa->target];
  668. dsa->sxfer = c->sxfer[dsa->target];
  669. }
  670. static void
  671. setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
  672. {
  673. c->scntl3[target] =
  674. (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
  675. c->sxfer[target] = (xferp << 5) | reqack;
  676. c->s[target] = BothDone;
  677. if (dsa) {
  678. synctodsa(dsa, c);
  679. c->n->scntl3 = c->scntl3[target];
  680. c->n->sxfer = c->sxfer[target];
  681. }
  682. }
  683. static void
  684. setasync(Dsa *dsa, Controller *c, int target)
  685. {
  686. setsync(dsa, c, target, 0, c->ccf, 0, 0);
  687. }
  688. static void
  689. setwide(Dsa *dsa, Controller *c, int target, uchar wide)
  690. {
  691. c->scntl3[target] = wide ? (1 << 3) : 0;
  692. setasync(dsa, c, target);
  693. c->s[target] = WideDone;
  694. }
  695. static int
  696. buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
  697. {
  698. *buf++ = X_MSG;
  699. *buf++ = 3;
  700. *buf++ = X_MSG_SDTR;
  701. *buf++ = tpf;
  702. *buf = offset;
  703. return 5;
  704. }
  705. static int
  706. buildwdtrmsg(uchar *buf, uchar expo)
  707. {
  708. *buf++ = X_MSG;
  709. *buf++ = 2;
  710. *buf++ = X_MSG_WDTR;
  711. *buf = expo;
  712. return 4;
  713. }
  714. static void
  715. start(Controller *c, long entry)
  716. {
  717. ulong p;
  718. if (c->running)
  719. panic(PRINTPREFIX "start called while running");
  720. c->running = 1;
  721. p = c->scriptpa + entry;
  722. lesetl(c->n->dsp, p);
  723. coherence();
  724. if (c->ssm)
  725. c->n->dcntl |= 0x4; /* start DMA in SSI mode */
  726. }
  727. static void
  728. ncrcontinue(Controller *c)
  729. {
  730. if (c->running)
  731. panic(PRINTPREFIX "ncrcontinue called while running");
  732. /* set the start DMA bit to continue execution */
  733. c->running = 1;
  734. coherence();
  735. c->n->dcntl |= 0x4;
  736. }
  737. static void
  738. softreset(Controller *c)
  739. {
  740. Ncr *n = c->n;
  741. n->istat = Srst; /* software reset */
  742. n->istat = 0;
  743. /* general initialisation */
  744. n->scid = (1 << 6) | 7; /* respond to reselect, ID 7 */
  745. n->respid = 1 << 7; /* response ID = 7 */
  746. #ifdef INTERNAL_SCLK
  747. n->stest1 = 0x80; /* disable external scsi clock */
  748. #else
  749. n->stest1 = 0x00;
  750. #endif
  751. n->stime0 = 0xdd; /* about 0.5 second timeout on each device */
  752. n->scntl0 |= 0x8; /* Enable parity checking */
  753. /* continued setup */
  754. n->sien0 = 0x8f;
  755. n->sien1 = 0x04;
  756. n->dien = 0x7d;
  757. n->stest3 = 0x80; /* TolerANT enable */
  758. c->running = 0;
  759. if (c->v->feature & BigFifo)
  760. n->ctest5 = (1 << 5);
  761. n->dmode = c->v->burst << 6; /* set burst length bits */
  762. if (c->v->burst & 4)
  763. n->ctest5 |= (1 << 2); /* including overflow into ctest5 bit 2 */
  764. if (c->v->feature & Prefetch)
  765. n->dcntl |= (1 << 5); /* prefetch enable */
  766. else if (c->v->feature & BurstOpCodeFetch)
  767. n->dmode |= (1 << 1); /* burst opcode fetch */
  768. if (c->v->feature & Differential) {
  769. /* chip capable */
  770. if ((c->feature & Differential) || bios_set_differential(c)) {
  771. /* user enabled, or some evidence bios set differential */
  772. if (n->sstat2 & (1 << 2))
  773. print(PRINTPREFIX "can't go differential; wrong cable\n");
  774. else {
  775. n->stest2 = (1 << 5);
  776. print(PRINTPREFIX "differential mode set\n");
  777. }
  778. }
  779. }
  780. if (c->clockmult) {
  781. n->stest1 |= (1 << 3); /* power up doubler */
  782. delay(2);
  783. n->stest3 |= (1 << 5); /* stop clock */
  784. n->stest1 |= (1 << 2); /* enable doubler */
  785. n->stest3 &= ~(1 << 5); /* start clock */
  786. /* pray */
  787. }
  788. }
  789. static void
  790. msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
  791. {
  792. uchar histpf, hisreqack;
  793. int tpf;
  794. int scf, xferp;
  795. int len;
  796. Ncr *n = c->n;
  797. switch (c->s[dsa->target]) {
  798. case SyncInit:
  799. switch (msg) {
  800. case A_SIR_MSG_SDTR:
  801. /* reply to my SDTR */
  802. histpf = n->scratcha[2];
  803. hisreqack = n->scratcha[3];
  804. KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
  805. dsa->target, histpf, hisreqack);
  806. if (hisreqack == 0)
  807. setasync(dsa, c, dsa->target);
  808. else {
  809. /* hisreqack should be <= c->v->maxsyncoff */
  810. tpf = chooserate(c, histpf, &scf, &xferp);
  811. KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
  812. dsa->target, tpf, hisreqack);
  813. setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  814. }
  815. *cont = -2;
  816. return;
  817. case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  818. /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  819. KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  820. KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  821. setasync(dsa, c, dsa->target);
  822. *cont = E_to_decisions;
  823. return;
  824. case A_SIR_MSG_REJECT:
  825. /* rejection of my SDTR */
  826. KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
  827. //async:
  828. KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  829. setasync(dsa, c, dsa->target);
  830. *cont = -2;
  831. return;
  832. }
  833. break;
  834. case WideInit:
  835. switch (msg) {
  836. case A_SIR_MSG_WDTR:
  837. /* reply to my WDTR */
  838. KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
  839. dsa->target, n->scratcha[2]);
  840. setwide(dsa, c, dsa->target, n->scratcha[2]);
  841. *cont = -2;
  842. return;
  843. case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  844. /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  845. KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  846. setwide(dsa, c, dsa->target, 0);
  847. *cont = E_to_decisions;
  848. return;
  849. case A_SIR_MSG_REJECT:
  850. /* rejection of my SDTR */
  851. KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
  852. setwide(dsa, c, dsa->target, 0);
  853. *cont = -2;
  854. return;
  855. }
  856. break;
  857. case NeitherDone:
  858. case WideDone:
  859. case BothDone:
  860. switch (msg) {
  861. case A_SIR_MSG_WDTR: {
  862. uchar hiswide, mywide;
  863. hiswide = n->scratcha[2];
  864. mywide = (c->v->feature & Wide) != 0;
  865. KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
  866. dsa->target, hiswide);
  867. if (hiswide < mywide)
  868. mywide = hiswide;
  869. KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
  870. dsa->target, mywide);
  871. setwide(dsa, c, dsa->target, mywide);
  872. len = buildwdtrmsg(dsa->msg_out, mywide);
  873. setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  874. *cont = E_response;
  875. c->s[dsa->target] = WideResponse;
  876. return;
  877. }
  878. case A_SIR_MSG_SDTR:
  879. #ifdef ASYNC_ONLY
  880. *cont = E_reject;
  881. return;
  882. #else
  883. /* target decides to renegotiate */
  884. histpf = n->scratcha[2];
  885. hisreqack = n->scratcha[3];
  886. KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
  887. dsa->target, histpf, hisreqack);
  888. if (hisreqack == 0) {
  889. /* he wants asynchronous */
  890. setasync(dsa, c, dsa->target);
  891. tpf = 0;
  892. }
  893. else {
  894. /* he wants synchronous */
  895. tpf = chooserate(c, histpf, &scf, &xferp);
  896. if (hisreqack > c->v->maxsyncoff)
  897. hisreqack = c->v->maxsyncoff;
  898. KPRINT(PRINTPREFIX "%d: using %d %d\n",
  899. dsa->target, tpf, hisreqack);
  900. setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  901. }
  902. /* build my SDTR message */
  903. len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
  904. setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  905. *cont = E_response;
  906. c->s[dsa->target] = SyncResponse;
  907. return;
  908. #endif
  909. }
  910. break;
  911. case WideResponse:
  912. switch (msg) {
  913. case A_SIR_EV_RESPONSE_OK:
  914. c->s[dsa->target] = WideDone;
  915. KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
  916. *cont = -2;
  917. return;
  918. case A_SIR_MSG_REJECT:
  919. setwide(dsa, c, dsa->target, 0);
  920. KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
  921. *cont = -2;
  922. return;
  923. }
  924. break;
  925. case SyncResponse:
  926. switch (msg) {
  927. case A_SIR_EV_RESPONSE_OK:
  928. c->s[dsa->target] = BothDone;
  929. KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
  930. dsa->target, phase[n->sstat1 & 7]);
  931. *cont = -2;
  932. return; /* chf */
  933. case A_SIR_MSG_REJECT:
  934. setasync(dsa, c, dsa->target);
  935. KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
  936. *cont = -2;
  937. return;
  938. }
  939. break;
  940. }
  941. KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
  942. dsa->target, c->s[dsa->target], msg);
  943. *wakeme = 1;
  944. return;
  945. }
  946. static void
  947. calcblockdma(Dsa *d, ulong base, ulong count)
  948. {
  949. ulong blocks;
  950. if (DEBUG(3))
  951. blocks = 0;
  952. else {
  953. blocks = count / A_BSIZE;
  954. if (blocks > 255)
  955. blocks = 255;
  956. }
  957. d->dmablks = blocks;
  958. d->dmaaddr[0] = base;
  959. d->dmaaddr[1] = base >> 8;
  960. d->dmaaddr[2] = base >> 16;
  961. d->dmaaddr[3] = base >> 24;
  962. setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
  963. d->flag = legetl(d->data_buf.dbc) == 0;
  964. }
  965. static ulong
  966. read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
  967. {
  968. ulong dbc;
  969. uchar dfifo = n->dfifo;
  970. int inchip;
  971. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  972. if (n->ctest5 & (1 << 5))
  973. inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
  974. else
  975. inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
  976. if (inchip) {
  977. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
  978. dsa->target, dsa->lun, inchip);
  979. }
  980. if (n->sxfer & SYNCOFFMASK(c)) {
  981. /* SCSI FIFO */
  982. uchar fifo = n->sstat1 >> 4;
  983. if (c->v->maxsyncoff > 8)
  984. fifo |= (n->sstat2 & (1 << 4));
  985. if (fifo) {
  986. inchip += fifo;
  987. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
  988. dsa->target, dsa->lun, fifo);
  989. }
  990. }
  991. else {
  992. if (n->sstat0 & (1 << 7)) {
  993. inchip++;
  994. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
  995. dsa->target, dsa->lun);
  996. }
  997. if (n->sstat2 & (1 << 7)) {
  998. inchip++;
  999. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
  1000. dsa->target, dsa->lun);
  1001. }
  1002. }
  1003. USED(inchip);
  1004. return dbc;
  1005. }
  1006. static ulong
  1007. write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
  1008. {
  1009. ulong dbc;
  1010. uchar dfifo = n->dfifo;
  1011. int inchip;
  1012. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  1013. USED(dsa);
  1014. if (n->ctest5 & (1 << 5))
  1015. inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
  1016. else
  1017. inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
  1018. #ifdef WMR_DEBUG
  1019. if (inchip) {
  1020. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
  1021. dsa->target, dsa->lun, inchip);
  1022. }
  1023. #endif
  1024. if (n->sstat0 & (1 << 5)) {
  1025. inchip++;
  1026. #ifdef WMR_DEBUG
  1027. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
  1028. #endif
  1029. }
  1030. if (n->sstat2 & (1 << 5)) {
  1031. inchip++;
  1032. #ifdef WMR_DEBUG
  1033. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
  1034. #endif
  1035. }
  1036. if (n->sxfer & SYNCOFFMASK(c)) {
  1037. /* synchronous SODR */
  1038. if (n->sstat0 & (1 << 6)) {
  1039. inchip++;
  1040. #ifdef WMR_DEBUG
  1041. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
  1042. dsa->target, dsa->lun);
  1043. #endif
  1044. }
  1045. if (n->sstat2 & (1 << 6)) {
  1046. inchip++;
  1047. #ifdef WMR_DEBUG
  1048. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
  1049. dsa->target, dsa->lun);
  1050. #endif
  1051. }
  1052. }
  1053. /* clear the dma fifo */
  1054. n->ctest3 |= (1 << 2);
  1055. /* wait till done */
  1056. while ((n->dstat & Dfe) == 0)
  1057. ;
  1058. return dbc + inchip;
  1059. }
  1060. static void
  1061. sd53c8xxinterrupt(Ureg *ur, void *a)
  1062. {
  1063. uchar istat;
  1064. ushort sist;
  1065. uchar dstat;
  1066. int wakeme = 0;
  1067. int cont = -1;
  1068. Dsa *dsa;
  1069. ulong dsapa;
  1070. Controller *c = a;
  1071. Ncr *n = c->n;
  1072. USED(ur);
  1073. if (DEBUG(1)) {
  1074. IPRINT(PRINTPREFIX "int\n");
  1075. }
  1076. ilock(c);
  1077. istat = n->istat;
  1078. if (istat & Intf) {
  1079. Dsa *d;
  1080. int wokesomething = 0;
  1081. if (DEBUG(1)) {
  1082. IPRINT(PRINTPREFIX "Intfly\n");
  1083. }
  1084. n->istat = Intf;
  1085. /* search for structures in A_STATE_DONE */
  1086. for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  1087. if (d->stateb == A_STATE_DONE) {
  1088. d->p9status = d->status;
  1089. if (DEBUG(1)) {
  1090. IPRINT(PRINTPREFIX "waking up dsa %lux\n", (ulong)d);
  1091. }
  1092. wakeup(d);
  1093. wokesomething = 1;
  1094. }
  1095. }
  1096. if (!wokesomething) {
  1097. IPRINT(PRINTPREFIX "nothing to wake up\n");
  1098. }
  1099. }
  1100. if ((istat & (Sip | Dip)) == 0) {
  1101. if (DEBUG(1)) {
  1102. IPRINT(PRINTPREFIX "int end %x\n", istat);
  1103. }
  1104. iunlock(c);
  1105. return;
  1106. }
  1107. sist = (n->sist1<<8)|n->sist0; /* BUG? can two-byte read be inconsistent? */
  1108. dstat = n->dstat;
  1109. dsapa = legetl(n->dsa);
  1110. /*
  1111. * Can't compute dsa until we know that dsapa is valid.
  1112. */
  1113. if(dsapa < -KZERO)
  1114. dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
  1115. else{
  1116. dsa = nil;
  1117. /*
  1118. * happens at startup on some cards but we
  1119. * don't actually deref dsa because none of the
  1120. * flags we are about are set.
  1121. * still, print in case that changes and we're
  1122. * about to dereference nil.
  1123. */
  1124. iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
  1125. }
  1126. c->running = 0;
  1127. if (istat & Sip) {
  1128. if (DEBUG(1)) {
  1129. IPRINT("sist = %.4x\n", sist);
  1130. }
  1131. if (sist & 0x80) {
  1132. ulong addr;
  1133. ulong sa;
  1134. ulong dbc;
  1135. ulong tbc;
  1136. int dmablks;
  1137. ulong dmaaddr;
  1138. addr = legetl(n->dsp);
  1139. sa = addr - c->scriptpa;
  1140. if (DEBUG(1) || DEBUG(2)) {
  1141. IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
  1142. dsa->target, dsa->lun, sa);
  1143. }
  1144. /*
  1145. * now recover
  1146. */
  1147. if (sa == E_data_in_mismatch) {
  1148. /*
  1149. * though this is a failure in the residue, there may have been blocks
  1150. * as well. if so, dmablks will not have been zeroed, since the state
  1151. * was not saved by the microcode.
  1152. */
  1153. dbc = read_mismatch_recover(c, n, dsa);
  1154. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1155. dsa->dmablks = 0;
  1156. n->scratcha[2] = 0;
  1157. advancedata(&dsa->data_buf, tbc);
  1158. if (DEBUG(1) || DEBUG(2)) {
  1159. IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
  1160. dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
  1161. }
  1162. cont = E_data_mismatch_recover;
  1163. }
  1164. else if (sa == E_data_in_block_mismatch) {
  1165. dbc = read_mismatch_recover(c, n, dsa);
  1166. tbc = A_BSIZE - dbc;
  1167. /* recover current state from registers */
  1168. dmablks = n->scratcha[2];
  1169. dmaaddr = legetl(n->scratchb);
  1170. /* we have got to dmaaddr + tbc */
  1171. /* we have dmablks * A_BSIZE - tbc + residue left to do */
  1172. /* so remaining transfer is */
  1173. IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
  1174. dmaaddr, tbc, dmablks);
  1175. calcblockdma(dsa, dmaaddr + tbc,
  1176. dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
  1177. /* copy changes into scratch registers */
  1178. IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
  1179. dsa->dmablks, legetl(dsa->dmaaddr),
  1180. legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
  1181. n->scratcha[2] = dsa->dmablks;
  1182. lesetl(n->scratchb, dsa->dmancr);
  1183. cont = E_data_block_mismatch_recover;
  1184. }
  1185. else if (sa == E_data_out_mismatch) {
  1186. dbc = write_mismatch_recover(c, n, dsa);
  1187. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1188. dsa->dmablks = 0;
  1189. n->scratcha[2] = 0;
  1190. advancedata(&dsa->data_buf, tbc);
  1191. if (DEBUG(1) || DEBUG(2)) {
  1192. IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
  1193. dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
  1194. }
  1195. cont = E_data_mismatch_recover;
  1196. }
  1197. else if (sa == E_data_out_block_mismatch) {
  1198. dbc = write_mismatch_recover(c, n, dsa);
  1199. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1200. /* recover current state from registers */
  1201. dmablks = n->scratcha[2];
  1202. dmaaddr = legetl(n->scratchb);
  1203. /* we have got to dmaaddr + tbc */
  1204. /* we have dmablks blocks - tbc + residue left to do */
  1205. /* so remaining transfer is */
  1206. IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
  1207. dmaaddr, tbc, dmablks);
  1208. calcblockdma(dsa, dmaaddr + tbc,
  1209. dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
  1210. /* copy changes into scratch registers */
  1211. n->scratcha[2] = dsa->dmablks;
  1212. lesetl(n->scratchb, dsa->dmancr);
  1213. cont = E_data_block_mismatch_recover;
  1214. }
  1215. else if (sa == E_id_out_mismatch) {
  1216. /*
  1217. * target switched phases while attention held during
  1218. * message out. The possibilities are:
  1219. * 1. It didn't like the last message. This is indicated
  1220. * by the new phase being message_in. Use script to recover
  1221. *
  1222. * 2. It's not SCSI-II compliant. The new phase will be other
  1223. * than message_in. We should also indicate that the device
  1224. * is asynchronous, if it's the SDTR that got ignored
  1225. *
  1226. * For now, if the phase switch is not to message_in, and
  1227. * and it happens after IDENTIFY and before SDTR, we
  1228. * notify the negotiation state machine.
  1229. */
  1230. ulong lim = legetl(dsa->msg_out_buf.dbc);
  1231. uchar p = n->sstat1 & 7;
  1232. dbc = write_mismatch_recover(c, n, dsa);
  1233. tbc = lim - dbc;
  1234. IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
  1235. dsa->target, dsa->lun, tbc, lim, phase[p]);
  1236. if (p != MessageIn && tbc == 1) {
  1237. msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
  1238. }
  1239. else
  1240. cont = E_id_out_mismatch_recover;
  1241. }
  1242. else if (sa == E_cmd_out_mismatch) {
  1243. /*
  1244. * probably the command count is longer than the device wants ...
  1245. */
  1246. ulong lim = legetl(dsa->cmd_buf.dbc);
  1247. uchar p = n->sstat1 & 7;
  1248. dbc = write_mismatch_recover(c, n, dsa);
  1249. tbc = lim - dbc;
  1250. IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
  1251. dsa->target, dsa->lun, tbc, lim, phase[p]);
  1252. USED(p, tbc);
  1253. cont = E_to_decisions;
  1254. }
  1255. else {
  1256. IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
  1257. dsa->target, dsa->lun, sa,
  1258. phase[n->dcmd & 7],
  1259. phase[n->sstat1 & 7]);
  1260. dumpncrregs(c, 1);
  1261. dsa->p9status = SDeio; /* chf */
  1262. wakeme = 1;
  1263. }
  1264. }
  1265. /*else*/ if (sist & 0x400) {
  1266. if (DEBUG(0)) {
  1267. IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
  1268. }
  1269. dsa->p9status = SDtimeout;
  1270. dsa->stateb = A_STATE_DONE;
  1271. coherence();
  1272. softreset(c);
  1273. cont = E_issue_check;
  1274. wakeme = 1;
  1275. }
  1276. if (sist & 0x1) {
  1277. IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
  1278. dsa->parityerror = 1;
  1279. }
  1280. if (sist & 0x4) {
  1281. IPRINT(PRINTPREFIX "%d/%d: unexpected disconnect\n",
  1282. dsa->target, dsa->lun);
  1283. dumpncrregs(c, 1);
  1284. //wakeme = 1;
  1285. dsa->p9status = SDeio;
  1286. }
  1287. }
  1288. if (istat & Dip) {
  1289. if (DEBUG(1)) {
  1290. IPRINT("dstat = %.2x\n", dstat);
  1291. }
  1292. /*else*/ if (dstat & Ssi) {
  1293. ulong w = legetl(n->dsp) - c->scriptpa;
  1294. IPRINT("[%lux]", w);
  1295. USED(w);
  1296. cont = -2; /* restart */
  1297. }
  1298. if (dstat & Sir) {
  1299. switch (legetl(n->dsps)) {
  1300. case A_SIR_MSG_IO_COMPLETE:
  1301. dsa->p9status = dsa->status;
  1302. wakeme = 1;
  1303. break;
  1304. case A_SIR_MSG_SDTR:
  1305. case A_SIR_MSG_WDTR:
  1306. case A_SIR_MSG_REJECT:
  1307. case A_SIR_EV_RESPONSE_OK:
  1308. msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
  1309. break;
  1310. case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
  1311. /* back up one in the data transfer */
  1312. IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
  1313. dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
  1314. if (dsa->flag == 2) {
  1315. IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
  1316. dsa->target, dsa->lun);
  1317. }
  1318. else {
  1319. calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
  1320. dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
  1321. }
  1322. cont = -2;
  1323. break;
  1324. case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
  1325. IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
  1326. n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
  1327. dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
  1328. dumpncrregs(c, 1);
  1329. wakeme = 1;
  1330. break;
  1331. case A_SIR_NOTIFY_LOAD_STATE:
  1332. IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
  1333. if (dsa == (void*)KZERO || dsa == (void*)-1) {
  1334. dsadump(c);
  1335. dumpncrregs(c, 1);
  1336. panic("bad dsa in load_state");
  1337. }
  1338. cont = -2;
  1339. break;
  1340. case A_SIR_NOTIFY_MSG_IN:
  1341. IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
  1342. dsa->target, dsa->lun, n->sfbr);
  1343. cont = -2;
  1344. break;
  1345. case A_SIR_NOTIFY_DISC:
  1346. IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
  1347. goto dsadump;
  1348. case A_SIR_NOTIFY_STATUS:
  1349. IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
  1350. cont = -2;
  1351. break;
  1352. case A_SIR_NOTIFY_COMMAND:
  1353. IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
  1354. cont = -2;
  1355. break;
  1356. case A_SIR_NOTIFY_DATA_IN:
  1357. IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
  1358. dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
  1359. cont = -2;
  1360. break;
  1361. case A_SIR_NOTIFY_BLOCK_DATA_IN:
  1362. IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
  1363. dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
  1364. cont = -2;
  1365. break;
  1366. case A_SIR_NOTIFY_DATA_OUT:
  1367. IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
  1368. cont = -2;
  1369. break;
  1370. case A_SIR_NOTIFY_DUMP:
  1371. IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
  1372. dumpncrregs(c, 1);
  1373. cont = -2;
  1374. break;
  1375. case A_SIR_NOTIFY_DUMP2:
  1376. IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
  1377. IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
  1378. IPRINT(" dsa %lux", legetl(n->dsa));
  1379. IPRINT(" sfbr %ux", n->sfbr);
  1380. IPRINT(" a %lux", legetl(n->scratcha));
  1381. IPRINT(" b %lux", legetl(n->scratchb));
  1382. IPRINT(" ssid %ux", n->ssid);
  1383. IPRINT("\n");
  1384. cont = -2;
  1385. break;
  1386. case A_SIR_NOTIFY_WAIT_RESELECT:
  1387. IPRINT(PRINTPREFIX "wait reselect\n");
  1388. cont = -2;
  1389. break;
  1390. case A_SIR_NOTIFY_RESELECT:
  1391. IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
  1392. n->ssid, n->sfbr, TK2MS(m->ticks));
  1393. cont = -2;
  1394. break;
  1395. case A_SIR_NOTIFY_ISSUE:
  1396. IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
  1397. dsadump:
  1398. IPRINT(" tgt=%d", dsa->target);
  1399. IPRINT(" time=%ld", TK2MS(m->ticks));
  1400. IPRINT("\n");
  1401. cont = -2;
  1402. break;
  1403. case A_SIR_NOTIFY_ISSUE_CHECK:
  1404. IPRINT(PRINTPREFIX "issue check\n");
  1405. cont = -2;
  1406. break;
  1407. case A_SIR_NOTIFY_SIGP:
  1408. IPRINT(PRINTPREFIX "responded to SIGP\n");
  1409. cont = -2;
  1410. break;
  1411. case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
  1412. ulong *dsp = c->script + (legetl(n->dsp)-c->scriptpa)/4;
  1413. int x;
  1414. IPRINT(PRINTPREFIX "code at %lux", dsp - c->script);
  1415. for (x = 0; x < 6; x++) {
  1416. IPRINT(" %.8lux", dsp[x]);
  1417. }
  1418. IPRINT("\n");
  1419. USED(dsp);
  1420. cont = -2;
  1421. break;
  1422. }
  1423. case A_SIR_NOTIFY_WSR:
  1424. IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
  1425. cont = -2;
  1426. break;
  1427. case A_SIR_NOTIFY_LOAD_SYNC:
  1428. IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
  1429. dsa->target, dsa->lun, n->scntl3, n->sxfer);
  1430. cont = -2;
  1431. break;
  1432. case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
  1433. if (DEBUG(2)) {
  1434. IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
  1435. dsa->target, dsa->lun);
  1436. }
  1437. cont = -2;
  1438. break;
  1439. case A_error_reselected: /* dsa isn't valid here */
  1440. iprint(PRINTPREFIX "reselection error\n");
  1441. dumpncrregs(c, 1);
  1442. for (dsa = KPTR(legetl(c->dsalist.head)); dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
  1443. IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
  1444. }
  1445. break;
  1446. default:
  1447. IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
  1448. dsa->target, dsa->lun, legetl(n->dsps));
  1449. dumpncrregs(c, 1);
  1450. wakeme = 1;
  1451. }
  1452. }
  1453. /*else*/ if (dstat & Iid) {
  1454. int i, target, lun;
  1455. ulong addr, dbc, *v;
  1456. addr = legetl(n->dsp);
  1457. if(dsa){
  1458. target = dsa->target;
  1459. lun = dsa->lun;
  1460. }else{
  1461. target = -1;
  1462. lun = -1;
  1463. }
  1464. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  1465. // if(dsa == nil)
  1466. idebug++;
  1467. IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
  1468. target, lun,
  1469. addr, addr - c->scriptpa, dbc);
  1470. addr = (ulong)c->script + addr - c->scriptpa;
  1471. addr -= 64;
  1472. addr &= ~63;
  1473. v = (ulong*)addr;
  1474. for(i=0; i<8; i++){
  1475. IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n",
  1476. addr, v[0], v[1], v[2], v[3]);
  1477. addr += 4*4;
  1478. v += 4;
  1479. }
  1480. USED(addr, dbc);
  1481. if(dsa == nil){
  1482. dsadump(c);
  1483. dumpncrregs(c, 1);
  1484. panic("bad dsa");
  1485. }
  1486. dsa->p9status = SDeio;
  1487. wakeme = 1;
  1488. }
  1489. /*else*/ if (dstat & Bf) {
  1490. IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
  1491. dumpncrregs(c, 1);
  1492. dsa->p9status = SDeio;
  1493. wakeme = 1;
  1494. }
  1495. }
  1496. if (cont == -2)
  1497. ncrcontinue(c);
  1498. else if (cont >= 0)
  1499. start(c, cont);
  1500. if (wakeme){
  1501. if(dsa->p9status == SDnostatus)
  1502. dsa->p9status = SDeio;
  1503. wakeup(dsa);
  1504. }
  1505. iunlock(c);
  1506. if (DEBUG(1)) {
  1507. IPRINT(PRINTPREFIX "int end 1\n");
  1508. }
  1509. }
  1510. static int
  1511. done(void *arg)
  1512. {
  1513. return ((Dsa *)arg)->p9status != SDnostatus;
  1514. }
  1515. static void
  1516. setmovedata(Movedata *d, ulong pa, ulong bc)
  1517. {
  1518. d->pa[0] = pa;
  1519. d->pa[1] = pa>>8;
  1520. d->pa[2] = pa>>16;
  1521. d->pa[3] = pa>>24;
  1522. d->dbc[0] = bc;
  1523. d->dbc[1] = bc>>8;
  1524. d->dbc[2] = bc>>16;
  1525. d->dbc[3] = bc>>24;
  1526. }
  1527. static void
  1528. advancedata(Movedata *d, long v)
  1529. {
  1530. lesetl(d->pa, legetl(d->pa) + v);
  1531. lesetl(d->dbc, legetl(d->dbc) - v);
  1532. }
  1533. static void
  1534. dumpwritedata(uchar *data, int datalen)
  1535. {
  1536. int i;
  1537. uchar *bp;
  1538. if (!DEBUG(0)){
  1539. USED(data, datalen);
  1540. return;
  1541. }
  1542. if (datalen) {
  1543. KPRINT(PRINTPREFIX "write:");
  1544. for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
  1545. KPRINT("%.2ux", *bp);
  1546. }
  1547. if (i < datalen) {
  1548. KPRINT("...");
  1549. }
  1550. KPRINT("\n");
  1551. }
  1552. }
  1553. static void
  1554. dumpreaddata(uchar *data, int datalen)
  1555. {
  1556. int i;
  1557. uchar *bp;
  1558. if (!DEBUG(0)){
  1559. USED(data, datalen);
  1560. return;
  1561. }
  1562. if (datalen) {
  1563. KPRINT(PRINTPREFIX "read:");
  1564. for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
  1565. KPRINT("%.2ux", *bp);
  1566. }
  1567. if (i < datalen) {
  1568. KPRINT("...");
  1569. }
  1570. KPRINT("\n");
  1571. }
  1572. }
  1573. static void
  1574. busreset(Controller *c)
  1575. {
  1576. int x, ntarget;
  1577. /* bus reset */
  1578. c->n->scntl1 |= (1 << 3);
  1579. delay(500);
  1580. c->n->scntl1 &= ~(1 << 3);
  1581. if(!(c->v->feature & Wide))
  1582. ntarget = 8;
  1583. else
  1584. ntarget = MAXTARGET;
  1585. for (x = 0; x < ntarget; x++) {
  1586. setwide(0, c, x, 0);
  1587. #ifndef ASYNC_ONLY
  1588. c->s[x] = NeitherDone;
  1589. #endif
  1590. }
  1591. c->capvalid = 0;
  1592. }
  1593. static void
  1594. reset(Controller *c)
  1595. {
  1596. /* should wakeup all pending tasks */
  1597. softreset(c);
  1598. busreset(c);
  1599. }
  1600. static int
  1601. sd53c8xxrio(SDreq* r)
  1602. {
  1603. Dsa *d;
  1604. uchar *bp;
  1605. Controller *c;
  1606. uchar target_expo, my_expo;
  1607. int bc, check, i, status, target;
  1608. if((target = r->unit->subno) == 0x07)
  1609. return r->status = SDtimeout; /* assign */
  1610. c = r->unit->dev->ctlr;
  1611. check = 0;
  1612. d = dsaalloc(c, target, r->lun);
  1613. qlock(&c->q[target]); /* obtain access to target */
  1614. docheck:
  1615. /* load the transfer control stuff */
  1616. d->scsi_id_buf[0] = 0;
  1617. d->scsi_id_buf[1] = c->sxfer[target];
  1618. d->scsi_id_buf[2] = target;
  1619. d->scsi_id_buf[3] = c->scntl3[target];
  1620. synctodsa(d, c);
  1621. bc = 0;
  1622. d->msg_out[bc] = 0x80 | r->lun;
  1623. #ifndef NO_DISCONNECT
  1624. d->msg_out[bc] |= (1 << 6);
  1625. #endif
  1626. bc++;
  1627. /* work out what to do about negotiation */
  1628. switch (c->s[target]) {
  1629. default:
  1630. KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
  1631. c->s[target] = NeitherDone;
  1632. /* fall through */
  1633. case NeitherDone:
  1634. if ((c->capvalid & (1 << target)) == 0)
  1635. break;
  1636. target_expo = (c->cap[target] >> 5) & 3;
  1637. my_expo = (c->v->feature & Wide) != 0;
  1638. if (target_expo < my_expo)
  1639. my_expo = target_expo;
  1640. #ifdef ALWAYS_DO_WDTR
  1641. bc += buildwdtrmsg(d->msg_out + bc, my_expo);
  1642. KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
  1643. c->s[target] = WideInit;
  1644. break;
  1645. #else
  1646. if (my_expo) {
  1647. bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
  1648. KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
  1649. c->s[target] = WideInit;
  1650. break;
  1651. }
  1652. KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
  1653. /* fall through */
  1654. #endif
  1655. case WideDone:
  1656. if (c->cap[target] & (1 << 4)) {
  1657. KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
  1658. bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
  1659. c->s[target] = SyncInit;
  1660. break;
  1661. }
  1662. KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
  1663. c->s[target] = BothDone;
  1664. break;
  1665. case BothDone:
  1666. break;
  1667. }
  1668. setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
  1669. setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
  1670. calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
  1671. if (DEBUG(0)) {
  1672. KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
  1673. for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
  1674. KPRINT("%.2ux", *bp);
  1675. }
  1676. KPRINT("\n");
  1677. if (!r->write) {
  1678. KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
  1679. target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
  1680. }
  1681. else
  1682. dumpwritedata(r->data, r->dlen);
  1683. }
  1684. setmovedata(&d->status_buf, DMASEG(&d->status), 1);
  1685. d->p9status = SDnostatus;
  1686. d->parityerror = 0;
  1687. coherence();
  1688. d->stateb = A_STATE_ISSUE; /* start operation */
  1689. coherence();
  1690. ilock(c);
  1691. if (c->ssm)
  1692. c->n->dcntl |= 0x10; /* single step */
  1693. if (c->running) {
  1694. c->n->istat = Sigp;
  1695. }
  1696. else {
  1697. start(c, E_issue_check);
  1698. }
  1699. iunlock(c);
  1700. while(waserror())
  1701. ;
  1702. tsleep(d, done, d, 600 * 1000);
  1703. poperror();
  1704. if (!done(d)) {
  1705. KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
  1706. dumpncrregs(c, 0);
  1707. dsafree(c, d);
  1708. reset(c);
  1709. qunlock(&c->q[target]);
  1710. r->status = SDtimeout;
  1711. return r->status = SDtimeout; /* assign */
  1712. }
  1713. if((status = d->p9status) == SDeio)
  1714. c->s[target] = NeitherDone;
  1715. if (d->parityerror) {
  1716. status = SDeio;
  1717. }
  1718. /*
  1719. * adjust datalen
  1720. */
  1721. r->rlen = r->dlen;
  1722. if (DEBUG(0)) {
  1723. KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
  1724. target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
  1725. }
  1726. r->rlen = r->dlen;
  1727. if (d->flag != 2) {
  1728. r->rlen -= d->dmablks * A_BSIZE;
  1729. r->rlen -= legetl(d->data_buf.dbc);
  1730. }
  1731. if(!r->write)
  1732. dumpreaddata(r->data, r->rlen);
  1733. if (DEBUG(0)) {
  1734. KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
  1735. target, r->lun, d->p9status, status, r->rlen);
  1736. }
  1737. /*
  1738. * spot the identify
  1739. */
  1740. if ((c->capvalid & (1 << target)) == 0
  1741. && (status == SDok || status == SDcheck)
  1742. && r->cmd[0] == 0x12 && r->dlen >= 8) {
  1743. c->capvalid |= 1 << target;
  1744. bp = r->data;
  1745. c->cap[target] = bp[7];
  1746. KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
  1747. }
  1748. if(!check && status == SDcheck && !(r->flags & SDnosense)){
  1749. check = 1;
  1750. r->write = 0;
  1751. memset(r->cmd, 0, sizeof(r->cmd));
  1752. r->cmd[0] = 0x03;
  1753. r->cmd[1] = r->lun<<5;
  1754. r->cmd[4] = sizeof(r->sense)-1;
  1755. r->clen = 6;
  1756. r->data = r->sense;
  1757. r->dlen = sizeof(r->sense)-1;
  1758. /*
  1759. * Clear out the microcode state
  1760. * so the Dsa can be re-used.
  1761. */
  1762. lesetl(&d->stateb, A_STATE_ALLOCATED);
  1763. coherence();
  1764. goto docheck;
  1765. }
  1766. qunlock(&c->q[target]);
  1767. dsafree(c, d);
  1768. if(status == SDok && check){
  1769. status = SDcheck;
  1770. r->flags |= SDvalidsense;
  1771. }
  1772. if(DEBUG(0))
  1773. KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
  1774. target, r->flags, status, r->rlen);
  1775. if(r->flags & SDvalidsense){
  1776. if(!DEBUG(0))
  1777. KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
  1778. target, r->flags, status, r->rlen);
  1779. for(i = 0; i < r->rlen; i++)
  1780. KPRINT(" %2.2uX", r->sense[i]);
  1781. KPRINT("\n");
  1782. }
  1783. return r->status = status;
  1784. }
  1785. static void
  1786. cribbios(Controller *c)
  1787. {
  1788. c->bios.scntl3 = c->n->scntl3;
  1789. c->bios.stest2 = c->n->stest2;
  1790. print(PRINTPREFIX "bios scntl3(%.2x) stest2(%.2x)\n", c->bios.scntl3, c->bios.stest2);
  1791. }
  1792. static int
  1793. bios_set_differential(Controller *c)
  1794. {
  1795. /* Concept lifted from FreeBSD - thanks Gerard */
  1796. /* basically, if clock conversion factors are set, then there is
  1797. * evidence the bios had a go at the chip, and if so, it would
  1798. * have set the differential enable bit in stest2
  1799. */
  1800. return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
  1801. }
  1802. #define NCR_VID 0x1000
  1803. #define NCR_810_DID 0x0001
  1804. #define NCR_820_DID 0x0002 /* don't know enough about this one to support it */
  1805. #define NCR_825_DID 0x0003
  1806. #define NCR_815_DID 0x0004
  1807. #define SYM_810AP_DID 0x0005
  1808. #define SYM_860_DID 0x0006
  1809. #define SYM_896_DID 0x000b
  1810. #define SYM_895_DID 0x000c
  1811. #define SYM_885_DID 0x000d /* ditto */
  1812. #define SYM_875_DID 0x000f /* ditto */
  1813. #define SYM_1010_DID 0x0020
  1814. #define SYM_1011_DID 0x0021
  1815. #define SYM_875J_DID 0x008f
  1816. static Variant variant[] = {
  1817. { NCR_810_DID, 0x0f, "NCR53C810", Burst16, 8, 24, 0 },
  1818. { NCR_810_DID, 0x1f, "SYM53C810ALV", Burst16, 8, 24, Prefetch },
  1819. { NCR_810_DID, 0xff, "SYM53C810A", Burst16, 8, 24, Prefetch },
  1820. { SYM_810AP_DID, 0xff, "SYM53C810AP", Burst16, 8, 24, Prefetch },
  1821. { NCR_815_DID, 0xff, "NCR53C815", Burst16, 8, 24, BurstOpCodeFetch },
  1822. { NCR_825_DID, 0x0f, "NCR53C825", Burst16, 8, 24, Wide|BurstOpCodeFetch|Differential },
  1823. { NCR_825_DID, 0xff, "SYM53C825A", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
  1824. { SYM_860_DID, 0x0f, "SYM53C860", Burst16, 8, 24, Prefetch|Ultra },
  1825. { SYM_860_DID, 0xff, "SYM53C860LV", Burst16, 8, 24, Prefetch|Ultra },
  1826. { SYM_875_DID, 0x01, "SYM53C875r1", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
  1827. { SYM_875_DID, 0xff, "SYM53C875", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
  1828. { SYM_875J_DID, 0xff, "SYM53C875j", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
  1829. { SYM_885_DID, 0xff, "SYM53C885", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
  1830. { SYM_895_DID, 0xff, "SYM53C895", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1831. { SYM_896_DID, 0xff, "SYM53C896", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1832. { SYM_1010_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1833. { SYM_1011_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1834. };
  1835. static int
  1836. xfunc(Controller *c, enum na_external x, unsigned long *v)
  1837. {
  1838. switch (x) {
  1839. default:
  1840. print("xfunc: can't find external %d\n", x);
  1841. return 0;
  1842. case X_scsi_id_buf:
  1843. *v = offsetof(Dsa, scsi_id_buf[0]);
  1844. break;
  1845. case X_msg_out_buf:
  1846. *v = offsetof(Dsa, msg_out_buf);
  1847. break;
  1848. case X_cmd_buf:
  1849. *v = offsetof(Dsa, cmd_buf);
  1850. break;
  1851. case X_data_buf:
  1852. *v = offsetof(Dsa, data_buf);
  1853. break;
  1854. case X_status_buf:
  1855. *v = offsetof(Dsa, status_buf);
  1856. break;
  1857. case X_dsa_head:
  1858. *v = DMASEG(&c->dsalist.head[0]);
  1859. break;
  1860. case X_ssid_mask:
  1861. *v = SSIDMASK(c);
  1862. break;
  1863. }
  1864. return 1;
  1865. }
  1866. static int
  1867. na_fixup(Controller *c, ulong pa_reg,
  1868. struct na_patch *patch, int patches,
  1869. int (*externval)(Controller*, int, ulong*))
  1870. {
  1871. int p;
  1872. int v;
  1873. ulong *script, pa_script;
  1874. unsigned long lw, lv;
  1875. script = c->script;
  1876. pa_script = c->scriptpa;
  1877. for (p = 0; p < patches; p++) {
  1878. switch (patch[p].type) {
  1879. case 1:
  1880. /* script relative */
  1881. script[patch[p].lwoff] += pa_script;
  1882. break;
  1883. case 2:
  1884. /* register i/o relative */
  1885. script[patch[p].lwoff] += pa_reg;
  1886. break;
  1887. case 3:
  1888. /* data external */
  1889. lw = script[patch[p].lwoff];
  1890. v = (lw >> 8) & 0xff;
  1891. if (!(*externval)(c, v, &lv))
  1892. return 0;
  1893. v = lv & 0xff;
  1894. script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
  1895. break;
  1896. case 4:
  1897. /* 32 bit external */
  1898. lw = script[patch[p].lwoff];
  1899. if (!(*externval)(c, lw, &lv))
  1900. return 0;
  1901. script[patch[p].lwoff] = lv;
  1902. break;
  1903. case 5:
  1904. /* 24 bit external */
  1905. lw = script[patch[p].lwoff];
  1906. if (!(*externval)(c, lw & 0xffffff, &lv))
  1907. return 0;
  1908. script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
  1909. break;
  1910. }
  1911. }
  1912. return 1;
  1913. }
  1914. static SDev*
  1915. sd53c8xxpnp(void)
  1916. {
  1917. char *cp;
  1918. Pcidev *p;
  1919. Variant *v;
  1920. int ba, nctlr;
  1921. void *scriptma;
  1922. Controller *ctlr;
  1923. SDev *sdev, *head, *tail;
  1924. ulong regpa, *script, scriptpa;
  1925. void *regva, *scriptva;
  1926. if(cp = getconf("*maxsd53c8xx"))
  1927. nctlr = strtoul(cp, 0, 0);
  1928. else
  1929. nctlr = 32;
  1930. p = nil;
  1931. head = tail = nil;
  1932. while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
  1933. for(v = variant; v < &variant[nelem(variant)]; v++){
  1934. if(p->did == v->did && p->rid <= v->maxrid)
  1935. break;
  1936. }
  1937. if(v >= &variant[nelem(variant)]) {
  1938. print("no match\n");
  1939. continue;
  1940. }
  1941. print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
  1942. v->name, p->rid, p->intl, p->pcr);
  1943. regpa = p->mem[1].bar;
  1944. ba = 2;
  1945. if(regpa & 0x04){
  1946. if(p->mem[2].bar)
  1947. continue;
  1948. ba++;
  1949. }
  1950. if(regpa == 0)
  1951. print("regpa 0\n");
  1952. regpa &= ~0xF;
  1953. regva = vmap(regpa, p->mem[1].size);
  1954. if(regva == 0)
  1955. continue;
  1956. script = nil;
  1957. scriptpa = 0;
  1958. scriptva = nil;
  1959. scriptma = nil;
  1960. if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
  1961. scriptpa = p->mem[ba].bar;
  1962. if((scriptpa & 0x04) && p->mem[ba+1].bar){
  1963. vunmap(regva, p->mem[1].size);
  1964. continue;
  1965. }
  1966. scriptpa &= ~0x0F;
  1967. scriptva = vmap(scriptpa, p->mem[ba].size);
  1968. if(scriptva)
  1969. script = scriptva;
  1970. }
  1971. if(scriptpa == 0){
  1972. /*
  1973. * Either the map failed, or this chip does not have
  1974. * local RAM. It will need a copy of the microcode.
  1975. */
  1976. scriptma = malloc(sizeof(na_script));
  1977. if(scriptma == nil){
  1978. vunmap(regva, p->mem[1].size);
  1979. continue;
  1980. }
  1981. scriptpa = DMASEG(scriptma);
  1982. script = scriptma;
  1983. }
  1984. ctlr = malloc(sizeof(Controller));
  1985. sdev = malloc(sizeof(SDev));
  1986. if(ctlr == nil || sdev == nil){
  1987. buggery:
  1988. if(ctlr)
  1989. free(ctlr);
  1990. if(sdev)
  1991. free(sdev);
  1992. if(scriptma)
  1993. free(scriptma);
  1994. else if(scriptva)
  1995. vunmap(scriptva, p->mem[ba].size);
  1996. if(regva)
  1997. vunmap(regva, p->mem[1].size);
  1998. continue;
  1999. }
  2000. if(dsaend == nil)
  2001. dsaend = xalloc(sizeof *dsaend);
  2002. if(dsaend == nil)
  2003. panic("sd53c8xxpnp: no memory");
  2004. lesetl(&dsaend->stateb, A_STATE_END);
  2005. // lesetl(dsaend->next, DMASEG(dsaend));
  2006. coherence();
  2007. lesetl(ctlr->dsalist.head, DMASEG(dsaend));
  2008. coherence();
  2009. ctlr->dsalist.freechain = 0;
  2010. ctlr->n = regva;
  2011. ctlr->v = v;
  2012. ctlr->script = script;
  2013. memmove(ctlr->script, na_script, sizeof(na_script));
  2014. /*
  2015. * Because we don't yet have an abstraction for the
  2016. * addresses as seen from the controller side (and on
  2017. * the 386 it doesn't matter), the following two lines
  2018. * are different between the 386 and alpha copies of
  2019. * this driver.
  2020. */
  2021. ctlr->scriptpa = scriptpa;
  2022. if(!na_fixup(ctlr, regpa, na_patches, NA_PATCHES, xfunc)){
  2023. print("script fixup failed\n");
  2024. goto buggery;
  2025. }
  2026. swabl(ctlr->script, ctlr->script, sizeof(na_script));
  2027. ctlr->pcidev = p;
  2028. sdev->ifc = &sd53c8xxifc;
  2029. sdev->ctlr = ctlr;
  2030. sdev->idno = '0';
  2031. if(!(v->feature & Wide))
  2032. sdev->nunit = 8;
  2033. else
  2034. sdev->nunit = MAXTARGET;
  2035. ctlr->sdev = sdev;
  2036. if(head != nil)
  2037. tail->next = sdev;
  2038. else
  2039. head = sdev;
  2040. tail = sdev;
  2041. nctlr--;
  2042. }
  2043. return head;
  2044. }
  2045. static int
  2046. sd53c8xxenable(SDev* sdev)
  2047. {
  2048. Pcidev *pcidev;
  2049. Controller *ctlr;
  2050. char name[32];
  2051. ctlr = sdev->ctlr;
  2052. pcidev = ctlr->pcidev;
  2053. pcisetbme(pcidev);
  2054. ilock(ctlr);
  2055. synctabinit(ctlr);
  2056. cribbios(ctlr);
  2057. reset(ctlr);
  2058. snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
  2059. intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
  2060. iunlock(ctlr);
  2061. return 1;
  2062. }
  2063. SDifc sd53c8xxifc = {
  2064. "53c8xx", /* name */
  2065. sd53c8xxpnp, /* pnp */
  2066. nil, /* legacy */
  2067. sd53c8xxenable, /* enable */
  2068. nil, /* disable */
  2069. scsiverify, /* verify */
  2070. scsionline, /* online */
  2071. sd53c8xxrio, /* rio */
  2072. nil, /* rctl */
  2073. nil, /* wctl */
  2074. scsibio, /* bio */
  2075. nil, /* probe */
  2076. nil, /* clear */
  2077. nil, /* rtopctl */
  2078. nil, /* wtopctl */
  2079. };