sdmylex.c 28 KB

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  1. /*
  2. * Mylex MultiMaster (Buslogic BT-*) SCSI Host Adapter
  3. * in both 24-bit and 32-bit mode.
  4. * 24-bit mode works for Adaptec AHA-154xx series too.
  5. *
  6. * To do:
  7. * allocate more Ccb's as needed, up to NMbox-1;
  8. * add nmbox and nccb to Ctlr struct for the above;
  9. * 64-bit LUN/explicit wide support necessary?
  10. *
  11. */
  12. #include "u.h"
  13. #include "../port/lib.h"
  14. #include "mem.h"
  15. #include "dat.h"
  16. #include "fns.h"
  17. #include "io.h"
  18. #include "ureg.h"
  19. #include "../port/error.h"
  20. #include "../port/sd.h"
  21. #define K2BPA(va, tbdf) PADDR(va)
  22. #define BPA2K(pa, tbdf) KADDR(pa)
  23. extern SDifc sdmylexifc;
  24. enum { /* registers */
  25. Rcontrol = 0x00, /* WO: control register */
  26. Rstatus = 0x00, /* RO: status register */
  27. Rcpr = 0x01, /* WO: command/parameter register */
  28. Rdatain = 0x01, /* RO: data-in register */
  29. Rinterrupt = 0x02, /* RO: interrupt register */
  30. };
  31. enum { /* Rcontrol */
  32. Rsbus = 0x10, /* SCSI Bus Reset */
  33. Rint = 0x20, /* Interrupt Reset */
  34. Rsoft = 0x40, /* Soft Reset */
  35. Rhard = 0x80, /* Hard Reset */
  36. };
  37. enum { /* Rstatus */
  38. Cmdinv = 0x01, /* Command Invalid */
  39. Dirrdy = 0x04, /* Data In Register Ready */
  40. Cprbsy = 0x08, /* Command/Parameter Register Busy */
  41. Hardy = 0x10, /* Host Adapter Ready */
  42. Inreq = 0x20, /* Initialisation Required */
  43. Dfail = 0x40, /* Diagnostic Failure */
  44. Dact = 0x80, /* Diagnostic Active */
  45. };
  46. enum { /* Rcpr */
  47. Cinitialise = 0x01, /* Initialise Mailbox */
  48. Cstart = 0x02, /* Start Mailbox Command */
  49. Cinquiry = 0x04, /* Adapter Inquiry */
  50. Ceombri = 0x05, /* Enable OMBR Interrupt */
  51. Cinquire = 0x0B, /* Inquire Configuration */
  52. Cextbios = 0x28, /* AHA-1542: extended BIOS info. */
  53. Cmbienable = 0x29, /* AHA-1542: Mailbox interface enable */
  54. Ciem = 0x81, /* Initialise Extended Mailbox */
  55. Ciesi = 0x8D, /* Inquire Extended Setup Information */
  56. Cerrm = 0x8F, /* Enable strict round-robin mode */
  57. Cwide = 0x96, /* Wide CCB */
  58. };
  59. enum { /* Rinterrupt */
  60. Imbl = 0x01, /* Incoming Mailbox Loaded */
  61. Mbor = 0x02, /* Mailbox Out Ready */
  62. Cmdc = 0x04, /* Command Complete */
  63. Rsts = 0x08, /* SCSI Reset State */
  64. Intv = 0x80, /* Interrupt Valid */
  65. };
  66. typedef struct Mbox24 Mbox24;
  67. struct Mbox24 {
  68. uchar code; /* action/completion code */
  69. uchar ccb[3]; /* CCB pointer (MSB, ..., LSB) */
  70. };
  71. typedef struct Mbox32 Mbox32;
  72. struct Mbox32 {
  73. uchar ccb[4]; /* CCB pointer (LSB, ..., MSB) */
  74. uchar btstat; /* BT-7[45]7[SD] status */
  75. uchar sdstat; /* SCSI device status */
  76. uchar pad;
  77. uchar code; /* action/completion code */
  78. };
  79. enum { /* mailbox commands */
  80. Mbfree = 0x00, /* Mailbox not in use */
  81. Mbostart = 0x01, /* Start a mailbox command */
  82. Mboabort = 0x02, /* Abort a mailbox command */
  83. Mbiok = 0x01, /* CCB completed without error */
  84. Mbiabort = 0x02, /* CCB aborted at request of host */
  85. Mbinx = 0x03, /* Aborted CCB not found */
  86. Mbierror = 0x04, /* CCB completed with error */
  87. };
  88. typedef struct Ccb24 Ccb24;
  89. typedef struct Ccb32 Ccb32;
  90. typedef union Ccb Ccb;
  91. typedef struct Ccb24 {
  92. uchar opcode; /* Operation code */
  93. uchar datadir; /* Data direction control */
  94. uchar cdblen; /* Length of CDB */
  95. uchar senselen; /* Length of sense area */
  96. uchar datalen[3]; /* Data length (MSB, ..., LSB) */
  97. uchar dataptr[3]; /* Data pointer (MSB, ..., LSB) */
  98. uchar linkptr[3]; /* Link pointer (MSB, ..., LSB) */
  99. uchar linkid; /* command linking identifier */
  100. uchar btstat; /* BT-* adapter status */
  101. uchar sdstat; /* SCSI device status */
  102. uchar reserved[2]; /* */
  103. uchar cs[12+0xFF]; /* Command descriptor block + Sense */
  104. void* data; /* buffer if address > 24-bits */
  105. Rendez;
  106. int done; /* command completed */
  107. Ccb* ccb; /* link on free list */
  108. } Ccb24;
  109. typedef struct Ccb32 {
  110. uchar opcode; /* Operation code */
  111. uchar datadir; /* Data direction control */
  112. uchar cdblen; /* Length of CDB */
  113. uchar senselen; /* Length of sense area */
  114. uchar datalen[4]; /* Data length (LSB, ..., MSB) */
  115. uchar dataptr[4]; /* Data pointer (LSB, ..., MSB) */
  116. uchar reserved[2];
  117. uchar btstat; /* BT-* adapter status */
  118. uchar sdstat; /* SCSI device status */
  119. uchar targetid; /* Target ID */
  120. uchar luntag; /* LUN & tag */
  121. uchar cdb[12]; /* Command descriptor block */
  122. uchar ccbctl; /* CCB control */
  123. uchar linkid; /* command linking identifier */
  124. uchar linkptr[4]; /* Link pointer (LSB, ..., MSB) */
  125. uchar senseptr[4]; /* Sense pointer (LSB, ..., MSB) */
  126. uchar sense[0xFF]; /* Sense bytes */
  127. Rendez;
  128. int done; /* command completed */
  129. Ccb* ccb; /* link on free list */
  130. } Ccb32;
  131. typedef union Ccb {
  132. Ccb24;
  133. Ccb32;
  134. } Ccb;
  135. enum { /* opcode */
  136. OInitiator = 0x00, /* initiator CCB */
  137. Ordl = 0x03, /* initiator CCB with
  138. * residual data length returned
  139. */
  140. };
  141. enum { /* datadir */
  142. CCBdatain = 0x08, /* inbound, length is checked */
  143. CCBdataout = 0x10, /* outbound, length is checked */
  144. };
  145. enum { /* btstat */
  146. Eok = 0x00, /* normal completion with no errors */
  147. };
  148. enum { /* luntag */
  149. TagEnable = 0x20, /* Tag enable */
  150. SQTag = 0x00, /* Simple Queue Tag */
  151. HQTag = 0x40, /* Head of Queue Tag */
  152. OQTag = 0x80, /* Ordered Queue Tag */
  153. };
  154. enum { /* CCB control */
  155. NoDisc = 0x08, /* No disconnect */
  156. NoUnd = 0x10, /* No underrrun error report */
  157. NoData = 0x20, /* No data transfer */
  158. NoStat = 0x40, /* No CCB status if zero */
  159. NoIntr = 0x80, /* No Interrupts */
  160. };
  161. typedef struct Ctlr Ctlr;
  162. struct Ctlr {
  163. int port; /* I/O port */
  164. int id; /* adapter SCSI id */
  165. int bus; /* 24 or 32 -bit */
  166. int irq;
  167. int wide;
  168. Pcidev* pcidev;
  169. SDev* sdev;
  170. int spurious;
  171. Lock issuelock;
  172. Lock ccblock;
  173. QLock ccbq;
  174. Rendez ccbr;
  175. Lock mboxlock;
  176. void* mb; /* mailbox out + mailbox in */
  177. int mbox; /* current mailbox out index into mb */
  178. int mbix; /* current mailbox in index into mb */
  179. Lock cachelock;
  180. Ccb* ccb; /* list of free Ccb's */
  181. Ccb** cache; /* last completed Ccb */
  182. };
  183. /*
  184. * The number of mailboxes should be a multiple of 8 (4 for Mbox32)
  185. * to ensure the boundary between the out and in mailboxes doesn't
  186. * straddle a cache-line boundary.
  187. * The number of Ccb's should be less than the number of mailboxes to
  188. * ensure no queueing is necessary on mailbox allocation.
  189. */
  190. enum {
  191. NMbox = 8*8, /* number of Mbox's */
  192. NCcb = NMbox-1, /* number of Ccb's */
  193. };
  194. #define PADDR24(a, n) ((PADDR(a)+(n)) <= (1<<24))
  195. static void
  196. ccbfree(Ctlr* ctlr, Ccb* ccb)
  197. {
  198. lock(&ctlr->ccblock);
  199. if(ctlr->bus == 24)
  200. ((Ccb24*)ccb)->ccb = ctlr->ccb;
  201. else
  202. ((Ccb32*)ccb)->ccb = ctlr->ccb;
  203. if(ctlr->ccb == nil)
  204. wakeup(&ctlr->ccbr);
  205. ctlr->ccb = ccb;
  206. unlock(&ctlr->ccblock);
  207. }
  208. static int
  209. ccbavailable(void* a)
  210. {
  211. return ((Ctlr*)a)->ccb != nil;
  212. }
  213. static Ccb*
  214. ccballoc(Ctlr* ctlr)
  215. {
  216. Ccb *ccb;
  217. for(;;){
  218. lock(&ctlr->ccblock);
  219. if((ccb = ctlr->ccb) != nil){
  220. if(ctlr->bus == 24)
  221. ctlr->ccb = ((Ccb24*)ccb)->ccb;
  222. else
  223. ctlr->ccb = ((Ccb32*)ccb)->ccb;
  224. unlock(&ctlr->ccblock);
  225. break;
  226. }
  227. unlock(&ctlr->ccblock);
  228. qlock(&ctlr->ccbq);
  229. if(waserror()){
  230. qunlock(&ctlr->ccbq);
  231. continue;
  232. }
  233. sleep(&ctlr->ccbr, ccbavailable, ctlr);
  234. qunlock(&ctlr->ccbq);
  235. poperror();
  236. }
  237. return ccb;
  238. }
  239. static int
  240. done24(void* arg)
  241. {
  242. return ((Ccb24*)arg)->done;
  243. }
  244. static int
  245. mylex24rio(SDreq* r)
  246. {
  247. ulong p;
  248. Ctlr *ctlr;
  249. Ccb24 *ccb;
  250. Mbox24 *mb;
  251. uchar *data, lun, *sense;
  252. int d, n, btstat, sdstat, target;
  253. ctlr = r->unit->dev->ctlr;
  254. target = r->unit->subno;
  255. lun = (r->cmd[1]>>5) & 0x07;
  256. /*
  257. * Ctlr->cache holds the last completed Ccb for this target if it
  258. * returned 'check condition'.
  259. * If this command is a request-sense and there is valid sense data
  260. * from the last completed Ccb, return it immediately.
  261. */
  262. lock(&ctlr->cachelock);
  263. if((ccb = ctlr->cache[target]) != nil){
  264. ctlr->cache[target] = nil;
  265. if(r->cmd[0] == 0x03
  266. && ccb->sdstat == SDcheck && lun == ((ccb->cs[1]>>5) & 0x07)){
  267. unlock(&ctlr->cachelock);
  268. if(r->dlen){
  269. sense = &ccb->cs[ccb->cdblen];
  270. n = 8+sense[7];
  271. if(n > r->dlen)
  272. n = r->dlen;
  273. memmove(r->data, sense, n);
  274. r->rlen = n;
  275. }
  276. ccbfree(ctlr, (Ccb*)ccb);
  277. return SDok;
  278. }
  279. }
  280. unlock(&ctlr->cachelock);
  281. if(ccb == nil)
  282. ccb = ccballoc(ctlr);
  283. /*
  284. * Check if the transfer is to memory above the 24-bit limit the
  285. * controller can address. If it is, try to allocate a temporary
  286. * buffer as a staging area.
  287. */
  288. n = r->dlen;
  289. if(n && !PADDR24(r->data, n)){
  290. data = mallocz(n, 0);
  291. if(data == nil || !PADDR24(data, n)){
  292. if(data != nil){
  293. free(data);
  294. ccb->data = nil;
  295. }
  296. ccbfree(ctlr, (Ccb*)ccb);
  297. return SDmalloc;
  298. }
  299. if(r->write)
  300. memmove(data, r->data, n);
  301. ccb->data = r->data;
  302. }
  303. else
  304. data = r->data;
  305. /*
  306. * Fill in the ccb.
  307. */
  308. ccb->opcode = Ordl;
  309. ccb->datadir = (target<<5)|lun;
  310. if(n == 0)
  311. ccb->datadir |= CCBdataout|CCBdatain;
  312. else if(!r->write)
  313. ccb->datadir |= CCBdatain;
  314. else
  315. ccb->datadir |= CCBdataout;
  316. ccb->cdblen = r->clen;
  317. ccb->senselen = 0xFF;
  318. ccb->datalen[0] = n>>16;
  319. ccb->datalen[1] = n>>8;
  320. ccb->datalen[2] = n;
  321. if(data == nil)
  322. p = 0;
  323. else
  324. p = PADDR(data);
  325. ccb->dataptr[0] = p>>16;
  326. ccb->dataptr[1] = p>>8;
  327. ccb->dataptr[2] = p;
  328. ccb->linkptr[0] = ccb->linkptr[1] = ccb->linkptr[2] = 0;
  329. ccb->linkid = 0;
  330. ccb->btstat = ccb->sdstat = 0;
  331. ccb->reserved[0] = ccb->reserved[1] = 0;
  332. memmove(ccb->cs, r->cmd, r->clen);
  333. /*
  334. * There's one more mbox than there there is
  335. * ccb so there is always one free.
  336. */
  337. lock(&ctlr->mboxlock);
  338. mb = ctlr->mb;
  339. mb += ctlr->mbox;
  340. p = PADDR(ccb);
  341. mb->ccb[0] = p>>16;
  342. mb->ccb[1] = p>>8;
  343. mb->ccb[2] = p;
  344. mb->code = Mbostart;
  345. ctlr->mbox++;
  346. if(ctlr->mbox >= NMbox)
  347. ctlr->mbox = 0;
  348. /*
  349. * This command does not require Hardy
  350. * and doesn't generate a Cmdc interrupt.
  351. */
  352. ccb->done = 0;
  353. outb(ctlr->port+Rcpr, Cstart);
  354. unlock(&ctlr->mboxlock);
  355. /*
  356. * Wait for the request to complete and return the status.
  357. * Since the buffer is not reference counted cannot return
  358. * until the DMA is done writing into the buffer so the caller
  359. * cannot free the buffer prematurely.
  360. */
  361. while(waserror())
  362. ;
  363. sleep(ccb, done24, ccb);
  364. poperror();
  365. /*
  366. * Save the status and patch up the number of
  367. * bytes actually transferred.
  368. * There's a firmware bug on some 956C controllers
  369. * which causes the return count from a successful
  370. * READ CAPACITY not be updated, so fix it here.
  371. */
  372. sdstat = ccb->sdstat;
  373. btstat = ccb->btstat;
  374. d = ccb->datalen[0]<<16;
  375. d |= ccb->datalen[1]<<8;
  376. d |= ccb->datalen[2];
  377. if(ccb->cs[0] == 0x25 && sdstat == SDok)
  378. d = 0;
  379. n -= d;
  380. r->rlen = n;
  381. /*
  382. * Tidy things up if a staging area was used for the data,
  383. */
  384. if(ccb->data != nil){
  385. if(sdstat == SDok && btstat == 0 && !r->write)
  386. memmove(ccb->data, data, n);
  387. free(data);
  388. ccb->data = nil;
  389. }
  390. /*
  391. * If there was a check-condition, save the
  392. * ccb for a possible request-sense command.
  393. */
  394. if(sdstat == SDcheck){
  395. if(r->flags & SDnosense){
  396. lock(&ctlr->cachelock);
  397. if(ctlr->cache[target])
  398. ccbfree(ctlr, ctlr->cache[target]);
  399. ctlr->cache[target] = (Ccb*)ccb;
  400. unlock(&ctlr->cachelock);
  401. return SDcheck;
  402. }
  403. sense = &ccb->cs[ccb->cdblen];
  404. n = 8+sense[7];
  405. if(n > sizeof(r->sense)-1)
  406. n = sizeof(r->sense)-1;
  407. memmove(r->sense, sense, n);
  408. r->flags |= SDvalidsense;
  409. }
  410. ccbfree(ctlr, (Ccb*)ccb);
  411. if(btstat){
  412. if(btstat == 0x11)
  413. return SDtimeout;
  414. return SDeio;
  415. }
  416. return sdstat;
  417. }
  418. static void
  419. mylex24interrupt(Ureg*, void* arg)
  420. {
  421. ulong pa;
  422. Ctlr *ctlr;
  423. Ccb24 *ccb;
  424. Mbox24 *mb, *mbox;
  425. int port, rinterrupt, rstatus;
  426. ctlr = arg;
  427. port = ctlr->port;
  428. /*
  429. * Save and clear the interrupt(s). The only
  430. * interrupts expected are Cmdc, which is ignored,
  431. * and Imbl which means something completed.
  432. * There's one spurious interrupt left over from
  433. * initialisation, ignore it.
  434. */
  435. rinterrupt = inb(port+Rinterrupt);
  436. rstatus = inb(port+Rstatus);
  437. outb(port+Rcontrol, Rint);
  438. if((rinterrupt & ~(Cmdc|Imbl)) != Intv && ctlr->spurious++)
  439. print("%s: interrupt 0x%2.2ux\n",
  440. ctlr->sdev->name, rinterrupt);
  441. if((rinterrupt & Cmdc) && (rstatus & Cmdinv))
  442. print("%s: command invalid\n", ctlr->sdev->name);
  443. /*
  444. * Look for something in the mail.
  445. * If there is, save the status, free the mailbox
  446. * and wakeup whoever.
  447. */
  448. mb = ctlr->mb;
  449. for(mbox = &mb[ctlr->mbix]; mbox->code; mbox = &mb[ctlr->mbix]){
  450. pa = (mbox->ccb[0]<<16)|(mbox->ccb[1]<<8)|mbox->ccb[2];
  451. ccb = BPA2K(pa, BUSUNKNOWN);
  452. mbox->code = 0;
  453. ccb->done = 1;
  454. wakeup(ccb);
  455. ctlr->mbix++;
  456. if(ctlr->mbix >= NMbox+NMbox)
  457. ctlr->mbix = NMbox;
  458. }
  459. }
  460. static int
  461. done32(void* arg)
  462. {
  463. return ((Ccb32*)arg)->done;
  464. }
  465. static int
  466. mylex32rio(SDreq* r)
  467. {
  468. ulong p;
  469. uchar lun;
  470. Ctlr *ctlr;
  471. Ccb32 *ccb;
  472. Mbox32 *mb;
  473. int d, n, btstat, sdstat, target;
  474. ctlr = r->unit->dev->ctlr;
  475. target = r->unit->subno;
  476. lun = (r->cmd[1]>>5) & 0x07;
  477. /*
  478. * Ctlr->cache holds the last completed Ccb for this target if it
  479. * returned 'check condition'.
  480. * If this command is a request-sense and there is valid sense data
  481. * from the last completed Ccb, return it immediately.
  482. */
  483. lock(&ctlr->cachelock);
  484. if((ccb = ctlr->cache[target]) != nil){
  485. ctlr->cache[target] = nil;
  486. if(r->cmd[0] == 0x03
  487. && ccb->sdstat == SDcheck && lun == (ccb->luntag & 0x07)){
  488. unlock(&ctlr->cachelock);
  489. if(r->dlen){
  490. n = 8+ccb->sense[7];
  491. if(n > r->dlen)
  492. n = r->dlen;
  493. memmove(r->data, ccb->sense, n);
  494. r->rlen = n;
  495. }
  496. ccbfree(ctlr, (Ccb*)ccb);
  497. return SDok;
  498. }
  499. }
  500. unlock(&ctlr->cachelock);
  501. if(ccb == nil)
  502. ccb = ccballoc(ctlr);
  503. /*
  504. * Fill in the ccb.
  505. */
  506. ccb->opcode = Ordl;
  507. n = r->dlen;
  508. if(n == 0)
  509. ccb->datadir = CCBdataout|CCBdatain;
  510. else if(!r->write)
  511. ccb->datadir = CCBdatain;
  512. else
  513. ccb->datadir = CCBdataout;
  514. ccb->cdblen = r->clen;
  515. ccb->datalen[0] = n;
  516. ccb->datalen[1] = n>>8;
  517. ccb->datalen[2] = n>>16;
  518. ccb->datalen[3] = n>>24;
  519. if(r->data == nil)
  520. p = 0;
  521. else
  522. p = PADDR(r->data);
  523. ccb->dataptr[0] = p;
  524. ccb->dataptr[1] = p>>8;
  525. ccb->dataptr[2] = p>>16;
  526. ccb->dataptr[3] = p>>24;
  527. ccb->targetid = target;
  528. ccb->luntag = lun;
  529. if(r->unit->inquiry[7] & 0x02)
  530. if(ctlr->wide)
  531. ccb->datadir |= SQTag|TagEnable;
  532. else
  533. ccb->luntag |= SQTag|TagEnable;
  534. memmove(ccb->cdb, r->cmd, r->clen);
  535. ccb->btstat = ccb->sdstat = 0;
  536. ccb->ccbctl = 0;
  537. /*
  538. * There's one more mbox than there there is
  539. * ccb so there is always one free.
  540. */
  541. lock(&ctlr->mboxlock);
  542. mb = ctlr->mb;
  543. mb += ctlr->mbox;
  544. p = PADDR(ccb);
  545. mb->ccb[0] = p;
  546. mb->ccb[1] = p>>8;
  547. mb->ccb[2] = p>>16;
  548. mb->ccb[3] = p>>24;
  549. mb->code = Mbostart;
  550. ctlr->mbox++;
  551. if(ctlr->mbox >= NMbox)
  552. ctlr->mbox = 0;
  553. /*
  554. * This command does not require Hardy
  555. * and doesn't generate a Cmdc interrupt.
  556. */
  557. ccb->done = 0;
  558. outb(ctlr->port+Rcpr, Cstart);
  559. unlock(&ctlr->mboxlock);
  560. /*
  561. * Wait for the request to complete and return the status.
  562. * Since the buffer is not reference counted cannot return
  563. * until the DMA is done writing into the buffer so the caller
  564. * cannot free the buffer prematurely.
  565. */
  566. while(waserror())
  567. ;
  568. sleep(ccb, done32, ccb);
  569. poperror();
  570. /*
  571. * Save the status and patch up the number of
  572. * bytes actually transferred.
  573. * There's a firmware bug on some 956C controllers
  574. * which causes the return count from a successful
  575. * READ CAPACITY not to be updated, so fix it here.
  576. */
  577. sdstat = ccb->sdstat;
  578. btstat = ccb->btstat;
  579. d = ccb->datalen[0];
  580. d |= (ccb->datalen[1]<<8);
  581. d |= (ccb->datalen[2]<<16);
  582. d |= (ccb->datalen[3]<<24);
  583. if(ccb->cdb[0] == 0x25 && sdstat == SDok)
  584. d = 0;
  585. n -= d;
  586. r->rlen = n;
  587. /*
  588. * If there was a check-condition, save the
  589. * ccb for a possible request-sense command.
  590. */
  591. if(sdstat == SDcheck){
  592. if(r->flags & SDnosense){
  593. lock(&ctlr->cachelock);
  594. if(ctlr->cache[target])
  595. ccbfree(ctlr, ctlr->cache[target]);
  596. ctlr->cache[target] = (Ccb*)ccb;
  597. unlock(&ctlr->cachelock);
  598. return SDcheck;
  599. }
  600. n = 8+ccb->sense[7];
  601. if(n > sizeof(r->sense)-1)
  602. n = sizeof(r->sense)-1;
  603. memmove(r->sense, ccb->sense, n);
  604. r->flags |= SDvalidsense;
  605. }
  606. ccbfree(ctlr, (Ccb*)ccb);
  607. if(btstat){
  608. if(btstat == 0x11)
  609. return SDtimeout;
  610. return SDeio;
  611. }
  612. return sdstat;
  613. }
  614. static void
  615. mylex32interrupt(Ureg*, void* arg)
  616. {
  617. ulong pa;
  618. Ctlr *ctlr;
  619. Ccb32 *ccb;
  620. Mbox32 *mb, *mbox;
  621. int port, rinterrupt, rstatus;
  622. ctlr = arg;
  623. port = ctlr->port;
  624. /*
  625. * Save and clear the interrupt(s). The only
  626. * interrupts expected are Cmdc, which is ignored,
  627. * and Imbl which means something completed.
  628. * There's one spurious interrupt left over from
  629. * initialisation, ignore it.
  630. * In order to share PCI IRQs, just ignore spurious interrupts.
  631. */
  632. rinterrupt = inb(port+Rinterrupt);
  633. rstatus = inb(port+Rstatus);
  634. outb(port+Rcontrol, Rint);
  635. if(0 && (rinterrupt & ~(Cmdc|Imbl)) != Intv && ctlr->spurious++)
  636. print("%s: interrupt 0x%2.2ux\n",
  637. ctlr->sdev->name, rinterrupt);
  638. if((rinterrupt & Cmdc) && (rstatus & Cmdinv))
  639. print("%s: command invalid\n", ctlr->sdev->name);
  640. /*
  641. * Look for something in the mail.
  642. * If there is, free the mailbox and wakeup whoever.
  643. */
  644. mb = ctlr->mb;
  645. for(mbox = &mb[ctlr->mbix]; mbox->code; mbox = &mb[ctlr->mbix]){
  646. pa = (mbox->ccb[3]<<24)
  647. |(mbox->ccb[2]<<16)
  648. |(mbox->ccb[1]<<8)
  649. |mbox->ccb[0];
  650. if(ctlr->pcidev)
  651. ccb = BPA2K(pa, ctlr->pcidev->tbdf);
  652. else
  653. ccb = BPA2K(pa, BUSUNKNOWN);
  654. mbox->code = 0;
  655. ccb->done = 1;
  656. wakeup(ccb);
  657. ctlr->mbix++;
  658. if(ctlr->mbix >= NMbox+NMbox)
  659. ctlr->mbix = NMbox;
  660. }
  661. }
  662. static int
  663. mylexrio(SDreq* r)
  664. {
  665. int subno;
  666. Ctlr *ctlr;
  667. subno = r->unit->subno;
  668. ctlr = r->unit->dev->ctlr;
  669. if(subno == ctlr->id || (!ctlr->wide && subno >= 8))
  670. r->status = SDtimeout;
  671. else if(ctlr->bus == 24)
  672. r->status = mylex24rio(r);
  673. else
  674. r->status = mylex32rio(r);
  675. return r->status;
  676. }
  677. /*
  678. * Issue a command to a controller. The command and its length is
  679. * contained in cmd and cmdlen. If any data is to be
  680. * returned, datalen should be non-zero, and the returned data
  681. * will be placed in data.
  682. * If Cmdc is set, bail out, the invalid command will be handled
  683. * when the interrupt is processed.
  684. */
  685. static void
  686. issueio(int port, uchar* cmd, int cmdlen, uchar* data, int datalen)
  687. {
  688. int len;
  689. if(cmd[0] != Cstart && cmd[0] != Ceombri){
  690. while(!(inb(port+Rstatus) & Hardy))
  691. ;
  692. }
  693. outb(port+Rcpr, cmd[0]);
  694. len = 1;
  695. while(len < cmdlen){
  696. if(!(inb(port+Rstatus) & Cprbsy)){
  697. outb(port+Rcpr, cmd[len]);
  698. len++;
  699. }
  700. if(inb(port+Rinterrupt) & Cmdc)
  701. return;
  702. }
  703. if(datalen){
  704. len = 0;
  705. while(len < datalen){
  706. if(inb(port+Rstatus) & Dirrdy){
  707. data[len] = inb(port+Rdatain);
  708. len++;
  709. }
  710. if(inb(port+Rinterrupt) & Cmdc)
  711. return;
  712. }
  713. }
  714. }
  715. /*
  716. * Issue a command to a controller, wait for it to complete then
  717. * try to reset the interrupt. Should only be called at initialisation.
  718. */
  719. static int
  720. issue(Ctlr* ctlr, uchar* cmd, int cmdlen, uchar* data, int datalen)
  721. {
  722. int port;
  723. uchar rinterrupt, rstatus;
  724. static Lock mylexissuelock;
  725. port = ctlr->port;
  726. ilock(&ctlr->issuelock);
  727. issueio(port, cmd, cmdlen, data, datalen);
  728. while(!((rinterrupt = inb(port+Rinterrupt)) & Cmdc))
  729. ;
  730. rstatus = inb(port+Rstatus);
  731. outb(port+Rcontrol, Rint);
  732. iunlock(&ctlr->issuelock);
  733. if((rinterrupt & Cmdc) && (rstatus & Cmdinv))
  734. return 0;
  735. return 1;
  736. }
  737. static SDev*
  738. mylexprobe(int port, int irq)
  739. {
  740. SDev *sdev;
  741. Ctlr *ctlr;
  742. uchar cmd[6], data[256];
  743. int clen, dlen, timeo;
  744. if(ioalloc(port, 0x3, 0, "mylex") < 0)
  745. return nil;
  746. ctlr = nil;
  747. sdev = nil;
  748. /*
  749. * Attempt to hard-reset the board and reset
  750. * the SCSI bus. If the board state doesn't settle to
  751. * idle with mailbox initialisation required, either
  752. * it isn't a compatible board or it's broken.
  753. * If the controller has SCAM set this can take a while.
  754. */
  755. if(getconf("*noscsireset") != nil)
  756. outb(port+Rcontrol, Rhard);
  757. else
  758. outb(port+Rcontrol, Rhard|Rsbus);
  759. for(timeo = 0; timeo < 100; timeo++){
  760. if(inb(port+Rstatus) == (Inreq|Hardy))
  761. break;
  762. delay(100);
  763. }
  764. if(inb(port+Rstatus) != (Inreq|Hardy)){
  765. buggery:
  766. if(ctlr != nil)
  767. free(ctlr);
  768. if (sdev != nil)
  769. free(sdev);
  770. iofree(port);
  771. return nil;
  772. }
  773. if((ctlr = malloc(sizeof(Ctlr))) == nil)
  774. goto buggery;
  775. ctlr->port = port;
  776. ctlr->irq = irq;
  777. ctlr->bus = 24;
  778. ctlr->wide = 0;
  779. /*
  780. * Try to determine if this is a 32-bit MultiMaster controller
  781. * by attempting to obtain the extended inquiry information;
  782. * this command is not implemented on Adaptec 154xx
  783. * controllers. If successful, the first byte of the returned
  784. * data is the host adapter bus type, 'E' for 32-bit EISA,
  785. * PCI and VLB buses.
  786. */
  787. cmd[0] = Ciesi;
  788. cmd[1] = 14;
  789. clen = 2;
  790. dlen = 256;
  791. if(issue(ctlr, cmd, clen, data, dlen)){
  792. if(data[0] == 'E')
  793. ctlr->bus = 32;
  794. print("mylex ctlr @ port 0x%ux: 32-bit ", ctlr->port);
  795. ctlr->wide = data[0x0D] & 0x01;
  796. if (ctlr->wide)
  797. print("wide ");
  798. else
  799. print("narrow ");
  800. print("SCSI host adapter\n");
  801. }
  802. else{
  803. /*
  804. * Inconceivable though it may seem, a hard controller reset
  805. * is necessary here to clear out the command queue. Every
  806. * board seems to lock-up in a different way if you give an
  807. * invalid command and then try to clear out the
  808. * command/parameter and/or data-in register.
  809. * Soft reset doesn't do the job either. Fortunately no
  810. * serious initialisation has been done yet so there's nothing
  811. * to tidy up.
  812. */
  813. outb(port+Rcontrol, Rhard);
  814. for(timeo = 0; timeo < 100; timeo++){
  815. if(inb(port+Rstatus) == (Inreq|Hardy))
  816. break;
  817. delay(100);
  818. }
  819. if(inb(port+Rstatus) != (Inreq|Hardy))
  820. goto buggery;
  821. }
  822. /*
  823. * If the BIOS is enabled on the AHA-1542C/CF and BIOS options for
  824. * support of drives > 1Gb, dynamic scanning of the SCSI bus or more
  825. * than 2 drives under DOS 5.0 are enabled, the BIOS disables
  826. * accepting Cmbinit to protect against running with drivers which
  827. * don't support those options. In order to unlock the interface it
  828. * is necessary to read a lock-code using Cextbios and write it back
  829. * using Cmbienable; the lock-code is non-zero.
  830. */
  831. cmd[0] = Cinquiry;
  832. clen = 1;
  833. dlen = 4;
  834. if(issue(ctlr, cmd, clen, data, dlen) == 0)
  835. goto buggery;
  836. if(data[0] >= 0x43){
  837. cmd[0] = Cextbios;
  838. clen = 1;
  839. dlen = 2;
  840. if(issue(ctlr, cmd, clen, data, dlen) == 0)
  841. goto buggery;
  842. /*
  843. * Lock-code returned in data[1]. If it's non-zero write
  844. * it back along with bit 0 of byte 0 cleared to enable
  845. * mailbox initialisation.
  846. */
  847. if(data[1]){
  848. cmd[0] = Cmbienable;
  849. cmd[1] = 0;
  850. cmd[2] = data[1];
  851. clen = 3;
  852. if(issue(ctlr, cmd, clen, 0, 0) == 0)
  853. goto buggery;
  854. }
  855. }
  856. /*
  857. * Get the id, DMA and IRQ info from the board. This will
  858. * cause an interrupt which will hopefully not cause any
  859. * trouble because the interrupt number isn't known yet.
  860. * This is necessary as the DMA won't be set up if the
  861. * board has the BIOS disabled.
  862. *
  863. * If the IRQ is already known, this must be a 32-bit PCI
  864. * or EISA card, in which case the returned DMA and IRQ can
  865. * be ignored.
  866. */
  867. cmd[0] = Cinquire;
  868. clen = 1;
  869. dlen = 3;
  870. if(issue(ctlr, cmd, clen, data, dlen) == 0)
  871. goto buggery;
  872. ctlr->id = data[2] & 0x07;
  873. if(ctlr->irq < 0){
  874. switch(data[0]){ /* DMA Arbitration Priority */
  875. case 0x80: /* Channel 7 */
  876. outb(0xD6, 0xC3);
  877. outb(0xD4, 0x03);
  878. break;
  879. case 0x40: /* Channel 6 */
  880. outb(0xD6, 0xC2);
  881. outb(0xD4, 0x02);
  882. break;
  883. case 0x20: /* Channel 5 */
  884. outb(0xD6, 0xC1);
  885. outb(0xD4, 0x01);
  886. break;
  887. case 0x01: /* Channel 0 */
  888. outb(0x0B, 0xC0);
  889. outb(0x0A, 0x00);
  890. break;
  891. default:
  892. if(ctlr->bus == 24)
  893. goto buggery;
  894. break;
  895. }
  896. switch(data[1]){ /* Interrupt Channel */
  897. case 0x40:
  898. ctlr->irq = 15;
  899. break;
  900. case 0x20:
  901. ctlr->irq = 14;
  902. break;
  903. case 0x08:
  904. ctlr->irq = 12;
  905. break;
  906. case 0x04:
  907. ctlr->irq = 11;
  908. break;
  909. case 0x02:
  910. ctlr->irq = 10;
  911. break;
  912. case 0x01:
  913. ctlr->irq = 9;
  914. break;
  915. default:
  916. goto buggery;
  917. }
  918. }
  919. if((sdev = malloc(sizeof(SDev))) == nil)
  920. goto buggery;
  921. sdev->ifc = &sdmylexifc;
  922. sdev->ctlr = ctlr;
  923. sdev->idno = '0';
  924. ctlr->sdev = sdev;
  925. if(!ctlr->wide)
  926. sdev->nunit = 8;
  927. else
  928. sdev->nunit = 16;
  929. return sdev;
  930. }
  931. static int mylexport[8] = {
  932. 0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0x000, 0x000,
  933. };
  934. static SDev*
  935. mylexpnp(void)
  936. {
  937. Pcidev *p;
  938. Ctlr *ctlr;
  939. ISAConf isa;
  940. int cfg, ctlrno, i, x;
  941. SDev *sdev, *head, *tail;
  942. p = nil;
  943. head = tail = nil;
  944. while(p = pcimatch(p, 0x104B, 0)){
  945. if((sdev = mylexprobe(p->mem[0].bar & ~0x01, p->intl)) == nil)
  946. continue;
  947. ctlr = sdev->ctlr;
  948. ctlr->pcidev = p;
  949. if(head != nil)
  950. tail->next = sdev;
  951. else
  952. head = sdev;
  953. tail = sdev;
  954. }
  955. if(strncmp(KADDR(0xFFFD9), "EISA", 4) == 0){
  956. for(cfg = 0x1000; cfg < MaxEISA*0x1000; cfg += 0x1000){
  957. x = 0;
  958. for(i = 0; i < 4; i++)
  959. x |= inb(cfg+CfgEISA+i)<<(i*8);
  960. if(x != 0x0142B30A && x != 0x0242B30A)
  961. continue;
  962. x = inb(cfg+0xC8C);
  963. if((sdev = mylexprobe(mylexport[x & 0x07], -1)) == nil)
  964. continue;
  965. if(head != nil)
  966. tail->next = sdev;
  967. else
  968. head = sdev;
  969. tail = sdev;
  970. }
  971. }
  972. for(ctlrno = 0; ctlrno < 4; ctlrno++){
  973. memset(&isa, 0, sizeof(isa));
  974. if(!isaconfig("scsi", ctlrno, &isa))
  975. continue;
  976. if(strcmp(isa.type, "aha1542"))
  977. continue;
  978. if((sdev = mylexprobe(isa.port, -1)) == nil)
  979. continue;
  980. if(head != nil)
  981. tail->next = sdev;
  982. else
  983. head = sdev;
  984. tail = sdev;
  985. }
  986. return head;
  987. }
  988. static int
  989. mylex24enable(Ctlr* ctlr)
  990. {
  991. ulong p;
  992. Ccb24 *ccb, *ccbp;
  993. uchar cmd[6], *v;
  994. int len;
  995. len = (sizeof(Mbox24)*NMbox*2)+(sizeof(Ccb24)*NCcb);
  996. v = xspanalloc(len, 32, 0);
  997. if(!PADDR24(ctlr, sizeof(Ctlr)) || !PADDR24(v, len))
  998. return 0;
  999. ctlr->mb = v;
  1000. v += sizeof(Mbox24)*NMbox*2;
  1001. ccb = (Ccb24*)v;
  1002. for(ccbp = ccb; ccbp < &ccb[NCcb]; ccbp++){
  1003. ccbp->ccb = ctlr->ccb;
  1004. ctlr->ccb = (Ccb*)ccbp;
  1005. }
  1006. /*
  1007. * Initialise the software controller and
  1008. * set the board scanning the mailboxes.
  1009. */
  1010. ctlr->mbix = NMbox;
  1011. cmd[0] = Cinitialise;
  1012. cmd[1] = NMbox;
  1013. p = K2BPA(ctlr->mb, BUSUNKNOWN);
  1014. cmd[2] = p>>16;
  1015. cmd[3] = p>>8;
  1016. cmd[4] = p;
  1017. return issue(ctlr, cmd, 5, 0, 0);
  1018. }
  1019. static int
  1020. mylex32enable(Ctlr* ctlr)
  1021. {
  1022. ulong p;
  1023. Ccb32 *ccb, *ccbp;
  1024. uchar cmd[6], *v;
  1025. v = xspanalloc((sizeof(Mbox32)*NMbox*2)+(sizeof(Ccb32)*NCcb), 32, 0);
  1026. ctlr->mb = v;
  1027. v += sizeof(Mbox32)*NMbox*2;
  1028. ccb = (Ccb32*)v;
  1029. for(ccbp = ccb; ccbp < &ccb[NCcb]; ccbp++){
  1030. /*
  1031. * Fill in some stuff that doesn't change.
  1032. */
  1033. ccbp->senselen = sizeof(ccbp->sense);
  1034. p = PADDR(ccbp->sense);
  1035. ccbp->senseptr[0] = p;
  1036. ccbp->senseptr[1] = p>>8;
  1037. ccbp->senseptr[2] = p>>16;
  1038. ccbp->senseptr[3] = p>>24;
  1039. ccbp->ccb = ctlr->ccb;
  1040. ctlr->ccb = (Ccb*)ccbp;
  1041. }
  1042. /*
  1043. * Attempt wide mode setup.
  1044. */
  1045. if(ctlr->wide){
  1046. cmd[0] = Cwide;
  1047. cmd[1] = 1;
  1048. if(!issue(ctlr, cmd, 2, 0, 0)) {
  1049. ctlr->wide = 0;
  1050. print(
  1051. "mylex32enable: ctlr @ port 0x%ux: scsi wide-mode setup failed on wide host adapter",
  1052. ctlr->port);
  1053. }
  1054. }
  1055. /*
  1056. * Initialise the software controller and
  1057. * set the board scanning the mailboxes.
  1058. */
  1059. ctlr->mbix = NMbox;
  1060. cmd[0] = Ciem;
  1061. cmd[1] = NMbox;
  1062. if(ctlr->pcidev)
  1063. p = K2BPA(ctlr->mb, ctlr->tbdf);
  1064. else
  1065. p = K2BPA(ctlr->mb, BUSUNKNOWN);
  1066. cmd[2] = p;
  1067. cmd[3] = p>>8;
  1068. cmd[4] = p>>16;
  1069. cmd[5] = p>>24;
  1070. return issue(ctlr, cmd, 6, 0, 0);
  1071. }
  1072. static int
  1073. mylexenable(SDev* sdev)
  1074. {
  1075. int tbdf;
  1076. Ctlr *ctlr;
  1077. void (*interrupt)(Ureg*, void*);
  1078. char name[32];
  1079. ctlr = sdev->ctlr;
  1080. if(ctlr->cache == nil){
  1081. if((ctlr->cache = malloc(sdev->nunit*sizeof(Ccb*))) == nil)
  1082. return 0;
  1083. }
  1084. tbdf = BUSUNKNOWN;
  1085. if(ctlr->bus == 32){
  1086. if(ctlr->pcidev){
  1087. tbdf = ctlr->pcidev->tbdf;
  1088. pcisetbme(ctlr->pcidev);
  1089. }
  1090. if(!mylex32enable(ctlr))
  1091. return 0;
  1092. interrupt = mylex32interrupt;
  1093. }
  1094. else if(mylex24enable(ctlr))
  1095. interrupt = mylex24interrupt;
  1096. else
  1097. return 0;
  1098. snprint(name, sizeof(name), "sd%c (%s)", sdev->idno, sdev->ifc->name);
  1099. intrenable(ctlr->irq, interrupt, ctlr, tbdf, name);
  1100. return 1;
  1101. }
  1102. SDifc sdmylexifc = {
  1103. "mylex", /* name */
  1104. mylexpnp, /* pnp */
  1105. nil, /* legacy */
  1106. mylexenable, /* enable */
  1107. nil, /* disable */
  1108. scsiverify, /* verify */
  1109. scsionline, /* online */
  1110. mylexrio, /* rio */
  1111. nil, /* rctl */
  1112. nil, /* wctl */
  1113. scsibio, /* bio */
  1114. nil, /* probe */
  1115. nil, /* clear */
  1116. nil, /* rtopctl */
  1117. nil, /* wtopctl */
  1118. };