uarti8250.c 14 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "../port/error.h"
  8. /*
  9. * 8250 UART and compatibles.
  10. */
  11. enum {
  12. Uart0 = 0x3F8, /* COM1 */
  13. Uart0IRQ = 4,
  14. Uart1 = 0x2F8, /* COM2 */
  15. Uart1IRQ = 3,
  16. UartFREQ = 1843200,
  17. };
  18. enum { /* I/O ports */
  19. Rbr = 0, /* Receiver Buffer (RO) */
  20. Thr = 0, /* Transmitter Holding (WO) */
  21. Ier = 1, /* Interrupt Enable */
  22. Iir = 2, /* Interrupt Identification (RO) */
  23. Fcr = 2, /* FIFO Control (WO) */
  24. Lcr = 3, /* Line Control */
  25. Mcr = 4, /* Modem Control */
  26. Lsr = 5, /* Line Status */
  27. Msr = 6, /* Modem Status */
  28. Scr = 7, /* Scratch Pad */
  29. Dll = 0, /* Divisor Latch LSB */
  30. Dlm = 1, /* Divisor Latch MSB */
  31. };
  32. enum { /* Ier */
  33. Erda = 0x01, /* Enable Received Data Available */
  34. Ethre = 0x02, /* Enable Thr Empty */
  35. Erls = 0x04, /* Enable Receiver Line Status */
  36. Ems = 0x08, /* Enable Modem Status */
  37. };
  38. enum { /* Iir */
  39. Ims = 0x00, /* Ms interrupt */
  40. Ip = 0x01, /* Interrupt Pending (not) */
  41. Ithre = 0x02, /* Thr Empty */
  42. Irda = 0x04, /* Received Data Available */
  43. Irls = 0x06, /* Receiver Line Status */
  44. Ictoi = 0x0C, /* Character Time-out Indication */
  45. IirMASK = 0x3F,
  46. Ifena = 0xC0, /* FIFOs enabled */
  47. };
  48. enum { /* Fcr */
  49. FIFOena = 0x01, /* FIFO enable */
  50. FIFOrclr = 0x02, /* clear Rx FIFO */
  51. FIFOtclr = 0x04, /* clear Tx FIFO */
  52. FIFO1 = 0x00, /* Rx FIFO trigger level 1 byte */
  53. FIFO4 = 0x40, /* 4 bytes */
  54. FIFO8 = 0x80, /* 8 bytes */
  55. FIFO14 = 0xC0, /* 14 bytes */
  56. };
  57. enum { /* Lcr */
  58. Wls5 = 0x00, /* Word Length Select 5 bits/byte */
  59. Wls6 = 0x01, /* 6 bits/byte */
  60. Wls7 = 0x02, /* 7 bits/byte */
  61. Wls8 = 0x03, /* 8 bits/byte */
  62. WlsMASK = 0x03,
  63. Stb = 0x04, /* 2 stop bits */
  64. Pen = 0x08, /* Parity Enable */
  65. Eps = 0x10, /* Even Parity Select */
  66. Stp = 0x20, /* Stick Parity */
  67. Brk = 0x40, /* Break */
  68. Dlab = 0x80, /* Divisor Latch Access Bit */
  69. };
  70. enum { /* Mcr */
  71. Dtr = 0x01, /* Data Terminal Ready */
  72. Rts = 0x02, /* Ready To Send */
  73. Out1 = 0x04, /* no longer in use */
  74. Ie = 0x08, /* IRQ Enable */
  75. Dm = 0x10, /* Diagnostic Mode loopback */
  76. };
  77. enum { /* Lsr */
  78. Dr = 0x01, /* Data Ready */
  79. Oe = 0x02, /* Overrun Error */
  80. Pe = 0x04, /* Parity Error */
  81. Fe = 0x08, /* Framing Error */
  82. Bi = 0x10, /* Break Interrupt */
  83. Thre = 0x20, /* Thr Empty */
  84. Temt = 0x40, /* Tramsmitter Empty */
  85. FIFOerr = 0x80, /* error in receiver FIFO */
  86. };
  87. enum { /* Msr */
  88. Dcts = 0x01, /* Delta Cts */
  89. Ddsr = 0x02, /* Delta Dsr */
  90. Teri = 0x04, /* Trailing Edge of Ri */
  91. Ddcd = 0x08, /* Delta Dcd */
  92. Cts = 0x10, /* Clear To Send */
  93. Dsr = 0x20, /* Data Set Ready */
  94. Ri = 0x40, /* Ring Indicator */
  95. Dcd = 0x80, /* Data Set Ready */
  96. };
  97. typedef struct Ctlr {
  98. int io;
  99. int irq;
  100. int tbdf;
  101. int iena;
  102. uchar sticky[8];
  103. Lock;
  104. int hasfifo;
  105. int checkfifo;
  106. int fena;
  107. } Ctlr;
  108. extern PhysUart i8250physuart;
  109. static Ctlr i8250ctlr[2] = {
  110. { .io = Uart0,
  111. .irq = Uart0IRQ,
  112. .tbdf = BUSUNKNOWN, },
  113. { .io = Uart1,
  114. .irq = Uart1IRQ,
  115. .tbdf = BUSUNKNOWN, },
  116. };
  117. static Uart i8250uart[2] = {
  118. { .regs = &i8250ctlr[0],
  119. .name = "COM1",
  120. .freq = UartFREQ,
  121. .phys = &i8250physuart,
  122. .special= 0,
  123. .next = &i8250uart[1], },
  124. { .regs = &i8250ctlr[1],
  125. .name = "COM2",
  126. .freq = UartFREQ,
  127. .phys = &i8250physuart,
  128. .special= 0,
  129. .next = nil, },
  130. };
  131. #define csr8r(c, r) inb((c)->io+(r))
  132. #define csr8w(c, r, v) outb((c)->io+(r), (c)->sticky[(r)]|(v))
  133. static long
  134. i8250status(Uart* uart, void* buf, long n, long offset)
  135. {
  136. char *p;
  137. Ctlr *ctlr;
  138. uchar ier, lcr, mcr, msr;
  139. ctlr = uart->regs;
  140. p = malloc(READSTR);
  141. mcr = ctlr->sticky[Mcr];
  142. msr = csr8r(ctlr, Msr);
  143. ier = ctlr->sticky[Ier];
  144. lcr = ctlr->sticky[Lcr];
  145. snprint(p, READSTR,
  146. "b%d c%d d%d e%d l%d m%d p%c r%d s%d i%d\n"
  147. "dev(%d) type(%d) framing(%d) overruns(%d) "
  148. "berr(%d) serr(%d)%s%s%s%s\n",
  149. uart->baud,
  150. uart->hup_dcd,
  151. (msr & Dsr) != 0,
  152. uart->hup_dsr,
  153. (lcr & WlsMASK) + 5,
  154. (ier & Ems) != 0,
  155. (lcr & Pen) ? ((lcr & Eps) ? 'e': 'o'): 'n',
  156. (mcr & Rts) != 0,
  157. (lcr & Stb) ? 2: 1,
  158. ctlr->fena,
  159. uart->dev,
  160. uart->type,
  161. uart->ferr,
  162. uart->oerr,
  163. uart->berr,
  164. uart->serr,
  165. (msr & Cts) ? " cts": "",
  166. (msr & Dsr) ? " dsr": "",
  167. (msr & Dcd) ? " dcd": "",
  168. (msr & Ri) ? " ring": ""
  169. );
  170. n = readstr(offset, buf, n, p);
  171. free(p);
  172. return n;
  173. }
  174. static void
  175. i8250fifo(Uart* uart, int level)
  176. {
  177. Ctlr *ctlr;
  178. ctlr = uart->regs;
  179. if(ctlr->hasfifo == 0)
  180. return;
  181. /*
  182. * Changing the FIFOena bit in Fcr flushes data
  183. * from both receive and transmit FIFOs; there's
  184. * no easy way to guarantee not losing data on
  185. * the receive side, but it's possible to wait until
  186. * the transmitter is really empty.
  187. */
  188. ilock(ctlr);
  189. while(!(csr8r(ctlr, Lsr) & Temt))
  190. ;
  191. /*
  192. * Set the trigger level, default is the max.
  193. * value.
  194. * Some UARTs require FIFOena to be set before
  195. * other bits can take effect, so set it twice.
  196. */
  197. ctlr->fena = level;
  198. switch(level){
  199. case 0:
  200. break;
  201. case 1:
  202. level = FIFO1|FIFOena;
  203. break;
  204. case 4:
  205. level = FIFO4|FIFOena;
  206. break;
  207. case 8:
  208. level = FIFO8|FIFOena;
  209. break;
  210. default:
  211. level = FIFO14|FIFOena;
  212. break;
  213. }
  214. csr8w(ctlr, Fcr, level);
  215. csr8w(ctlr, Fcr, level);
  216. iunlock(ctlr);
  217. }
  218. static void
  219. i8250dtr(Uart* uart, int on)
  220. {
  221. Ctlr *ctlr;
  222. /*
  223. * Toggle DTR.
  224. */
  225. ctlr = uart->regs;
  226. if(on)
  227. ctlr->sticky[Mcr] |= Dtr;
  228. else
  229. ctlr->sticky[Mcr] &= ~Dtr;
  230. csr8w(ctlr, Mcr, 0);
  231. }
  232. static void
  233. i8250rts(Uart* uart, int on)
  234. {
  235. Ctlr *ctlr;
  236. /*
  237. * Toggle RTS.
  238. */
  239. ctlr = uart->regs;
  240. if(on)
  241. ctlr->sticky[Mcr] |= Rts;
  242. else
  243. ctlr->sticky[Mcr] &= ~Rts;
  244. csr8w(ctlr, Mcr, 0);
  245. }
  246. static void
  247. i8250modemctl(Uart* uart, int on)
  248. {
  249. Ctlr *ctlr;
  250. ctlr = uart->regs;
  251. ilock(&uart->tlock);
  252. if(on){
  253. ctlr->sticky[Ier] |= Ems;
  254. csr8w(ctlr, Ier, ctlr->sticky[Ier]);
  255. uart->modem = 1;
  256. uart->cts = csr8r(ctlr, Msr) & Cts;
  257. }
  258. else{
  259. ctlr->sticky[Ier] &= ~Ems;
  260. csr8w(ctlr, Ier, ctlr->sticky[Ier]);
  261. uart->modem = 0;
  262. uart->cts = 1;
  263. }
  264. iunlock(&uart->tlock);
  265. /* modem needs fifo */
  266. (*uart->phys->fifo)(uart, on);
  267. }
  268. static int
  269. i8250parity(Uart* uart, int parity)
  270. {
  271. int lcr;
  272. Ctlr *ctlr;
  273. ctlr = uart->regs;
  274. lcr = ctlr->sticky[Lcr] & ~(Eps|Pen);
  275. switch(parity){
  276. case 'e':
  277. lcr |= Eps|Pen;
  278. break;
  279. case 'o':
  280. lcr |= Pen;
  281. break;
  282. case 'n':
  283. break;
  284. default:
  285. return -1;
  286. }
  287. ctlr->sticky[Lcr] = lcr;
  288. csr8w(ctlr, Lcr, 0);
  289. uart->parity = parity;
  290. return 0;
  291. }
  292. static int
  293. i8250stop(Uart* uart, int stop)
  294. {
  295. int lcr;
  296. Ctlr *ctlr;
  297. ctlr = uart->regs;
  298. lcr = ctlr->sticky[Lcr] & ~Stb;
  299. switch(stop){
  300. case 1:
  301. break;
  302. case 2:
  303. lcr |= Stb;
  304. break;
  305. default:
  306. return -1;
  307. }
  308. ctlr->sticky[Lcr] = lcr;
  309. csr8w(ctlr, Lcr, 0);
  310. uart->stop = stop;
  311. return 0;
  312. }
  313. static int
  314. i8250bits(Uart* uart, int bits)
  315. {
  316. int lcr;
  317. Ctlr *ctlr;
  318. ctlr = uart->regs;
  319. lcr = ctlr->sticky[Lcr] & ~WlsMASK;
  320. switch(bits){
  321. case 5:
  322. lcr |= Wls5;
  323. break;
  324. case 6:
  325. lcr |= Wls6;
  326. break;
  327. case 7:
  328. lcr |= Wls7;
  329. break;
  330. case 8:
  331. lcr |= Wls8;
  332. break;
  333. default:
  334. return -1;
  335. }
  336. ctlr->sticky[Lcr] = lcr;
  337. csr8w(ctlr, Lcr, 0);
  338. uart->bits = bits;
  339. return 0;
  340. }
  341. static int
  342. i8250baud(Uart* uart, int baud)
  343. {
  344. ulong bgc;
  345. Ctlr *ctlr;
  346. /*
  347. * Set the Baud rate by calculating and setting the Baud rate
  348. * Generator Constant. This will work with fairly non-standard
  349. * Baud rates.
  350. */
  351. if(uart->freq == 0 || baud <= 0)
  352. return -1;
  353. bgc = (uart->freq+8*baud-1)/(16*baud);
  354. ctlr = uart->regs;
  355. csr8w(ctlr, Lcr, Dlab);
  356. outb(ctlr->io+Dlm, bgc>>8);
  357. outb(ctlr->io+Dll, bgc);
  358. csr8w(ctlr, Lcr, 0);
  359. uart->baud = baud;
  360. return 0;
  361. }
  362. static void
  363. i8250break(Uart* uart, int ms)
  364. {
  365. Ctlr *ctlr;
  366. /*
  367. * Send a break.
  368. */
  369. if(ms <= 0)
  370. ms = 200;
  371. ctlr = uart->regs;
  372. csr8w(ctlr, Lcr, Brk);
  373. tsleep(&up->sleep, return0, 0, ms);
  374. csr8w(ctlr, Lcr, 0);
  375. }
  376. static void
  377. i8250kick(Uart* uart)
  378. {
  379. int i;
  380. Ctlr *ctlr;
  381. if(uart->cts == 0 || uart->blocked)
  382. return;
  383. /*
  384. * 128 here is an arbitrary limit to make sure
  385. * we don't stay in this loop too long. If the
  386. * chip's output queue is longer than 128, too
  387. * bad -- presotto
  388. */
  389. ctlr = uart->regs;
  390. for(i = 0; i < 128; i++){
  391. if(!(csr8r(ctlr, Lsr) & Thre))
  392. break;
  393. if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
  394. break;
  395. outb(ctlr->io+Thr, *(uart->op++));
  396. }
  397. }
  398. static void
  399. i8250interrupt(Ureg*, void* arg)
  400. {
  401. Ctlr *ctlr;
  402. Uart *uart;
  403. int iir, lsr, old, r;
  404. uart = arg;
  405. ctlr = uart->regs;
  406. for(iir = csr8r(ctlr, Iir); !(iir & Ip); iir = csr8r(ctlr, Iir)){
  407. switch(iir & IirMASK){
  408. case Ims: /* Ms interrupt */
  409. r = csr8r(ctlr, Msr);
  410. if(r & Dcts){
  411. ilock(&uart->tlock);
  412. old = uart->cts;
  413. uart->cts = r & Cts;
  414. if(old == 0 && uart->cts)
  415. uart->ctsbackoff = 2;
  416. iunlock(&uart->tlock);
  417. }
  418. if(r & Ddsr){
  419. old = r & Dsr;
  420. if(uart->hup_dsr && uart->dsr && !old)
  421. uart->dohup = 1;
  422. uart->dsr = old;
  423. }
  424. if(r & Ddcd){
  425. old = r & Dcd;
  426. if(uart->hup_dcd && uart->dcd && !old)
  427. uart->dohup = 1;
  428. uart->dcd = old;
  429. }
  430. break;
  431. case Ithre: /* Thr Empty */
  432. uartkick(uart);
  433. break;
  434. case Irda: /* Received Data Available */
  435. case Irls: /* Receiver Line Status */
  436. case Ictoi: /* Character Time-out Indication */
  437. /*
  438. * Consume any received data.
  439. * If the received byte came in with a break,
  440. * parity or framing error, throw it away;
  441. * overrun is an indication that something has
  442. * already been tossed.
  443. */
  444. while((lsr = csr8r(ctlr, Lsr)) & Dr){
  445. if(lsr & (FIFOerr|Oe))
  446. uart->oerr++;
  447. if(lsr & Pe)
  448. uart->perr++;
  449. if(lsr & Fe)
  450. uart->ferr++;
  451. r = csr8r(ctlr, Rbr);
  452. if(!(lsr & (Bi|Fe|Pe)))
  453. uartrecv(uart, r);
  454. }
  455. break;
  456. default:
  457. iprint("weird uart interrupt 0x%2.2uX\n", iir);
  458. break;
  459. }
  460. }
  461. }
  462. static void
  463. i8250disable(Uart* uart)
  464. {
  465. Ctlr *ctlr;
  466. /*
  467. * Turn off DTR and RTS, disable interrupts and fifos.
  468. */
  469. (*uart->phys->dtr)(uart, 0);
  470. (*uart->phys->rts)(uart, 0);
  471. (*uart->phys->fifo)(uart, 0);
  472. ctlr = uart->regs;
  473. ctlr->sticky[Ier] = 0;
  474. csr8w(ctlr, Ier, ctlr->sticky[Ier]);
  475. if(ctlr->iena != 0){
  476. if(intrdisable(ctlr->irq, i8250interrupt, uart, ctlr->tbdf, uart->name) == 0)
  477. ctlr->iena = 0;
  478. }
  479. }
  480. static void
  481. i8250enable(Uart* uart, int ie)
  482. {
  483. Ctlr *ctlr;
  484. ctlr = uart->regs;
  485. /*
  486. * Check if there is a FIFO.
  487. * Changing the FIFOena bit in Fcr flushes data
  488. * from both receive and transmit FIFOs; there's
  489. * no easy way to guarantee not losing data on
  490. * the receive side, but it's possible to wait until
  491. * the transmitter is really empty.
  492. * Also, reading the Iir outwith i8250interrupt()
  493. * can be dangerous, but this should only happen
  494. * once before interrupts are enabled.
  495. */
  496. ilock(ctlr);
  497. if(!ctlr->checkfifo){
  498. /*
  499. * Wait until the transmitter is really empty.
  500. */
  501. while(!(csr8r(ctlr, Lsr) & Temt))
  502. ;
  503. csr8w(ctlr, Fcr, FIFOena);
  504. if(csr8r(ctlr, Iir) & Ifena)
  505. ctlr->hasfifo = 1;
  506. csr8w(ctlr, Fcr, 0);
  507. ctlr->checkfifo = 1;
  508. }
  509. iunlock(ctlr);
  510. /*
  511. * Enable interrupts and turn on DTR and RTS.
  512. * Be careful if this is called to set up a polled serial line
  513. * early on not to try to enable interrupts as interrupt-
  514. * -enabling mechanisms might not be set up yet.
  515. */
  516. if(ie){
  517. if(ctlr->iena == 0){
  518. intrenable(ctlr->irq, i8250interrupt, uart, ctlr->tbdf, uart->name);
  519. ctlr->iena = 1;
  520. }
  521. ctlr->sticky[Ier] = Ethre|Erda;
  522. ctlr->sticky[Mcr] |= Ie;
  523. }
  524. else{
  525. ctlr->sticky[Ier] = 0;
  526. ctlr->sticky[Mcr] = 0;
  527. }
  528. csr8w(ctlr, Ier, ctlr->sticky[Ier]);
  529. csr8w(ctlr, Mcr, ctlr->sticky[Mcr]);
  530. (*uart->phys->dtr)(uart, 1);
  531. (*uart->phys->rts)(uart, 1);
  532. /*
  533. * During startup, the i8259 interrupt controller is reset.
  534. * This may result in a lost interrupt from the i8250 uart.
  535. * The i8250 thinks the interrupt is still outstanding and does not
  536. * generate any further interrupts. The workaround is to call the
  537. * interrupt handler to clear any pending interrupt events.
  538. * Note: this must be done after setting Ier.
  539. */
  540. if(ie)
  541. i8250interrupt(nil, uart);
  542. }
  543. void*
  544. i8250alloc(int io, int irq, int tbdf)
  545. {
  546. Ctlr *ctlr;
  547. if((ctlr = malloc(sizeof(Ctlr))) != nil){
  548. ctlr->io = io;
  549. ctlr->irq = irq;
  550. ctlr->tbdf = tbdf;
  551. }
  552. return ctlr;
  553. }
  554. static Uart*
  555. i8250pnp(void)
  556. {
  557. return i8250uart;
  558. }
  559. static int
  560. i8250getc(Uart *uart)
  561. {
  562. Ctlr *ctlr;
  563. ctlr = uart->regs;
  564. while(!(csr8r(ctlr, Lsr)&Dr))
  565. delay(1);
  566. return csr8r(ctlr, Rbr);
  567. }
  568. static void
  569. i8250putc(Uart *uart, int c)
  570. {
  571. int i;
  572. Ctlr *ctlr;
  573. ctlr = uart->regs;
  574. for(i = 0; !(csr8r(ctlr, Lsr)&Thre) && i < 128; i++)
  575. delay(1);
  576. outb(ctlr->io+Thr, c);
  577. for(i = 0; !(csr8r(ctlr, Lsr)&Thre) && i < 128; i++)
  578. delay(1);
  579. }
  580. PhysUart i8250physuart = {
  581. .name = "i8250",
  582. .pnp = i8250pnp,
  583. .enable = i8250enable,
  584. .disable = i8250disable,
  585. .kick = i8250kick,
  586. .dobreak = i8250break,
  587. .baud = i8250baud,
  588. .bits = i8250bits,
  589. .stop = i8250stop,
  590. .parity = i8250parity,
  591. .modemctl = i8250modemctl,
  592. .rts = i8250rts,
  593. .dtr = i8250dtr,
  594. .status = i8250status,
  595. .fifo = i8250fifo,
  596. .getc = i8250getc,
  597. .putc = i8250putc,
  598. };
  599. void
  600. i8250console(void)
  601. {
  602. Uart *uart;
  603. int n;
  604. char *cmd, *p;
  605. if((p = getconf("console")) == nil)
  606. return;
  607. n = strtoul(p, &cmd, 0);
  608. if(p == cmd)
  609. return;
  610. switch(n){
  611. default:
  612. return;
  613. case 0:
  614. uart = &i8250uart[0];
  615. break;
  616. case 1:
  617. uart = &i8250uart[1];
  618. break;
  619. }
  620. (*uart->phys->enable)(uart, 0);
  621. uartctl(uart, "b9600 l8 pn s1");
  622. if(*cmd != '\0')
  623. uartctl(uart, cmd);
  624. consuart = uart;
  625. uart->console = 1;
  626. }
  627. void
  628. i8250mouse(char* which, int (*putc)(Queue*, int), int setb1200)
  629. {
  630. char *p;
  631. int port;
  632. port = strtol(which, &p, 0);
  633. if(p == which || port < 0 || port > 1)
  634. error(Ebadarg);
  635. uartmouse(&i8250uart[port], putc, setb1200);
  636. }
  637. void
  638. i8250setmouseputc(char* which, int (*putc)(Queue*, int))
  639. {
  640. char *p;
  641. int port;
  642. port = strtol(which, &p, 0);
  643. if(p == which || port < 0 || port > 1)
  644. error(Ebadarg);
  645. uartsetmouseputc(&i8250uart[port], putc);
  646. }