uartpci.c 2.8 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "../port/error.h"
  8. extern PhysUart i8250physuart;
  9. extern PhysUart pciphysuart;
  10. extern void* i8250alloc(int, int, int);
  11. static Uart*
  12. uartpci(int ctlrno, Pcidev* p, int barno, int n, int freq, char* name)
  13. {
  14. int i, io;
  15. void *ctlr;
  16. char buf[64];
  17. Uart *head, *uart;
  18. io = p->mem[barno].bar & ~0x01;
  19. snprint(buf, sizeof(buf), "%s%d", pciphysuart.name, ctlrno);
  20. if(ioalloc(io, p->mem[barno].size, 0, buf) < 0){
  21. print("uartpci: I/O 0x%uX in use\n", io);
  22. return nil;
  23. }
  24. head = uart = malloc(sizeof(Uart)*n);
  25. for(i = 0; i < n; i++){
  26. ctlr = i8250alloc(io, p->intl, p->tbdf);
  27. io += 8;
  28. if(ctlr == nil)
  29. continue;
  30. uart->regs = ctlr;
  31. snprint(buf, sizeof(buf), "%s.%8.8uX", name, p->tbdf);
  32. kstrdup(&uart->name, buf);
  33. uart->freq = freq;
  34. uart->phys = &i8250physuart;
  35. if(uart != head)
  36. (uart-1)->next = uart;
  37. uart++;
  38. }
  39. return head;
  40. }
  41. static Uart*
  42. uartpcipnp(void)
  43. {
  44. Pcidev *p;
  45. char *name;
  46. int ctlrno, n, subid;
  47. Uart *head, *tail, *uart;
  48. /*
  49. * Loop through all PCI devices looking for simple serial
  50. * controllers (ccrb == 0x07) and configure the ones which
  51. * are familiar. All suitable devices are configured to
  52. * simply point to the generic i8250 driver.
  53. */
  54. head = tail = nil;
  55. ctlrno = 0;
  56. for(p = pcimatch(nil, 0, 0); p != nil; p = pcimatch(p, 0, 0)){
  57. if(p->ccrb != 0x07 || p->ccru != 0)
  58. continue;
  59. switch((p->did<<16)|p->vid){
  60. default:
  61. continue;
  62. case (0x9050<<16)|0x10B5: /* Perle PCI-Fast4 series */
  63. case (0x9030<<16)|0x10B5: /* Perle Ultraport series */
  64. /*
  65. * These devices consists of a PLX bridge (the above
  66. * PCI VID+DID) behind which are some 16C654 UARTs.
  67. * Must check the subsystem VID and DID for correct
  68. * match.
  69. */
  70. subid = pcicfgr16(p, PciSVID);
  71. subid |= pcicfgr16(p, PciSID)<<16;
  72. switch(subid){
  73. default:
  74. continue;
  75. case (0x0011<<16)|0x12E0: /* Perle PCI-Fast16 */
  76. n = 16;
  77. name = "PCI-Fast16";
  78. break;
  79. case (0x0021<<16)|0x12E0: /* Perle PCI-Fast8 */
  80. n = 8;
  81. name = "PCI-Fast8";
  82. break;
  83. case (0x0031<<16)|0x12E0: /* Perle PCI-Fast4 */
  84. n = 4;
  85. name = "PCI-Fast4";
  86. break;
  87. case (0x0021<<16)|0x155F: /* Perle Ultraport8 */
  88. n = 8;
  89. name = "Ultraport8"; /* 16C754 UARTs */
  90. break;
  91. }
  92. uart = uartpci(ctlrno, p, 2, n, 7372800, name);
  93. if(uart == nil)
  94. continue;
  95. break;
  96. }
  97. if(head != nil)
  98. tail->next = uart;
  99. else
  100. head = uart;
  101. for(tail = uart; tail->next != nil; tail = tail->next)
  102. ;
  103. ctlrno++;
  104. }
  105. return head;
  106. }
  107. PhysUart pciphysuart = {
  108. .name = "UartPCI",
  109. .pnp = uartpcipnp,
  110. .enable = nil,
  111. .disable = nil,
  112. .kick = nil,
  113. .dobreak = nil,
  114. .baud = nil,
  115. .bits = nil,
  116. .stop = nil,
  117. .parity = nil,
  118. .modemctl = nil,
  119. .rts = nil,
  120. .dtr = nil,
  121. .status = nil,
  122. .fifo = nil,
  123. };