io.h 6.5 KB

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  1. /*
  2. * programmable interrupt vectors (for the 8259's)
  3. */
  4. enum
  5. {
  6. Bptvec= 3, /* breakpoints */
  7. Mathemuvec= 7, /* math coprocessor emulation interrupt */
  8. Mathovervec= 9, /* math coprocessor overrun interrupt */
  9. Matherr1vec= 16, /* math coprocessor error interrupt */
  10. Faultvec= 14, /* page fault */
  11. Int0vec= 24, /* first 8259 */
  12. Clockvec= Int0vec+0, /* clock interrupts */
  13. Kbdvec= Int0vec+1, /* keyboard interrupts */
  14. Uart1vec= Int0vec+3, /* modem line */
  15. Uart0vec= Int0vec+4, /* serial line */
  16. PCMCIAvec= Int0vec+5, /* PCMCIA card change */
  17. Floppyvec= Int0vec+6, /* floppy interrupts */
  18. Parallelvec= Int0vec+7, /* parallel port interrupts */
  19. Int1vec= Int0vec+8,
  20. Ethervec= Int0vec+10, /* ethernet interrupt */
  21. Mousevec= Int0vec+12, /* mouse interrupt */
  22. Matherr2vec= Int0vec+13, /* math coprocessor */
  23. ATA0vec= Int0vec+14, /* hard disk */
  24. Syscallvec= 64,
  25. };
  26. /*
  27. * 8259 interrupt controllers
  28. */
  29. enum
  30. {
  31. Int0ctl= 0x20, /* control port (ICW1, OCW2, OCW3) */
  32. Int0aux= 0x21, /* everything else (ICW2, ICW3, ICW4, OCW1) */
  33. Int1ctl= 0xA0, /* control port */
  34. Int1aux= 0xA1, /* everything else (ICW2, ICW3, ICW4, OCW1) */
  35. Icw1= 0x10, /* select bit in ctl register */
  36. Ocw2= 0x00,
  37. Ocw3= 0x08,
  38. EOI= 0x20, /* non-specific end of interrupt */
  39. Elcr1= 0x4D0, /* Edge/Level Triggered Register */
  40. Elcr2= 0x4D1,
  41. };
  42. extern int int0mask; /* interrupts enabled for first 8259 */
  43. extern int int1mask; /* interrupts enabled for second 8259 */
  44. #define NVRAUTHADDR 0
  45. #define LINESIZE 0
  46. enum {
  47. MaxEISA = 16,
  48. EISAconfig = 0xC80,
  49. MaxScsi = 4,
  50. NTarget = 16,
  51. MaxEther = 4,
  52. };
  53. #define DMAOK(x, l) ((ulong)(((ulong)(x))+(l)) < (ulong)(KZERO|16*1024*1024))
  54. enum {
  55. BusCBUS = 0, /* Corollary CBUS */
  56. BusCBUSII, /* Corollary CBUS II */
  57. BusEISA, /* Extended ISA */
  58. BusFUTURE, /* IEEE Futurebus */
  59. BusINTERN, /* Internal bus */
  60. BusISA, /* Industry Standard Architecture */
  61. BusMBI, /* Multibus I */
  62. BusMBII, /* Multibus II */
  63. BusMCA, /* Micro Channel Architecture */
  64. BusMPI, /* MPI */
  65. BusMPSA, /* MPSA */
  66. BusNUBUS, /* Apple Macintosh NuBus */
  67. BusPCI, /* Peripheral Component Interconnect */
  68. BusPCMCIA, /* PC Memory Card International Association */
  69. BusTC, /* DEC TurboChannel */
  70. BusVL, /* VESA Local bus */
  71. BusVME, /* VMEbus */
  72. BusXPRESS, /* Express System Bus */
  73. };
  74. #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
  75. #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
  76. #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
  77. #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
  78. #define BUSTYPE(tbdf) ((tbdf)>>24)
  79. #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
  80. #define BUSUNKNOWN (-1)
  81. /*
  82. * PCI support code.
  83. */
  84. enum { /* type 0 and type 1 pre-defined header */
  85. PciVID = 0x00, /* vendor ID */
  86. PciDID = 0x02, /* device ID */
  87. PciPCR = 0x04, /* command */
  88. PciPSR = 0x06, /* status */
  89. PciRID = 0x08, /* revision ID */
  90. PciCCRp = 0x09, /* programming interface class code */
  91. PciCCRu = 0x0A, /* sub-class code */
  92. PciCCRb = 0x0B, /* base class code */
  93. PciCLS = 0x0C, /* cache line size */
  94. PciLTR = 0x0D, /* latency timer */
  95. PciHDT = 0x0E, /* header type */
  96. PciBST = 0x0F, /* BIST */
  97. PciBAR0 = 0x10, /* base address */
  98. PciBAR1 = 0x14,
  99. PciINTL = 0x3C, /* interrupt line */
  100. PciINTP = 0x3D, /* interrupt pin */
  101. };
  102. enum { /* type 0 pre-defined header */
  103. PciBAR2 = 0x18,
  104. PciBAR3 = 0x1C,
  105. PciBAR4 = 0x20,
  106. PciBAR5 = 0x24,
  107. PciCIS = 0x28, /* cardbus CIS pointer */
  108. PciSVID = 0x2C, /* subsystem vendor ID */
  109. PciSID = 0x2E, /* cardbus CIS pointer */
  110. PciEBAR0 = 0x30, /* expansion ROM base address */
  111. PciMGNT = 0x3E, /* burst period length */
  112. PciMLT = 0x3F, /* maximum latency between bursts */
  113. };
  114. enum { /* type 1 pre-defined header */
  115. PciPBN = 0x18, /* primary bus number */
  116. PciSBN = 0x19, /* secondary bus number */
  117. PciUBN = 0x1A, /* subordinate bus number */
  118. PciSLTR = 0x1B, /* secondary latency timer */
  119. PciIBR = 0x1C, /* I/O base */
  120. PciILR = 0x1D, /* I/O limit */
  121. PciSPSR = 0x1E, /* secondary status */
  122. PciMBR = 0x20, /* memory base */
  123. PciMLR = 0x22, /* memory limit */
  124. PciPMBR = 0x24, /* prefetchable memory base */
  125. PciPMLR = 0x26, /* prefetchable memory limit */
  126. PciPUBR = 0x28, /* prefetchable base upper 32 bits */
  127. PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
  128. PciIUBR = 0x30, /* I/O base upper 16 bits */
  129. PciIULR = 0x32, /* I/O limit upper 16 bits */
  130. PciEBAR1 = 0x28, /* expansion ROM base address */
  131. PciBCR = 0x3E, /* bridge control register */
  132. };
  133. typedef struct Pcidev Pcidev;
  134. typedef struct Pcidev {
  135. int tbdf; /* type+bus+device+function */
  136. ushort vid; /* vendor ID */
  137. ushort did; /* device ID */
  138. struct {
  139. ulong bar; /* base address */
  140. int size;
  141. } mem[6];
  142. uchar rid;
  143. uchar ccrp;
  144. uchar ccrb;
  145. uchar intl; /* interrupt line */
  146. ushort ccru; /* is uchar in cpu kernel */
  147. ulong pcr;
  148. Pcidev* list;
  149. Pcidev* bridge; /* down a bus */
  150. Pcidev* link; /* next device on this bno */
  151. } Pcidev;
  152. extern int pcicfgr8(Pcidev*, int);
  153. extern int pcicfgr16(Pcidev*, int);
  154. extern int pcicfgr32(Pcidev*, int);
  155. extern void pcicfgw8(Pcidev*, int, int);
  156. extern void pcicfgw16(Pcidev*, int, int);
  157. extern void pcicfgw32(Pcidev*, int, int);
  158. extern void pcihinv(Pcidev*, ulong);
  159. extern Pcidev* pcimatch(Pcidev*, int, int);
  160. extern Pcidev* pcimatchtbdf(int);
  161. extern void pcireset(void);
  162. extern void pcisetbme(Pcidev*);
  163. extern void pciclrbme(Pcidev*);
  164. /*
  165. * a parsed plan9.ini line
  166. */
  167. #define ISAOPTLEN 16
  168. #define NISAOPT 8
  169. typedef struct ISAConf {
  170. char type[NAMELEN];
  171. ulong port;
  172. ulong irq;
  173. ulong dma;
  174. ulong mem;
  175. ulong size;
  176. ulong freq;
  177. int nopt;
  178. char opt[NISAOPT][ISAOPTLEN];
  179. } ISAConf;
  180. extern int isaconfig(char*, int, ISAConf*);
  181. /*
  182. * SCSI support code.
  183. */
  184. enum {
  185. STblank =-6, /* blank block */
  186. STnomem =-5, /* buffer allocation failed */
  187. STtimeout =-4, /* bus timeout */
  188. STownid =-3, /* playing with myself */
  189. STharderr =-2, /* controller error of some kind */
  190. STinit =-1, /* */
  191. STok = 0, /* good */
  192. STcheck = 0x02, /* check condition */
  193. STcondmet = 0x04, /* condition met/good */
  194. STbusy = 0x08, /* busy */
  195. STintok = 0x10, /* intermediate/good */
  196. STintcondmet = 0x14, /* intermediate/condition met/good */
  197. STresconf = 0x18, /* reservation conflict */
  198. STterminated = 0x22, /* command terminated */
  199. STqfull = 0x28, /* queue full */
  200. };
  201. typedef struct Target {
  202. int ctlrno;
  203. int targetno;
  204. uchar* inquiry;
  205. uchar* sense;
  206. QLock;
  207. char id[NAMELEN];
  208. int ok;
  209. char fflag;
  210. Filter work[3];
  211. Filter rate[3];
  212. } Target;
  213. typedef int (*Scsiio)(Target*, int, uchar*, int, void*, int*);