mem.h 6.2 KB

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  1. /*
  2. * Memory and machine-specific definitions. Used in C and assembler.
  3. */
  4. #define KiB 1024u /* Kibi 0x0000000000000400 */
  5. #define MiB 1048576u /* Mebi 0x0000000000100000 */
  6. #define GiB 1073741824u /* Gibi 000000000040000000 */
  7. #define HOWMANY(x, y) (((x)+((y)-1))/(y))
  8. #define ROUNDUP(x, y) (HOWMANY((x), (y))*(y)) /* ceiling */
  9. #define ROUNDDN(x, y) (((x)/(y))*(y)) /* floor */
  10. #define MIN(a, b) ((a) < (b)? (a): (b))
  11. #define MAX(a, b) ((a) > (b)? (a): (b))
  12. /*
  13. * Sizes
  14. */
  15. #define BI2BY 8 /* bits per byte */
  16. #define BI2WD 32 /* bits per word */
  17. #define BY2WD 4 /* bytes per word */
  18. #define BY2V 8 /* bytes per vlong */
  19. #define BY2PG 4096 /* bytes per page */
  20. #define WD2PG (BY2PG/BY2WD) /* words per page */
  21. #define PGSHIFT 12 /* log(BY2PG) */
  22. #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
  23. #define PGROUND(s) ROUND(s, BY2PG)
  24. #define CACHELINELOG 4
  25. #define CACHELINESZ (1<<CACHELINELOG)
  26. #define BLOCKALIGN CACHELINESZ
  27. #define MHz 1000000
  28. #define BY2PTE 8 /* bytes per pte entry */
  29. #define BY2PTEG 64 /* bytes per pte group */
  30. #define MAXMACH 1 /* max # cpus system can run */
  31. #define MACHSIZE BY2PG
  32. #define KSTACK 4096 /* Size of kernel stack */
  33. /*
  34. * Time
  35. */
  36. #define HZ 100 /* clock frequency */
  37. #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
  38. /*
  39. * Standard PPC Special Purpose Registers (OEA and VEA)
  40. */
  41. #define DSISR 18
  42. #define DAR 19 /* Data Address Register */
  43. #define DEC 22 /* Decrementer */
  44. #define SDR1 25
  45. #define SRR0 26 /* Saved Registers (exception) */
  46. #define SRR1 27
  47. #define SPRG0 272 /* Supervisor Private Registers */
  48. #define SPRG1 273
  49. #define SPRG2 274
  50. #define SPRG3 275
  51. #define ASR 280 /* Address Space Register */
  52. #define EAR 282 /* External Access Register (optional) */
  53. #define TBRU 269 /* Time base Upper/Lower (Reading) */
  54. #define TBRL 268
  55. #define TBWU 284 /* Time base Upper/Lower (Writing) */
  56. #define TBWL 285
  57. #define PVR 287 /* Processor Version */
  58. #define IABR 1010 /* Instruction Address Breakpoint Register (optional) */
  59. #define DABR 1013 /* Data Address Breakpoint Register (optional) */
  60. #define FPECR 1022 /* Floating-Point Exception Cause Register (optional) */
  61. #define PIR 1023 /* Processor Identification Register (optional) */
  62. #define IBATU(i) (528+2*(i)) /* Instruction BAT register (upper) */
  63. #define IBATL(i) (529+2*(i)) /* Instruction BAT register (lower) */
  64. #define DBATU(i) (536+2*(i)) /* Data BAT register (upper) */
  65. #define DBATL(i) (537+2*(i)) /* Data BAT register (lower) */
  66. /*
  67. * PPC604e-specific Special Purpose Registers (OEA)
  68. */
  69. #define HID0 1008 /* Hardware Implementation Dependant Register 0 */
  70. #define HID1 1009 /* Hardware Implementation Dependant Register 1 */
  71. #define PMC1 953 /* Performance Monitor Counter 1 */
  72. #define PMC2 954 /* Performance Monitor Counter 2 */
  73. #define PMC3 957 /* Performance Monitor Counter 3 */
  74. #define PMC4 958 /* Performance Monitor Counter 4 */
  75. #define MMCR0 952 /* Monitor Control Register 0 */
  76. #define MMCR1 956 /* Monitor Control Register 0 */
  77. #define SIA 955 /* Sampled Instruction Address */
  78. #define SDA 959 /* Sampled Data Address */
  79. #define BIT(i) (1<<(31-(i))) /* Silly backwards register bit numbering scheme */
  80. /*
  81. * Bit encodings for Machine State Register (MSR)
  82. */
  83. #define MSR_POW BIT(13) /* Enable Power Management */
  84. #define MSR_ILE BIT(15) /* Interrupt Little-Endian enable */
  85. #define MSR_EE BIT(16) /* External Interrupt enable */
  86. #define MSR_PR BIT(17) /* Supervisor/User privelege */
  87. #define MSR_FP BIT(18) /* Floating Point enable */
  88. #define MSR_ME BIT(19) /* Machine Check enable */
  89. #define MSR_FE0 BIT(20) /* Floating Exception mode 0 */
  90. #define MSR_SE BIT(21) /* Single Step (optional) */
  91. #define MSR_BE BIT(22) /* Branch Trace (optional) */
  92. #define MSR_FE1 BIT(23) /* Floating Exception mode 1 */
  93. #define MSR_IP BIT(25) /* Exception prefix 0x000/0xFFF */
  94. #define MSR_IR BIT(26) /* Instruction MMU enable */
  95. #define MSR_DR BIT(27) /* Data MMU enable */
  96. #define MSR_PM BIT(29) /* Performance Monitor marked mode (604e specific) */
  97. #define MSR_RI BIT(30) /* Recoverable Exception */
  98. #define MSR_LE BIT(31) /* Little-Endian enable */
  99. /*
  100. * Exception codes (trap vectors)
  101. */
  102. #define CRESET 0x01
  103. #define CMCHECK 0x02
  104. #define CDSI 0x03
  105. #define CISI 0x04
  106. #define CEI 0x05
  107. #define CALIGN 0x06
  108. #define CPROG 0x07
  109. #define CFPU 0x08
  110. #define CDEC 0x09
  111. #define CSYSCALL 0x0C
  112. #define CTRACE 0x0D /* optional */
  113. #define CFPA 0x0E /* optional */
  114. /* PPC604e-specific: */
  115. #define CPERF 0x0F /* performance monitoring */
  116. #define CIBREAK 0x13
  117. #define CSMI 0x14
  118. /*
  119. * Magic registers
  120. */
  121. #define MACH 30 /* R30 is m-> */
  122. #define USER 29 /* R29 is up-> */
  123. /*
  124. * virtual MMU
  125. */
  126. #define PTEMAPMEM (1024*1024)
  127. #define PTEPERTAB (PTEMAPMEM/BY2PG)
  128. #define SEGMAPSIZE 1984
  129. #define SSEGMAPSIZE 16
  130. #define PPN(x) ((x)&~(BY2PG-1))
  131. /*
  132. * First pte word
  133. */
  134. #define PTE0(v, vsid, h, va) (((v)<<31)|((vsid)<<7)|((h)<<6)|(((va)>>22)&0x3f))
  135. /*
  136. * Second pte word; WIMG & PP(RW/RO) common to page table and BATs
  137. */
  138. #define PTE1_W BIT(25)
  139. #define PTE1_I BIT(26)
  140. #define PTE1_M BIT(27)
  141. #define PTE1_G BIT(28)
  142. #define PTE1_RW BIT(30)
  143. #define PTE1_RO BIT(31)
  144. /*
  145. * PTE bits for fault.c. These belong to the second PTE word. Validity is
  146. * implied for putmmu(), and we always set PTE0_V. PTEVALID is used
  147. * here to set cache policy bits on a global basis.
  148. */
  149. #define PTEVALID 0
  150. #define PTEWRITE PTE1_RW
  151. #define PTERONLY PTE1_RO
  152. #define PTEUNCACHED PTE1_I
  153. /*
  154. * Address spaces
  155. */
  156. #define UZERO 0 /* base of user address space */
  157. #define UTZERO (UZERO+BY2PG) /* first address in user text */
  158. #define USTKTOP (TSTKTOP-TSTKSIZ*BY2PG) /* byte just beyond user stack */
  159. #define TSTKTOP KZERO /* top of temporary stack */
  160. #define TSTKSIZ 100
  161. #define KZERO 0x80000000 /* base of kernel address space */
  162. #define KTZERO (KZERO+0x4000) /* first address in kernel text */
  163. #define USTKSIZE (4*1024*1024) /* size of user stack */
  164. #define UREGSIZE ((8+32)*4)
  165. #define PCIMEM0 0xf0000000
  166. #define PCISIZE0 0x0e000000
  167. #define PCIMEM1 0xc0000000
  168. #define PCISIZE1 0x30000000
  169. #define IOMEM 0xfe000000
  170. #define IOSIZE 0x00800000
  171. #define FALCON 0xfef80000
  172. #define RAVEN 0xfeff0000
  173. #define FLASHA 0xff000000
  174. #define FLASHB 0xff800000
  175. #define FLASHAorB 0xfff00000
  176. #define isphys(x) (((ulong)x&KZERO)!=0)
  177. #define getpgcolor(a) 0