arm.h 8.3 KB

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  1. /*
  2. * arm-specific definitions for cortex-a8
  3. * these are used in C and assembler
  4. *
  5. * `cortex' refers specifically to the cortex-a8.
  6. */
  7. /*
  8. * Program Status Registers
  9. */
  10. #define PsrMusr 0x00000010 /* mode */
  11. #define PsrMfiq 0x00000011
  12. #define PsrMirq 0x00000012
  13. #define PsrMsvc 0x00000013 /* `protected mode for OS' */
  14. #define PsrMmon 0x00000016 /* `secure monitor' (trustzone hyper) */
  15. #define PsrMabt 0x00000017
  16. #define PsrMund 0x0000001B
  17. #define PsrMsys 0x0000001F /* `privileged user mode for OS' (trustzone) */
  18. #define PsrMask 0x0000001F
  19. #define PsrDfiq 0x00000040 /* disable FIQ interrupts */
  20. #define PsrDirq 0x00000080 /* disable IRQ interrupts */
  21. #define PsrV 0x10000000 /* overflow */
  22. #define PsrC 0x20000000 /* carry/borrow/extend */
  23. #define PsrZ 0x40000000 /* zero */
  24. #define PsrN 0x80000000 /* negative/less than */
  25. /*
  26. * Coprocessors
  27. */
  28. #define CpFP 10 /* float FP, VFP cfg. */
  29. #define CpDFP 11 /* double FP */
  30. #define CpSC 15 /* System Control */
  31. /*
  32. * Primary (CRn) CpSC registers.
  33. */
  34. #define CpID 0 /* ID and cache type */
  35. #define CpCONTROL 1 /* miscellaneous control */
  36. #define CpTTB 2 /* Translation Table Base(s) */
  37. #define CpDAC 3 /* Domain Access Control */
  38. #define CpFSR 5 /* Fault Status */
  39. #define CpFAR 6 /* Fault Address */
  40. #define CpCACHE 7 /* cache/write buffer control */
  41. #define CpTLB 8 /* TLB control */
  42. #define CpCLD 9 /* L2 Cache Lockdown, op1==1 */
  43. #define CpTLD 10 /* TLB Lockdown, with op2 */
  44. #define CpVECS 12 /* vector bases, op1==0, Crm==0, op2s (cortex) */
  45. #define CpPID 13 /* Process ID */
  46. #define CpDTLB 15 /* TLB, L1 cache stuff (cortex) */
  47. /*
  48. * CpTTB op1==0, Crm==0 opcode2 values.
  49. */
  50. #define CpTTB0 0
  51. #define CpTTB1 1 /* cortex */
  52. #define CpTTBctl 2 /* cortex */
  53. /*
  54. * CpFSR op1==0, Crm==0 opcode 2 values.
  55. */
  56. #define CpDFSR 0 /* data fault status */
  57. #define CpIFSR 1 /* instruction fault status */
  58. /*
  59. * CpID Secondary (CRm) registers.
  60. */
  61. #define CpIDidct 0
  62. /*
  63. * CpID op1==0 opcode2 fields.
  64. * the cortex has more op1 codes for cache size, etc.
  65. */
  66. #define CpIDid 0 /* main ID */
  67. #define CpIDct 1 /* cache type */
  68. #define CpIDtlb 3 /* tlb type (cortex) */
  69. #define CpIDmpid 5 /* multiprocessor id (cortex) */
  70. /* CpIDid op1 values */
  71. #define CpIDcsize 1 /* cache size (cortex) */
  72. #define CpIDcssel 2 /* cache size select (cortex) */
  73. /*
  74. * CpCONTROL op2 codes, op1==0, Crm==0.
  75. */
  76. #define CpMainctl 0
  77. #define CpAuxctl 1
  78. #define CpCPaccess 2
  79. /*
  80. * CpCONTROL: op1==0, CRm==0, op2==CpMainctl.
  81. * main control register.
  82. * cortex/armv7 has more ops and CRm values.
  83. */
  84. #define CpCmmu 0x00000001 /* M: MMU enable */
  85. #define CpCalign 0x00000002 /* A: alignment fault enable */
  86. #define CpCdcache 0x00000004 /* C: data cache on */
  87. #define CpCsbo (3<<22|1<<18|1<<16|017<<3) /* must be 1 (armv7) */
  88. #define CpCsbz (CpCtre|1<<26|CpCve|1<<15|7<<7) /* must be 0 (armv7) */
  89. #define CpCsw (1<<10) /* SW: SWP(B) enable (deprecated in v7) */
  90. #define CpCpredict 0x00000800 /* Z: branch prediction (armv7) */
  91. #define CpCicache 0x00001000 /* I: instruction cache on */
  92. #define CpChv 0x00002000 /* V: high vectors */
  93. #define CpCrr (1<<14) /* RR: round robin vs random cache replacement */
  94. #define CpCha (1<<17) /* HA: hw access flag enable */
  95. #define CpCdz (1<<19) /* DZ: divide by zero fault enable */
  96. #define CpCfi (1<<21) /* FI: fast intrs */
  97. #define CpCve (1<<24) /* VE: intr vectors enable */
  98. #define CpCee (1<<25) /* EE: exception endianness */
  99. #define CpCnmfi (1<<27) /* NMFI: non-maskable fast intrs. */
  100. #define CpCtre (1<<28) /* TRE: TEX remap enable */
  101. #define CpCafe (1<<29) /* AFE: access flag (ttb) enable */
  102. /*
  103. * CpCONTROL: op1==0, CRm==0, op2==CpAuxctl.
  104. * Auxiliary control register on cortex at least.
  105. */
  106. #define CpACcachenopipe (1<<20) /* don't pipeline cache maint. */
  107. #define CpACcp15serial (1<<18) /* serialise CP1[45] ops. */
  108. #define CpACcp15waitidle (1<<17) /* CP1[45] wait-on-idle */
  109. #define CpACcp15pipeflush (1<<16) /* CP1[45] flush pipeline */
  110. #define CpACneonissue1 (1<<12) /* neon single issue */
  111. #define CpACldstissue1 (1<<11) /* force single issue ld, st */
  112. #define CpACissue1 (1<<10) /* force single issue */
  113. #define CpACnobsm (1<<7) /* no branch size mispredicts */
  114. #define CpACibe (1<<6) /* cp15 invalidate & btb enable */
  115. #define CpACl1neon (1<<5) /* cache neon (FP) data in L1 cache */
  116. #define CpACasa (1<<4) /* enable speculative accesses */
  117. #define CpACl1pe (1<<3) /* l1 cache parity enable */
  118. #define CpACl2en (1<<1) /* l2 cache enable; default 1 */
  119. /*
  120. * CpCONTROL Secondary (CRm) registers and opcode2 fields.
  121. */
  122. #define CpCONTROLscr 1
  123. #define CpSCRscr 0
  124. /*
  125. * CpCACHE Secondary (CRm) registers and opcode2 fields. op1==0.
  126. * In ARM-speak, 'flush' means invalidate and 'clean' means writeback.
  127. */
  128. #define CpCACHEintr 0 /* interrupt (op2==4) */
  129. #define CpCACHEisi 1 /* inner-sharable I cache (v7) */
  130. #define CpCACHEpaddr 4 /* 0: phys. addr (cortex) */
  131. #define CpCACHEinvi 5 /* instruction, branch table */
  132. #define CpCACHEinvd 6 /* data or unified */
  133. // #define CpCACHEinvu 7 /* unified (not on cortex) */
  134. #define CpCACHEva2pa 8 /* va -> pa translation (cortex) */
  135. #define CpCACHEwb 10 /* writeback */
  136. #define CpCACHEinvdse 11 /* data or unified by mva */
  137. #define CpCACHEwbi 14 /* writeback+invalidate */
  138. #define CpCACHEall 0 /* entire (not for invd nor wb(i) on cortex) */
  139. #define CpCACHEse 1 /* single entry */
  140. #define CpCACHEsi 2 /* set/index (set/way) */
  141. #define CpCACHEtest 3 /* test loop */
  142. #define CpCACHEwait 4 /* wait (prefetch flush on cortex) */
  143. #define CpCACHEdmbarr 5 /* wb only (cortex) */
  144. #define CpCACHEflushbtc 6 /* flush branch-target cache (cortex) */
  145. #define CpCACHEflushbtse 7 /* ⋯ or just one entry in it (cortex) */
  146. /*
  147. * CpTLB Secondary (CRm) registers and opcode2 fields.
  148. */
  149. #define CpTLBinvi 5 /* instruction */
  150. #define CpTLBinvd 6 /* data */
  151. #define CpTLBinvu 7 /* unified */
  152. #define CpTLBinv 0 /* invalidate all */
  153. #define CpTLBinvse 1 /* invalidate single entry */
  154. #define CpTBLasid 2 /* by ASID (cortex) */
  155. /*
  156. * CpCLD Secondary (CRm) registers and opcode2 fields for op1==0. (cortex)
  157. */
  158. #define CpCLDena 12 /* enables */
  159. #define CpCLDcyc 13 /* cycle counter */
  160. #define CpCLDuser 14 /* user enable */
  161. #define CpCLDenapmnc 0
  162. #define CpCLDenacyc 1
  163. /*
  164. * CpCLD Secondary (CRm) registers and opcode2 fields for op1==1.
  165. */
  166. #define CpCLDl2 0 /* l2 cache */
  167. #define CpCLDl2aux 2 /* auxiliary control */
  168. /*
  169. * l2 cache aux. control
  170. */
  171. #define CpCl2ecc (1<<28) /* use ecc, not parity */
  172. #define CpCl2noldforw (1<<27) /* no ld forwarding */
  173. #define CpCl2nowrcomb (1<<25) /* no write combining */
  174. #define CpCl2nowralldel (1<<24) /* no write allocate delay */
  175. #define CpCl2nowrallcomb (1<<23) /* no write allocate combine */
  176. #define CpCl2nowralloc (1<<22) /* no write allocate */
  177. #define CpCl2eccparity (1<<21) /* enable ecc or parity */
  178. #define CpCl2inner (1<<16) /* inner cacheability */
  179. /* other bits are tag ram & data ram latencies */
  180. /*
  181. * CpTLD Secondary (CRm) registers and opcode2 fields.
  182. */
  183. #define CpTLDlock 0 /* TLB lockdown registers */
  184. #define CpTLDpreload 1 /* TLB preload */
  185. #define CpTLDi 0 /* TLB instr. lockdown reg. */
  186. #define CpTLDd 1 /* " data " " */
  187. /*
  188. * CpVECS Secondary (CRm) registers and opcode2 fields.
  189. */
  190. #define CpVECSbase 0
  191. #define CpVECSnorm 0 /* (non-)secure base addr */
  192. #define CpVECSmon 1 /* secure monitor base addr */
  193. /*
  194. * MMU page table entries.
  195. * Mbz (0x10) bit is implementation-defined and must be 0 on the cortex.
  196. */
  197. #define Mbz (0<<4)
  198. #define Fault 0x00000000 /* L[12] pte: unmapped */
  199. #define Coarse (Mbz|1) /* L1 */
  200. #define Section (Mbz|2) /* L1 1MB */
  201. #define Fine (Mbz|3) /* L1 */
  202. #define Large 0x00000001 /* L2 64KB */
  203. #define Small 0x00000002 /* L2 4KB */
  204. #define Tiny 0x00000003 /* L2 1KB: not in v7 */
  205. #define Buffered 0x00000004 /* L[12]: write-back not -thru */
  206. #define Cached 0x00000008 /* L[12] */
  207. #define Dom0 0
  208. #define Noaccess 0 /* AP, DAC */
  209. #define Krw 1 /* AP */
  210. /* armv7 deprecates AP[2] == 1 & AP[1:0] == 2 (Uro), prefers 3 (new in v7) */
  211. #define Uro 2 /* AP */
  212. #define Urw 3 /* AP */
  213. #define Client 1 /* DAC */
  214. #define Manager 3 /* DAC */
  215. #define AP(n, v) F((v), ((n)*2)+4, 2)
  216. #define L1AP(ap) (AP(3, (ap)))
  217. #define L2AP(ap) (AP(0, (ap))) /* armv7 */
  218. #define DAC(n, v) F((v), (n)*2, 2)
  219. #define HVECTORS 0xffff0000