rebootcode.s 4.7 KB

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  1. /*
  2. * omap3530 reboot code
  3. *
  4. * must fit in 11K to avoid stepping on PTEs; see mem.h.
  5. *
  6. * R11 is used by the loader as a temporary, so avoid it.
  7. */
  8. #include "arm.s"
  9. /*
  10. * Turn off MMU, then copy the new kernel to its correct location
  11. * in physical memory. Then jump to the start of the kernel.
  12. */
  13. /* main(PADDR(entry), PADDR(code), size); */
  14. TEXT main(SB), 1, $-4
  15. MOVW $setR12(SB), R12
  16. MOVW R0, p1+0(FP) /* destination, passed in R0 */
  17. MOVW CPSR, R0
  18. ORR $(PsrDirq|PsrDfiq), R0
  19. MOVW R0, CPSR /* splhi */
  20. BARRIERS
  21. PUTC('R')
  22. MRC CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
  23. BIC $CpACasa, R1 /* no speculative I access forwarding to mem */
  24. /* slow down */
  25. ORR $(CpACcachenopipe|CpACcp15serial|CpACcp15waitidle|CpACcp15pipeflush), R1
  26. MCR CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
  27. BARRIERS
  28. BL cachesoff(SB)
  29. /* now back in 29- or 26-bit addressing, mainly for SB */
  30. /* double mapping of PHYSDRAM & KZERO now in effect */
  31. /*
  32. * turn the MMU off
  33. */
  34. PUTC('e')
  35. /* first switch to PHYSDRAM-based addresses */
  36. DMB
  37. MOVW $KSEGM, R7 /* clear segment bits */
  38. MOVW $PHYSDRAM, R0 /* set dram base bits */
  39. BIC R7, R12 /* adjust SB */
  40. ORR R0, R12
  41. BL _r15warp(SB)
  42. /* don't care about saving R14; we're not returning */
  43. /*
  44. * now running in PHYSDRAM segment, not KZERO.
  45. */
  46. PUTC('b')
  47. SUB $12, SP /* paranoia */
  48. BL cacheuwbinv(SB)
  49. ADD $12, SP /* paranoia */
  50. /* invalidate mmu mappings */
  51. MOVW $KZERO, R0 /* some valid virtual address */
  52. MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
  53. BARRIERS
  54. PUTC('o')
  55. MRC CpSC, 0, R0, C(CpCONTROL), C(0)
  56. BIC $(CpCmmu|CpCdcache|CpCicache), R0
  57. MCR CpSC, 0, R0, C(CpCONTROL), C(0) /* mmu off */
  58. BARRIERS
  59. PUTC('o')
  60. /* copy in arguments from stack frame before moving stack */
  61. MOVW p2+4(FP), R4 /* phys source */
  62. MOVW n+8(FP), R5 /* byte count */
  63. MOVW p1+0(FP), R6 /* phys destination */
  64. /* set up a new stack for local vars and memmove args */
  65. MOVW R6, SP /* tiny trampoline stack */
  66. SUB $(0x20 + 4), SP /* back up before a.out header */
  67. // MOVW R14, -48(SP) /* store return addr */
  68. SUB $48, SP /* allocate stack frame */
  69. MOVW R5, 40(SP) /* save count */
  70. MOVW R6, 44(SP) /* save dest/entry */
  71. DELAY(printloop2, 2)
  72. PUTC('t')
  73. MOVW 40(SP), R5 /* restore count */
  74. MOVW 44(SP), R6 /* restore dest/entry */
  75. MOVW R6, 0(SP) /* normally saved LR goes here */
  76. MOVW R6, 4(SP) /* push dest */
  77. MOVW R6, R0
  78. MOVW R4, 8(SP) /* push src */
  79. MOVW R5, 12(SP) /* push size */
  80. BL memmove(SB)
  81. PUTC('-')
  82. /*
  83. * flush caches
  84. */
  85. BL cacheuwbinv(SB)
  86. PUTC('>')
  87. DELAY(printloopret, 1)
  88. PUTC('\r')
  89. DELAY(printloopnl, 1)
  90. PUTC('\n')
  91. /*
  92. * jump to kernel entry point. Note the true kernel entry point is
  93. * the virtual address KZERO|R6, but this must wait until
  94. * the MMU is enabled by the kernel in l.s
  95. */
  96. MOVW 44(SP), R6 /* restore R6 (dest/entry) */
  97. ORR R6, R6 /* NOP: avoid link bug */
  98. B (R6)
  99. PUTC('?')
  100. B 0(PC)
  101. /*
  102. * turn the caches off, double map PHYSDRAM & KZERO, invalidate TLBs, revert
  103. * to tiny addresses. upon return, it will be safe to turn off the mmu.
  104. */
  105. TEXT cachesoff(SB), 1, $-4
  106. MOVM.DB.W [R14,R1-R10], (R13) /* save regs on stack */
  107. MOVW CPSR, R0
  108. ORR $(PsrDirq|PsrDfiq), R0
  109. MOVW R0, CPSR
  110. BARRIERS
  111. SUB $12, SP /* paranoia */
  112. BL cacheuwbinv(SB)
  113. ADD $12, SP /* paranoia */
  114. MRC CpSC, 0, R0, C(CpCONTROL), C(0)
  115. BIC $(CpCicache|CpCdcache), R0
  116. MCR CpSC, 0, R0, C(CpCONTROL), C(0) /* caches off */
  117. BARRIERS
  118. /*
  119. * caches are off
  120. */
  121. /* invalidate stale TLBs before changing them */
  122. MOVW $KZERO, R0 /* some valid virtual address */
  123. MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
  124. BARRIERS
  125. /* redo double map of PHYSDRAM, KZERO */
  126. MOVW $PHYSDRAM, R3
  127. CMP $KZERO, R3
  128. BEQ noun2map
  129. MOVW $(L1+L1X(PHYSDRAM)), R4 /* address of PHYSDRAM's PTE */
  130. MOVW $PTEDRAM, R2 /* PTE bits */
  131. MOVW $DOUBLEMAPMBS, R5
  132. _ptrdbl:
  133. ORR R3, R2, R1 /* first identity-map 0 to 0, etc. */
  134. MOVW R1, (R4)
  135. ADD $4, R4 /* bump PTE address */
  136. ADD $MiB, R3 /* bump pa */
  137. SUB.S $1, R5
  138. BNE _ptrdbl
  139. noun2map:
  140. /*
  141. * flush stale TLB entries
  142. */
  143. BARRIERS
  144. MOVW $KZERO, R0 /* some valid virtual address */
  145. MCR CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
  146. BARRIERS
  147. /* switch back to PHYSDRAM addressing, mainly for SB */
  148. MOVW $KSEGM, R7 /* clear segment bits */
  149. MOVW $PHYSDRAM, R0 /* set dram base bits */
  150. BIC R7, R12 /* adjust SB */
  151. ORR R0, R12
  152. BIC R7, SP
  153. ORR R0, SP
  154. MOVM.IA.W (R13), [R14,R1-R10] /* restore regs from stack */
  155. MOVW $KSEGM, R0 /* clear segment bits */
  156. BIC R0, R14 /* adjust link */
  157. MOVW $PHYSDRAM, R0 /* set dram base bits */
  158. ORR R0, R14
  159. RET
  160. TEXT _r15warp(SB), 1, $-4
  161. BIC R7, R14 /* link */
  162. ORR R0, R14
  163. BIC R7, R13 /* SP */
  164. ORR R0, R13
  165. RET
  166. TEXT panic(SB), 1, $-4 /* stub */
  167. PUTC('?')
  168. RET
  169. TEXT pczeroseg(SB), 1, $-4 /* stub */
  170. RET
  171. #include "cache.v7.s"