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  1. beagleboard rev c3:
  2. cortex-a8 cpu: arm v7-a arch. rev 3, 500MHz, dual-issue
  3. OMAP3530-GP rev 2, CPU-OPP2 L3-165MHz
  4. OMAP3 Beagle board + LPDDR/NAND
  5. DRAM: 256 MB
  6. NAND: 256 MiB
  7. Board revision C
  8. Serial #784200230000000004013f790401d018
  9. igepv2 board:
  10. cortex-a8 cpu: arm v7-a arch. rev 3, 720MHz, dual-issue
  11. OMAP3530-GP ES3.1, CPU-OPP2 L3-165MHz
  12. IGEP v2.x rev. B + LPDDR/ONENAND
  13. DRAM: 512 MB
  14. Muxed OneNAND(DDP) 512MB 1.8V 16-bit (0x58)
  15. OneNAND version = 0x0031
  16. Chip support all block unlock
  17. Chip has 2 plane
  18. Scanning device for bad blocks
  19. Bad eraseblock 3134 at 0x187c0000
  20. Bad eraseblock 3135 at 0x187e0000
  21. OneNAND: 512 MB
  22. omap3530 SoC
  23. CORE_CLK runs at 26MHz
  24. see spruf98d from ti.com (/public/doc/ti/omap35x.ref.spruf98d.pdf)
  25. separate i & d tlbs, each 32 entries
  26. can invalidate i, d or both tlbs by { all, mva, or asid match }
  27. i & d L1 caches, 16K each, 4 ways, 64 sets, 64-byte lines
  28. i is VIPT, d is PIPT
  29. no `test and clean D & U all' operations
  30. no prefetching, no cache maintenance
  31. can invalidate i, d or both cache but not D & U all
  32. can invalidate entire i-cache only
  33. can clean or invalidate by set and way data/unified cache
  34. unified L2 PIPT cache, 256K, 8 ways, 512 sets, 64-byte lines
  35. no hardware cache coherence
  36. l3 interconnect firewalls are all off at boot time, except for a bit of
  37. secure ram
  38. sram at 0x40200000 size 1MB
  39. l4 interconnect firewalls seem to be sane at boot time
  40. ___
  41. The state of the Beagleboard/IGEPv2 (TI OMAP35 SoC, Cortex-A8) port.
  42. Plan 9 runs on the IGEPv2 and Gumstix Overo boards.
  43. On the Beagleboard, Plan 9 is not yet usable but it gets as far as
  44. trying to access the USB ethernet (since the Beagleboard has no
  45. built-in ethernet and must use USB ethernet).
  46. IGEP & Gumstix Ethernet
  47. The smsc9221 ethernet consumes a lot of system time. The design
  48. decision to use fifos rather than buffer rings and to not incorporate
  49. dma into the ethernet controller is probably responsible. With only a
  50. single core, running the 9221 consumes a lot of the available CPU
  51. time. It's probably worth trying to use the system dma controller again.
  52. USB
  53. The ohci and ehci controllers are seen, but no devices yet.
  54. There are four USB errata that need to be looked into for the igepv2
  55. (silicon 3.1) at least. From the omap3530 errata (rev e):
  56. - 3.1.1.130 only one usb dma channel (rx or tx) can be active
  57. at one time: use interrupt mode instead
  58. - 3.1.1.144 otg soft reset doesn't work right
  59. - 3.1.1.183 ohci and ehci controllers cannot work concurrently
  60. - §3.1.3 usb limitations: all ports must be configured to identical speeds
  61. (high vs full/low)
  62. Flash
  63. access to nand flash would be handy for nvram and paqfs file systems.
  64. In the flash, x-loader occupies up to 0x20000, then u-boot from
  65. 0x80000 to 0x1e0000, and there's a linux kernel after that (if you
  66. care). The beagle's flash chip is a micron pop 2Gb nand
  67. mt29f2g16abdhc-et (physical marking jw256), and the igep's is a
  68. samsung onenand.
  69. VFPv3 Floating Point
  70. The Cortex-A8 has VFPv3 floating point, which uses different opcodes
  71. than 5c/5l currently generate. New 5c or 5l is in the works.
  72. Video
  73. The display subsystem for omap3 (dss) is divided into 3 parts, called lcd,
  74. video and dsi (ignoring the various accelerators). The system only
  75. supports the lcd via dvi interface so far because it's the only one we
  76. have been able to test. 1280x1024x16 is the default resolution, this
  77. might be changed. Writing to /dev/dssctl (e.g., echo 1024x768x16
  78. >/dev/dssctl) changes the resolution. Currently the system does not
  79. use the rfbi since it seems like an unnecessary optimisation at this
  80. point. Per Odlund wrote the first draft of the video driver for a
  81. Google Summer of Code project.
  82. Stray Interrupts
  83. IRQs 56 and 57 are I2C. 83, 86 and 94 are MMC.
  84. ___
  85. The code is fairly heavy-handed with the use of barrier instructions
  86. (BARRIERS in assembler, coherence in C), partly in reaction to bad
  87. experience doing Power PC ports, but also just as precautions against
  88. modern processors, which may feel free to execute instructions out of
  89. order or some time later, store to memory out of order or some time
  90. later, otherwise break the model of traditional sequential processors,
  91. or any combination of the above.
  92. ___
  93. There are a few rough edges:
  94. - the clock.c scheduling rate (HZ) is quite approximate. The OMAP
  95. timers are complex, but one could eventually do better (or just let
  96. timesync compensate).
  97. - User processes are limited to 512MB virtual (mainly by the IGEPv2 Ethernet
  98. being at 0x2c000000), which isn't a problem since Beagleboards only
  99. have 256MB of dram and IGEPv2s have 512MB, and we don't want to swap.
  100. - might use ucalloc.c to allocate uncached scratch space for generated code
  101. in coproc.c.
  102. - the C implementation of cache primitives failed with mmu off; still true?
  103. - unlock, setup: protect module register target APE (PM_RT) per spruf98c §1.6.7
  104. - setup mpp (multi-purpose pins)?
  105. ___
  106. memory map (mostly from omap35x ref)
  107. hex addr size what
  108. ----
  109. 0 16MB physical address of flash registers, buffers
  110. 20000000 16MB virtual address of flash registers, buffers
  111. 2c000000 ? smc 9221 ethernet
  112. 38000000 16MB 256MB (beagle) or 512MB (igep) nand flash mapped here
  113. 40000000 112K boot rom, top of user space
  114. 40200000 64K sram
  115. 48000000 16MB L4 core
  116. 48002000 8K system control (scm)
  117. 48004000 16K clock manager
  118. 48040000 8K L4-core config
  119. 48050000 4K graphics
  120. 48062000 4K usb tll
  121. 48064000 1K usb uhh_config
  122. 48064400 1K ohci
  123. 48064800 1K ehci
  124. 4806a000 8K 8250 uart0
  125. 4806c000 8K 8250 uart1
  126. 48086000 4K gptimer10
  127. 48088000 4K gptimer11
  128. 4809c000 8K mmc/sd goo
  129. 480ab000 8K hs usb otg
  130. 480ad000 8K mmc/sd goo
  131. 480b4000 8K mmc/sd goo
  132. 480c7000 device intr controller
  133. 48200000 2K intr ctlr (intc)
  134. 48300000 256K L4-wakeup
  135. 48304000 4K gptimer12
  136. 48318000 8K gptimer1
  137. 49000000 1MB L4 peripherals
  138. 49020000 8K 8250 uart2 (with exposed connector for console)
  139. 49032000 4K gptimer2
  140. 49034000 4K gptimer3
  141. 49040000 4K gptimer9
  142. 49050000 8K gpio2
  143. 49058000 8K gpio6
  144. 50000000 64K graphics accelerator
  145. 68000000 1K L3 config (rt)
  146. 68004000 1K L3 hs usb host
  147. 68004400 1K L3 hs usb otg
  148. 68005400 1K L3 graphics
  149. 68006800 1K L4-core config
  150. 68010000 L3 protection mechanism
  151. 6e000000 ? gpmc
  152. 80000000 256MB dram on beagle
  153. 512MB dram on igep
  154. c0000000 1GB kernel virtual space, mapped to 80000000
  155. apparently the vector address (0 or 0xffff0000) is virtual,
  156. so we're expected to map it to ram.