caches-v7.c 2.1 KB

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  1. /*
  2. * caches defined by arm v7 architecture
  3. */
  4. #include "u.h"
  5. #include "../port/lib.h"
  6. #include "mem.h"
  7. #include "dat.h"
  8. #include "fns.h"
  9. #include "../port/error.h"
  10. #include "io.h"
  11. #include "arm.h"
  12. static char *
  13. l1iptype(uint type)
  14. {
  15. static char *types[] = {
  16. "reserved",
  17. "asid-tagged VIVT",
  18. "VIPT",
  19. "PIPT",
  20. };
  21. if (type >= nelem(types) || types[type] == nil)
  22. return "GOK";
  23. return types[type];
  24. }
  25. static char *catype[] = {
  26. "none,",
  27. "i,",
  28. "d,",
  29. "split i&d,",
  30. "unified,",
  31. "gok,",
  32. "gok,",
  33. "gok,",
  34. };
  35. void
  36. cacheinfo(int level, Memcache *cp, int ext, int type)
  37. {
  38. ulong setsways;
  39. memset(cp, 0, sizeof *cp);
  40. if (type == Nocache)
  41. return;
  42. cp->level = level;
  43. cp->type = type;
  44. cp->external = ext;
  45. if (level == 2) { /* external PL310 */
  46. allcache->info(cp);
  47. setsways = cp->setsways;
  48. } else {
  49. /* select internal cache level */
  50. cpwrsc(CpIDcssel, CpID, CpIDid, 0, (level - 1) << 1);
  51. setsways = cprdsc(CpIDcsize, CpID, CpIDid, 0);
  52. cp->l1ip = cpctget();
  53. cp->nways = ((setsways >> 3) & MASK(10)) + 1;
  54. cp->nsets = ((setsways >> 13) & MASK(15)) + 1;
  55. cp->log2linelen = (setsways & MASK(2)) + 2 + 2;
  56. }
  57. cp->linelen = 1 << cp->log2linelen;
  58. cp->setsways = setsways;
  59. cp->setsh = cp->log2linelen;
  60. cp->waysh = 32 - log2(cp->nways);
  61. }
  62. void
  63. allcacheinfo(Memcache *mc)
  64. {
  65. int n;
  66. ulong lvl;
  67. lvl = cprdsc(CpIDcsize, CpID, CpIDidct, CpIDclvlid);
  68. n = 1;
  69. for (lvl &= MASK(21); lvl; lvl >>= 3)
  70. cacheinfo(n, &mc[n], Intcache, lvl & MASK(3));
  71. // cacheinfo(2, &mc[2], Extcache, Unified); /* PL310 */
  72. }
  73. void
  74. prcachecfg(void)
  75. {
  76. int cache;
  77. Memcache *mc;
  78. for (cache = 1; cache < 8 && cachel[cache].type; cache++) {
  79. mc = &cachel[cache];
  80. iprint("l%d: %s %-10s %2d ways %4d sets %d bytes/line; can W[",
  81. mc->level, mc->external? "ext": "int", catype[mc->type],
  82. mc->nways, mc->nsets, mc->linelen);
  83. if (mc->linelen != CACHELINESZ)
  84. iprint(" *should* be %d", CACHELINESZ);
  85. if (mc->setsways & Cawt)
  86. iprint("T");
  87. if (mc->setsways & Cawb)
  88. iprint("B");
  89. if (mc->setsways & Cawa)
  90. iprint("A");
  91. iprint("]");
  92. if (cache == 1)
  93. iprint("; l1-i %s", l1iptype((mc->l1ip >> 14) & MASK(2)));
  94. iprint("\n");
  95. }
  96. }