dat.h 9.1 KB

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  1. /*
  2. * Time.
  3. *
  4. * HZ should divide 1000 evenly, ideally.
  5. * 100, 125, 200, 250 and 333 are okay.
  6. */
  7. #define HZ 100 /* clock frequency */
  8. #define MS2HZ (1000/HZ) /* millisec per clock tick */
  9. #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
  10. enum {
  11. Mhz = 1000 * 1000,
  12. Dogsectimeout = 4, /* must be ≤ 34 s. to fit in a ulong */
  13. };
  14. /*
  15. * More accurate time
  16. */
  17. #define MS2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000))
  18. #define US2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000000))
  19. #define CONSOLE 0
  20. typedef struct Conf Conf;
  21. typedef struct Confmem Confmem;
  22. typedef struct FPsave FPsave;
  23. typedef struct ISAConf ISAConf;
  24. typedef struct Isolated Isolated;
  25. typedef struct Label Label;
  26. typedef struct Lock Lock;
  27. typedef struct Lowmemcache Lowmemcache;
  28. typedef struct Memcache Memcache;
  29. typedef struct MMMU MMMU;
  30. typedef struct Mach Mach;
  31. typedef u32int Mreg; /* Msr - bloody UART */
  32. typedef struct Notsave Notsave;
  33. typedef struct Page Page;
  34. typedef struct Pcisiz Pcisiz;
  35. typedef struct Pcidev Pcidev;
  36. typedef struct PhysUart PhysUart;
  37. typedef struct PMMU PMMU;
  38. typedef struct Proc Proc;
  39. typedef u32int PTE;
  40. typedef struct Soc Soc;
  41. typedef struct Uart Uart;
  42. typedef struct Ureg Ureg;
  43. typedef uvlong Tval;
  44. #pragma incomplete Pcidev
  45. #pragma incomplete Ureg
  46. #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */
  47. /*
  48. * parameters for sysproc.c
  49. */
  50. #define AOUT_MAGIC (E_MAGIC)
  51. struct Lock
  52. {
  53. ulong key;
  54. u32int sr;
  55. uintptr pc;
  56. Proc* p;
  57. Mach* m;
  58. int isilock;
  59. };
  60. struct Label
  61. {
  62. uintptr sp;
  63. uintptr pc;
  64. };
  65. enum {
  66. Maxfpregs = 32, /* could be 16 or 32, see Mach.fpnregs */
  67. Nfpctlregs = 16,
  68. };
  69. /*
  70. * emulated or vfp3 floating point
  71. */
  72. struct FPsave
  73. {
  74. ulong status;
  75. ulong control;
  76. /*
  77. * vfp3 with ieee fp regs; uvlong is sufficient for hardware but
  78. * each must be able to hold an Internal from fpi.h for sw emulation.
  79. */
  80. ulong regs[Maxfpregs][3];
  81. int fpstate;
  82. uintptr pc; /* of failed fp instr. */
  83. };
  84. /*
  85. * FPsave.fpstate
  86. */
  87. enum
  88. {
  89. FPinit,
  90. FPactive,
  91. FPinactive,
  92. FPemu,
  93. /* bit or'd with the state */
  94. FPillegal= 0x100,
  95. };
  96. struct Confmem
  97. {
  98. uintptr base;
  99. usize npage;
  100. uintptr limit;
  101. uintptr kbase;
  102. uintptr klimit;
  103. };
  104. struct Conf
  105. {
  106. ulong nmach; /* processors */
  107. ulong nproc; /* processes */
  108. Confmem mem[1]; /* physical memory */
  109. ulong npage; /* total physical pages of memory */
  110. usize upages; /* user page pool */
  111. ulong copymode; /* 0 is copy on write, 1 is copy on reference */
  112. ulong ialloc; /* max interrupt time allocation in bytes */
  113. ulong pipeqsize; /* size in bytes of pipe queues */
  114. ulong nimage; /* number of page cache image headers */
  115. ulong nswap; /* number of swap pages */
  116. int nswppo; /* max # of pageouts per segment pass */
  117. ulong hz; /* processor cycle freq */
  118. ulong mhz;
  119. int monitor; /* flag */
  120. };
  121. /*
  122. * things saved in the Proc structure during a notify
  123. */
  124. struct Notsave {
  125. int emptiness;
  126. };
  127. /*
  128. * MMU stuff in Mach.
  129. */
  130. struct MMMU
  131. {
  132. PTE* mmul1; /* l1 for this processor */
  133. int mmul1lo;
  134. int mmul1hi;
  135. int mmupid;
  136. };
  137. /*
  138. * MMU stuff in proc
  139. */
  140. #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */
  141. struct PMMU
  142. {
  143. Page* mmul2;
  144. Page* mmul2cache; /* free mmu pages */
  145. };
  146. #include "../port/portdat.h"
  147. struct Mach
  148. {
  149. /* offsets known to asm */
  150. int machno; /* physical id of processor */
  151. uintptr splpc; /* pc of last caller to splhi */
  152. Proc* proc; /* current process */
  153. MMMU;
  154. /* end of offsets known to asm */
  155. int flushmmu; /* flush current proc mmu state */
  156. ulong ticks; /* of the clock since boot time */
  157. Label sched; /* scheduler wakeup */
  158. Lock alarmlock; /* access to alarm list */
  159. void* alarm; /* alarms bound to this clock */
  160. int inclockintr;
  161. Proc* readied; /* for runproc */
  162. ulong schedticks; /* next forced context switch */
  163. int cputype;
  164. ulong delayloop;
  165. /* stats */
  166. int tlbfault;
  167. int tlbpurge;
  168. int pfault;
  169. int cs;
  170. int syscall;
  171. int load;
  172. int intr;
  173. uvlong fastclock; /* last sampled value */
  174. uvlong inidle; /* time spent in idlehands() */
  175. ulong spuriousintr;
  176. int lastintr;
  177. int ilockdepth;
  178. Perf perf; /* performance counters */
  179. int probing; /* probeaddr() state */
  180. int trapped;
  181. Lock probelock;
  182. int inidlehands;
  183. int cpumhz;
  184. uvlong cpuhz; /* speed of cpu */
  185. uvlong cyclefreq; /* Frequency of user readable cycle counter */
  186. /* vfp3 fpu */
  187. int havefp;
  188. int havefpvalid;
  189. int fpon;
  190. int fpconfiged;
  191. int fpnregs;
  192. ulong fpscr; /* sw copy */
  193. int fppid; /* pid of last fault */
  194. uintptr fppc; /* addr of last fault */
  195. int fpcnt; /* how many consecutive at that addr */
  196. /* save areas for exceptions, hold R0-R4 */
  197. u32int sfiq[5];
  198. u32int sirq[5];
  199. u32int sund[5];
  200. u32int sabt[5];
  201. u32int smon[5]; /* probably not needed */
  202. u32int ssys[5];
  203. int stack[1];
  204. };
  205. /*
  206. * Fake kmap.
  207. */
  208. typedef void KMap;
  209. #define VA(k) ((uintptr)(k))
  210. #define kmap(p) (KMap*)((p)->pa|kseg0)
  211. #define kunmap(k)
  212. struct
  213. {
  214. Lock;
  215. int machs; /* bitmap of active CPUs */
  216. int wfi; /* bitmap of CPUs in WFI state */
  217. int stopped; /* bitmap of CPUs stopped */
  218. int exiting; /* shutdown */
  219. int ispanic; /* shutdown in response to a panic */
  220. int thunderbirdsarego; /* lets the added processors continue to schedinit */
  221. }active;
  222. extern register Mach* m; /* R10 */
  223. extern register Proc* up; /* R9 */
  224. /* an object guaranteed to be in its own cache line */
  225. typedef uchar Cacheline[CACHELINESZ];
  226. struct Isolated {
  227. Cacheline c0;
  228. ulong word;
  229. Cacheline c1;
  230. };
  231. extern Memcache cachel[]; /* arm arch v7 supports 1-7 */
  232. extern ulong intrcount[MAXMACH];
  233. extern int irqtooearly;
  234. extern uintptr kseg0;
  235. extern Isolated l1ptstable;
  236. extern uchar *l2pages;
  237. extern Mach* machaddr[MAXMACH];
  238. extern ulong memsize;
  239. extern int navailcpus;
  240. extern int normalprint;
  241. /*
  242. * a parsed plan9.ini line
  243. */
  244. #define NISAOPT 8
  245. struct ISAConf {
  246. char *type;
  247. ulong port;
  248. int irq;
  249. ulong dma;
  250. ulong mem;
  251. ulong size;
  252. ulong freq;
  253. int nopt;
  254. char *opt[NISAOPT];
  255. };
  256. #define MACHP(n) machaddr[n]
  257. /*
  258. * Horrid. But the alternative is 'defined'.
  259. */
  260. #ifdef _DBGC_
  261. #define DBGFLG (dbgflg[_DBGC_])
  262. #else
  263. #define DBGFLG (0)
  264. #endif /* _DBGC_ */
  265. int vflag;
  266. extern char dbgflg[256];
  267. #define dbgprint print /* for now */
  268. /*
  269. * hardware info about a device
  270. */
  271. typedef struct {
  272. ulong port;
  273. int size;
  274. } Devport;
  275. struct DevConf
  276. {
  277. ulong intnum; /* interrupt number */
  278. char *type; /* card type, malloced */
  279. int nports; /* Number of ports */
  280. Devport *ports; /* The ports themselves */
  281. };
  282. /* characteristics of a given arm cache level */
  283. struct Memcache {
  284. uint waysh; /* shifts for set/way register */
  285. uint setsh;
  286. uint log2linelen;
  287. uint level; /* 1 is nearest processor, 2 further away */
  288. uint type;
  289. uint external; /* flag */
  290. uint l1ip; /* l1 I policy */
  291. uint nways; /* associativity */
  292. uint nsets;
  293. uint linelen; /* bytes per cache line */
  294. uint setsways;
  295. };
  296. enum Cachetype {
  297. Nocache,
  298. Ionly,
  299. Donly,
  300. Splitid,
  301. Unified,
  302. };
  303. enum {
  304. Intcache,
  305. Extcache,
  306. };
  307. /*
  308. * characteristics of cache level, kept at low, fixed address (CACHECONF).
  309. * all offsets are known to cache.v7.s.
  310. */
  311. struct Lowmemcache {
  312. uint l1waysh; /* shifts for set/way register */
  313. uint l1setsh;
  314. uint l2waysh;
  315. uint l2setsh;
  316. };
  317. /*
  318. * cache capabilities. write-back vs write-through is controlled
  319. * by the Buffered bit in PTEs.
  320. *
  321. * see cache.v7.s and Memcache in dat.h
  322. */
  323. enum {
  324. Cawt = 1 << 31,
  325. Cawb = 1 << 30,
  326. Cara = 1 << 29,
  327. Cawa = 1 << 28,
  328. };
  329. /* non-architectural L2 cache */
  330. typedef struct Cacheimpl Cacheimpl;
  331. struct Cacheimpl {
  332. void (*info)(Memcache *);
  333. void (*on)(void);
  334. void (*off)(void);
  335. void (*inv)(void);
  336. void (*wb)(void);
  337. void (*wbinv)(void);
  338. void (*invse)(void *, int);
  339. void (*wbse)(void *, int);
  340. void (*wbinvse)(void *, int);
  341. };
  342. /* extern */ Cacheimpl *l2cache, *allcache, *nocache, *l1cache;
  343. enum Dmamode {
  344. Const,
  345. Postincr,
  346. Index,
  347. Index2,
  348. };
  349. /* pmu = power management unit */
  350. enum Irqs {
  351. /*
  352. * 1st 32 gic irqs reserved for cpu; private interrupts.
  353. * 0—15 are software-generated by other cpus;
  354. * 16—31 are private peripheral intrs.
  355. */
  356. Cpu0irq = 0,
  357. Cpu1irq,
  358. /* ... */
  359. Cpu15irq = 15,
  360. Glbtmrirq = 27,
  361. Loctmrirq = 29,
  362. Wdtmrirq = 30,
  363. /* shared interrupts */
  364. Ctlr0base = (1+0)*32, /* primary ctlr */
  365. Tn0irq = Ctlr0base + 0, /* tegra timers */
  366. Tn1irq = Ctlr0base + 1,
  367. Rtcirq = Ctlr0base + 2,
  368. Ctlr1base = (1+1)*32, /* secondary ctlr */
  369. Uartirq = Ctlr1base + 4,
  370. Tn2irq = Ctlr1base + 9, /* tegra timers */
  371. Tn3irq = Ctlr1base + 10,
  372. /* +24 is cpu0_pmu_intr, +25 is cpu1_pum_intr */
  373. Ctlr2base = (1+2)*32, /* ternary ctlr */
  374. Extpmuirq = Ctlr2base + 22,
  375. Ctlr3base = (1+3)*32, /* quad ctlr */
  376. Pcieirq = Ctlr3base + 2,
  377. };
  378. struct Soc { /* addr's of SoC controllers */
  379. uintptr clkrst;
  380. uintptr power;
  381. uintptr exceptvec;
  382. uintptr sema;
  383. uintptr l2cache;
  384. uintptr flow;
  385. /* private memory region */
  386. uintptr scu;
  387. uintptr intr; /* `cpu interface' */
  388. /* private-peripheral-interrupt cortex-a clocks */
  389. uintptr glbtmr;
  390. uintptr loctmr;
  391. uintptr intrdist;
  392. uintptr uart[5];
  393. /* shared-peripheral-interrupt tegra2 clocks */
  394. uintptr rtc; /* real-time clock */
  395. uintptr tmr[4];
  396. uintptr µs;
  397. uintptr pci;
  398. uintptr ether;
  399. uintptr ehci;
  400. uintptr ide;
  401. uintptr nand;
  402. uintptr nor;
  403. uintptr spi[4];
  404. uintptr twsi;
  405. uintptr mmc[4];
  406. uintptr gpio[7];
  407. } soc;
  408. extern Soc soc;