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  1. this is a plan 9 port to the Trimslice with tegra2 soc: dual-core,
  2. dual-issue 1GHz Cortex-A9 system (v7a arch).
  3. dram is 1GB at 0.
  4. linux believes that u-boot runs in the bottom 4MB.
  5. the l2 cache is a non-architectural bag nailed on the side.
  6. mp arm systems have a generic interrupt controller; this one is gic v1(!).
  7. vfp 3 floating-point is present.
  8. section numbers (§) are in the tegra 2 tech. ref. man.
  9. for a minimal cpu server, need these devices to work:
  10. clock signals §5 (leave to u-boot),
  11. pad mux + gpio crap §8, §11 and §18 (leave to u-boot),
  12. ☑ 1 cpu §13,
  13. ☑ uart (16[45]50) §22,
  14. ☑ gic (gic.v1.pdf),
  15. ☑ clock §6—7,
  16. ☑ ether8169 via pcie §31.
  17. then add these:
  18. ☑ 2nd cpu (cortex.a9.mpcore.pdf),
  19. ☑ l2 cache (l2cache.pl310.pdf, errata),
  20. ☑ fpu (cortex.a9.fp.pdf),
  21. ☑ user profiling,
  22. kprof,
  23. in-line 64-bit arithmetic,
  24. eventually might want:
  25. usb (e.g., for sata) §26,
  26. nor flash §17,
  27. video §29,
  28. and the really horrid ones:
  29. nand flash §16,
  30. mmc §25.
  31. physical memory map
  32. 0 1GB ram
  33. 40000000 256K iram (audio/video memory)
  34. 50000000 cortex-a9 cpu regs, periphbase, intr distrib, memsel,
  35. l2 cache
  36. 54000000 graphics regs
  37. 58000000 gart (graphics window)
  38. 60000000 256MB ppsb bus dev regs, including semas, intr ctlr, dma,
  39. arm7 cache, gpio, except. vects
  40. 70000000 256MB apc bus regs, including uarts, nand, nor, spi, rtc
  41. 80000000 1GB ahb extern mem, pcie for cpu only
  42. 90000000-97ffffff pcie 0 mem(?)
  43. a0000000-a7ffffff pcie 0 prefetch mem, includes rtl8111dl ether(?)
  44. a0020000 ether region 4
  45. a0024000 ether region 2
  46. c0000000 256MB ahb bus virtual b0000000
  47. c3000000-c80007ff 81MB ide, usb, sata, mmc
  48. d0000000 256MB nor flash virtual 40000000
  49. f000f000 4K mmu tlb
  50. fff00000 48K irom boot code
  51. ffff0000 64K high vectors
  52. use 0xc0000000 as KZERO.