io.h 7.0 KB

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  1. /*
  2. * This file is part of the UCB release of Plan 9. It is subject to the license
  3. * terms in the LICENSE file found in the top-level directory of this
  4. * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. No
  5. * part of the UCB release of Plan 9, including this file, may be copied,
  6. * modified, propagated, or distributed except according to the terms contained
  7. * in the LICENSE file.
  8. */
  9. enum {
  10. VectorNMI = 2, /* non-maskable interrupt */
  11. VectorBPT = 3, /* breakpoint */
  12. VectorUD = 6, /* invalid opcode exception */
  13. VectorCNA = 7, /* coprocessor not available */
  14. Vector2F = 8, /* double fault */
  15. VectorCSO = 9, /* coprocessor segment overrun */
  16. VectorPF = 14, /* page fault */
  17. Vector15 = 15, /* reserved */
  18. VectorCERR = 16, /* coprocessor error */
  19. VectorPIC = 32, /* external i8259 interrupts */
  20. IrqCLOCK = 0,
  21. IrqKBD = 1,
  22. IrqUART1 = 3,
  23. IrqUART0 = 4,
  24. IrqPCMCIA = 5,
  25. IrqFLOPPY = 6,
  26. IrqLPT = 7,
  27. IrqIRQ7 = 7,
  28. IrqAUX = 12, /* PS/2 port */
  29. IrqIRQ13 = 13, /* coprocessor on 386 */
  30. IrqATA0 = 14,
  31. IrqATA1 = 15,
  32. MaxIrqPIC = 15,
  33. VectorLAPIC = VectorPIC+16, /* local APIC interrupts */
  34. IrqLINT0 = VectorLAPIC+0,
  35. IrqLINT1 = VectorLAPIC+1,
  36. IrqTIMER = VectorLAPIC+2,
  37. IrqERROR = VectorLAPIC+3,
  38. IrqPCINT = VectorLAPIC+4,
  39. IrqSPURIOUS = VectorLAPIC+15,
  40. MaxIrqLAPIC = VectorLAPIC+15,
  41. VectorSYSCALL = 64,
  42. VectorAPIC = 65, /* external APIC interrupts */
  43. MaxVectorAPIC = 255,
  44. };
  45. enum {
  46. IdtPIC = 32, /* external i8259 interrupts */
  47. IdtLINT0 = 48, /* local APIC interrupts */
  48. IdtLINT1 = 49,
  49. IdtTIMER = 50,
  50. IdtERROR = 51,
  51. IdtPCINT = 52,
  52. IdtIPI = 62,
  53. IdtSPURIOUS = 63,
  54. IdtSYSCALL = 64,
  55. IdtIOAPIC = 65, /* external APIC interrupts */
  56. IdtMAX = 255,
  57. };
  58. typedef struct Vkey {
  59. int tbdf; /* pci: ioapic or msi sources */
  60. int irq; /* 8259-emulating sources */
  61. } Vkey;
  62. typedef struct Vctl {
  63. Vctl* next; /* handlers on this vector */
  64. int isintr; /* interrupt or fault/trap */
  65. Vkey; /* source-specific key; tbdf for pci */
  66. void (*f)(Ureg*, void*); /* handler to call */
  67. void* a; /* argument to call it with */
  68. char name[KNAMELEN]; /* of driver */
  69. char *type;
  70. int (*isr)(int); /* get isr bit for this irq */
  71. int (*eoi)(int); /* eoi */
  72. int (*mask)(Vkey*, int); /* interrupt enable returns masked vector */
  73. int vno;
  74. } Vctl;
  75. typedef struct ACVctl {
  76. char* (*f)(Ureg*,void*);
  77. void* a;
  78. int vno;
  79. char name[KNAMELEN]; /* of driver */
  80. } ACVctl;
  81. enum {
  82. BusCBUS = 0, /* Corollary CBUS */
  83. BusCBUSII, /* Corollary CBUS II */
  84. BusEISA, /* Extended ISA */
  85. BusFUTURE, /* IEEE Futurebus */
  86. BusINTERN, /* Internal bus */
  87. BusISA, /* Industry Standard Architecture */
  88. BusMBI, /* Multibus I */
  89. BusMBII, /* Multibus II */
  90. BusMCA, /* Micro Channel Architecture */
  91. BusMPI, /* MPI */
  92. BusMPSA, /* MPSA */
  93. BusNUBUS, /* Apple Macintosh NuBus */
  94. BusPCI, /* Peripheral Component Interconnect */
  95. BusPCMCIA, /* PC Memory Card International Association */
  96. BusTC, /* DEC TurboChannel */
  97. BusVL, /* VESA Local bus */
  98. BusVME, /* VMEbus */
  99. BusXPRESS, /* Express System Bus */
  100. };
  101. #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
  102. #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
  103. #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
  104. #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
  105. #define BUSTYPE(tbdf) ((tbdf)>>24)
  106. #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
  107. #define BUSUNKNOWN (-1)
  108. enum {
  109. MaxEISA = 16,
  110. CfgEISA = 0xC80,
  111. };
  112. /*
  113. * PCI support code.
  114. */
  115. enum { /* type 0 and type 1 pre-defined header */
  116. PciVID = 0x00, /* vendor ID */
  117. PciDID = 0x02, /* device ID */
  118. PciPCR = 0x04, /* command */
  119. PciPSR = 0x06, /* status */
  120. PciRID = 0x08, /* revision ID */
  121. PciCCRp = 0x09, /* programming interface class code */
  122. PciCCRu = 0x0A, /* sub-class code */
  123. PciCCRb = 0x0B, /* base class code */
  124. PciCLS = 0x0C, /* cache line size */
  125. PciLTR = 0x0D, /* latency timer */
  126. PciHDT = 0x0E, /* header type */
  127. PciBST = 0x0F, /* BIST */
  128. PciBAR0 = 0x10, /* base address */
  129. PciBAR1 = 0x14,
  130. PciCP = 0x34, /* capabilities pointer */
  131. PciINTL = 0x3C, /* interrupt line */
  132. PciINTP = 0x3D, /* interrupt pin */
  133. };
  134. enum { /* type 0 pre-defined header */
  135. PciCIS = 0x28, /* cardbus CIS pointer */
  136. PciSVID = 0x2C, /* subsystem vendor ID */
  137. PciSID = 0x2E, /* cardbus CIS pointer */
  138. PciEBAR0 = 0x30, /* expansion ROM base address */
  139. PciMGNT = 0x3E, /* burst period length */
  140. PciMLT = 0x3F, /* maximum latency between bursts */
  141. };
  142. enum { /* type 1 pre-defined header */
  143. PciPBN = 0x18, /* primary bus number */
  144. PciSBN = 0x19, /* secondary bus number */
  145. PciUBN = 0x1A, /* subordinate bus number */
  146. PciSLTR = 0x1B, /* secondary latency timer */
  147. PciIBR = 0x1C, /* I/O base */
  148. PciILR = 0x1D, /* I/O limit */
  149. PciSPSR = 0x1E, /* secondary status */
  150. PciMBR = 0x20, /* memory base */
  151. PciMLR = 0x22, /* memory limit */
  152. PciPMBR = 0x24, /* prefetchable memory base */
  153. PciPMLR = 0x26, /* prefetchable memory limit */
  154. PciPUBR = 0x28, /* prefetchable base upper 32 bits */
  155. PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
  156. PciIUBR = 0x30, /* I/O base upper 16 bits */
  157. PciIULR = 0x32, /* I/O limit upper 16 bits */
  158. PciEBAR1 = 0x28, /* expansion ROM base address */
  159. PciBCR = 0x3E, /* bridge control register */
  160. };
  161. enum { /* type 2 pre-defined header */
  162. PciCBExCA = 0x10,
  163. PciCBSPSR = 0x16,
  164. PciCBPBN = 0x18, /* primary bus number */
  165. PciCBSBN = 0x19, /* secondary bus number */
  166. PciCBUBN = 0x1A, /* subordinate bus number */
  167. PciCBSLTR = 0x1B, /* secondary latency timer */
  168. PciCBMBR0 = 0x1C,
  169. PciCBMLR0 = 0x20,
  170. PciCBMBR1 = 0x24,
  171. PciCBMLR1 = 0x28,
  172. PciCBIBR0 = 0x2C, /* I/O base */
  173. PciCBILR0 = 0x30, /* I/O limit */
  174. PciCBIBR1 = 0x34, /* I/O base */
  175. PciCBILR1 = 0x38, /* I/O limit */
  176. PciCBSVID = 0x40, /* subsystem vendor ID */
  177. PciCBSID = 0x42, /* subsystem ID */
  178. PciCBLMBAR = 0x44, /* legacy mode base address */
  179. };
  180. /* capabilities */
  181. enum {
  182. PciCapPMG = 0x01, /* power management */
  183. PciCapAGP = 0x02,
  184. PciCapVPD = 0x03, /* vital product data */
  185. PciCapSID = 0x04, /* slot id */
  186. PciCapMSI = 0x05,
  187. PciCapCHS = 0x06, /* compact pci hot swap */
  188. PciCapPCIX = 0x07,
  189. PciCapHTC = 0x08, /* hypertransport irq conf */
  190. PciCapVND = 0x09, /* vendor specific information */
  191. PciCapPCIe = 0x10,
  192. PciCapMSIX = 0x11,
  193. PciCapSATA = 0x12,
  194. PciCapHSW = 0x0c, /* hot swap */
  195. };
  196. typedef struct Pcisiz Pcisiz;
  197. struct Pcisiz
  198. {
  199. Pcidev* dev;
  200. int siz;
  201. int bar;
  202. };
  203. typedef struct Pcidev Pcidev;
  204. struct Pcidev
  205. {
  206. int tbdf; /* type+bus+device+function */
  207. ushort vid; /* vendor ID */
  208. ushort did; /* device ID */
  209. ushort pcr;
  210. uchar rid;
  211. uchar ccrp;
  212. uchar ccru;
  213. uchar ccrb;
  214. uchar cls;
  215. uchar ltr;
  216. struct {
  217. uint32_t bar; /* base address */
  218. int size;
  219. } mem[6];
  220. struct {
  221. uint32_t bar;
  222. int size;
  223. } rom;
  224. uchar intl; /* interrupt line */
  225. Pcidev* list;
  226. Pcidev* link; /* next device on this bno */
  227. Pcidev* bridge; /* down a bus */
  228. struct {
  229. uint32_t bar;
  230. int size;
  231. } ioa, mema;
  232. };
  233. #define PCIWINDOW 0
  234. #define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
  235. #define ISAWINDOW 0
  236. #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
  237. #pragma varargck type "T" int