ahci.h 6.2 KB

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  1. /*
  2. * advanced host controller interface (sata)
  3. * © 2007 coraid, inc
  4. */
  5. /* ata errors */
  6. enum {
  7. Emed = 1<<0, /* media error */
  8. Enm = 1<<1, /* no media */
  9. Eabrt = 1<<2, /* abort */
  10. Emcr = 1<<3, /* media change request */
  11. Eidnf = 1<<4, /* no user-accessible address */
  12. Emc = 1<<5, /* media change */
  13. Eunc = 1<<6, /* data error */
  14. Ewp = 1<<6, /* write protect */
  15. Eicrc = 1<<7, /* interface crc error */
  16. Efatal = Eidnf|Eicrc, /* must sw reset */
  17. };
  18. /* ata status */
  19. enum {
  20. ASerr = 1<<0, /* error */
  21. ASdrq = 1<<3, /* request */
  22. ASdf = 1<<5, /* fault */
  23. ASdrdy = 1<<6, /* ready */
  24. ASbsy = 1<<7, /* busy */
  25. ASobs = 1<<1|1<<2|1<<4,
  26. };
  27. /* pci configuration */
  28. enum {
  29. Abar = 5,
  30. };
  31. /*
  32. * ahci memory configuration
  33. *
  34. * 0000-0023 generic host control
  35. * 0024-009f reserved
  36. * 00a0-00ff vendor specific.
  37. * 0100-017f port 0
  38. * ...
  39. * 1080-1100 port 31
  40. */
  41. /* cap bits: supported features */
  42. enum {
  43. Hs64a = 1<<31, /* 64-bit addressing */
  44. Hsncq = 1<<30, /* ncq */
  45. Hssntf = 1<<29, /* snotification reg. */
  46. Hsmps = 1<<28, /* mech pres switch */
  47. Hsss = 1<<27, /* staggered spinup */
  48. Hsalp = 1<<26, /* aggressive link pm */
  49. Hsal = 1<<25, /* activity led */
  50. Hsclo = 1<<24, /* command-list override */
  51. Hiss = 1<<20, /* for interface speed */
  52. // Hsnzo = 1<<19,
  53. Hsam = 1<<18, /* ahci-mode only */
  54. Hspm = 1<<17, /* port multiplier */
  55. // Hfbss = 1<<16,
  56. Hpmb = 1<<15, /* multiple-block pio */
  57. Hssc = 1<<14, /* slumber state */
  58. Hpsc = 1<<13, /* partial-slumber state */
  59. Hncs = 1<<8, /* n command slots */
  60. Hcccs = 1<<7, /* coal */
  61. Hems = 1<<6, /* enclosure mgmt. */
  62. Hsxs = 1<<5, /* external sata */
  63. Hnp = 1<<0, /* n ports */
  64. };
  65. /* ghc bits */
  66. enum {
  67. Hae = 1<<31, /* enable ahci */
  68. Hie = 1<<1, /* " interrupts */
  69. Hhr = 1<<0, /* hba reset */
  70. };
  71. typedef struct {
  72. u32int cap;
  73. u32int ghc;
  74. u32int isr;
  75. u32int pi; /* ports implemented */
  76. u32int ver;
  77. u32int ccc; /* coaleasing control */
  78. u32int cccports;
  79. u32int emloc;
  80. u32int emctl;
  81. } Ahba;
  82. enum {
  83. Acpds = 1<<31, /* cold port detect status */
  84. Atfes = 1<<30, /* task file error status */
  85. Ahbfs = 1<<29, /* hba fatal */
  86. Ahbds = 1<<28, /* hba error (parity error) */
  87. Aifs = 1<<27, /* interface fatal §6.1.2 */
  88. Ainfs = 1<<26, /* interface error (recovered) */
  89. Aofs = 1<<24, /* too many bytes from disk */
  90. Aipms = 1<<23, /* incorrect prt mul status */
  91. Aprcs = 1<<22, /* PhyRdy change status Pxserr.diag.n */
  92. Adpms = 1<<7, /* mechanical presence status */
  93. Apcs = 1<<6, /* port connect diag.x */
  94. Adps = 1<<5, /* descriptor processed */
  95. Aufs = 1<<4, /* unknown fis diag.f */
  96. Asdbs = 1<<3, /* set device bits fis received w/ i bit set */
  97. Adss = 1<<2, /* dma setup */
  98. Apio = 1<<1, /* pio setup fis */
  99. Adhrs = 1<<0, /* device to host register fis */
  100. IEM = Acpds|Atfes|Ahbds|Ahbfs|Ahbds|Aifs|Ainfs|Aprcs|Apcs|Adps|
  101. Aufs|Asdbs|Adss|Adhrs,
  102. Ifatal = Atfes|Ahbfs|Ahbds|Aifs,
  103. };
  104. /* serror bits */
  105. enum {
  106. SerrX = 1<<26, /* exchanged */
  107. SerrF = 1<<25, /* unknown fis */
  108. SerrT = 1<<24, /* transition error */
  109. SerrS = 1<<23, /* link sequence */
  110. SerrH = 1<<22, /* handshake */
  111. SerrC = 1<<21, /* crc */
  112. SerrD = 1<<20, /* not used by ahci */
  113. SerrB = 1<<19, /* 10-tp-8 decode */
  114. SerrW = 1<<18, /* comm wake */
  115. SerrI = 1<<17, /* phy internal */
  116. SerrN = 1<<16, /* phyrdy change */
  117. ErrE = 1<<11, /* internal */
  118. ErrP = 1<<10, /* ata protocol violation */
  119. ErrC = 1<<9, /* communication */
  120. ErrT = 1<<8, /* transient */
  121. ErrM = 1<<1, /* recoverd comm */
  122. ErrI = 1<<0, /* recovered data integrety */
  123. ErrAll = ErrE|ErrP|ErrC|ErrT|ErrM|ErrI,
  124. SerrAll = SerrX|SerrF|SerrT|SerrS|SerrH|SerrC|SerrD|SerrB|SerrW|
  125. SerrI|SerrN|ErrAll,
  126. SerrBad = 0x7f<<19,
  127. };
  128. /* cmd register bits */
  129. enum {
  130. Aicc = 1<<28, /* interface communcations control. 4 bits */
  131. Aasp = 1<<27, /* aggressive slumber & partial sleep */
  132. Aalpe = 1<<26, /* aggressive link pm enable */
  133. Adlae = 1<<25, /* drive led on atapi */
  134. Aatapi = 1<<24, /* device is atapi */
  135. Aesp = 1<<21, /* external sata port */
  136. Acpd = 1<<20, /* cold presence detect */
  137. Ampsp = 1<<19, /* mechanical pres. */
  138. Ahpcp = 1<<18, /* hot plug capable */
  139. Apma = 1<<17, /* pm attached */
  140. Acps = 1<<16, /* cold presence state */
  141. Acr = 1<<15, /* cmdlist running */
  142. Afr = 1<<14, /* fis running */
  143. Ampss = 1<<13, /* mechanical presence switch state */
  144. Accs = 1<<8, /* current command slot 12:08 */
  145. Afre = 1<<4, /* fis enable receive */
  146. Aclo = 1<<3, /* command list override */
  147. Apod = 1<<2, /* power on dev (requires cold-pres. detect) */
  148. Asud = 1<<1, /* spin-up device; requires ss capability */
  149. Ast = 1<<0, /* start */
  150. Arun = Ast|Acr|Afre|Afr,
  151. };
  152. /* ctl register bits */
  153. enum {
  154. Aipm = 1<<8, /* interface power mgmt. 3=off */
  155. Aspd = 1<<4,
  156. Adet = 1<<0, /* device detection */
  157. };
  158. #define sstatus scr0
  159. #define sctl scr2
  160. #define serror scr1
  161. #define sactive scr3
  162. typedef struct {
  163. u32int list; /* PxCLB must be 1kb aligned. */
  164. u32int listhi;
  165. u32int fis; /* 256-byte aligned */
  166. u32int fishi;
  167. u32int isr;
  168. u32int ie; /* interrupt enable */
  169. u32int cmd;
  170. u32int res1;
  171. u32int task;
  172. u32int sig;
  173. u32int scr0;
  174. u32int scr2;
  175. u32int scr1;
  176. u32int scr3;
  177. u32int ci; /* command issue */
  178. u32int ntf;
  179. uchar res2[8];
  180. u32int vendor;
  181. } Aport;
  182. /* in host's memory; not memory mapped */
  183. typedef struct {
  184. uchar *base;
  185. uchar *d;
  186. uchar *p;
  187. uchar *r;
  188. uchar *u;
  189. u32int *devicebits;
  190. } Afis;
  191. enum {
  192. Lprdtl = 1<<16, /* physical region descriptor table len */
  193. Lpmp = 1<<12, /* port multiplier port */
  194. Lclear = 1<<10, /* clear busy on R_OK */
  195. Lbist = 1<<9,
  196. Lreset = 1<<8,
  197. Lpref = 1<<7, /* prefetchable */
  198. Lwrite = 1<<6,
  199. Latapi = 1<<5,
  200. Lcfl = 1<<0, /* command fis length in double words */
  201. };
  202. /* in hosts memory; memory mapped */
  203. typedef struct {
  204. u32int flags;
  205. u32int len;
  206. u32int ctab;
  207. u32int ctabhi;
  208. uchar reserved[16];
  209. } Alist;
  210. typedef struct {
  211. u32int dba;
  212. u32int dbahi;
  213. u32int pad;
  214. u32int count;
  215. } Aprdt;
  216. typedef struct {
  217. uchar cfis[0x40];
  218. uchar atapi[0x10];
  219. uchar pad[0x30];
  220. Aprdt prdt;
  221. } Actab;
  222. enum {
  223. Ferror = 1,
  224. Fdone = 2,
  225. };
  226. enum {
  227. Dllba = 1,
  228. Dsmart = 1<<1,
  229. Dpower = 1<<2,
  230. Dnop = 1<<3,
  231. Datapi = 1<<4,
  232. Datapi16= 1<<5,
  233. };
  234. typedef struct {
  235. QLock;
  236. Rendez;
  237. uchar flag;
  238. uchar feat;
  239. uchar smart;
  240. Afis fis;
  241. Alist *list;
  242. Actab *ctab;
  243. } Aportm;
  244. typedef struct {
  245. Aport *p;
  246. Aportm *m;
  247. } Aportc;