sd63xxesb.c 35 KB

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  1. /*
  2. * intel/amd ahci sata controller
  3. * copyright © 2007 coraid, inc.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #include "../port/sd.h"
  13. #include "ahci.h"
  14. #define dprint(...) if(debug) iprint(__VA_ARGS__); else USED(debug)
  15. #define idprint(...) if(prid) print(__VA_ARGS__); else USED(prid)
  16. #define aprint(...) if(datapi) iprint(__VA_ARGS__); else USED(datapi)
  17. enum {
  18. NCtlr = 4,
  19. NCtlrdrv= 32,
  20. NDrive = NCtlr*NCtlrdrv,
  21. Read = 0,
  22. Write,
  23. };
  24. /* pci space configuration */
  25. enum {
  26. Pmap = 0x90,
  27. Ppcs = 0x91,
  28. Prev = 0xa8,
  29. };
  30. enum {
  31. Tesb,
  32. Tich,
  33. Tsb600,
  34. };
  35. #define Intel(x) ((x) == Tesb || (x) == Tich)
  36. static char *tname[] = {
  37. "63xxesb",
  38. "ich",
  39. "sb600",
  40. };
  41. enum {
  42. Dnull,
  43. Dmissing,
  44. Dnew,
  45. Dready,
  46. Derror,
  47. Dreset,
  48. Doffline,
  49. Dportreset,
  50. Dlast,
  51. };
  52. static char *diskstates[Dlast] = {
  53. "null",
  54. "missing",
  55. "new",
  56. "ready",
  57. "error",
  58. "reset",
  59. "offline",
  60. "portreset",
  61. };
  62. extern SDifc sd63xxesbifc;
  63. typedef struct Ctlr Ctlr;
  64. enum {
  65. DMautoneg,
  66. DMsatai,
  67. DMsataii,
  68. };
  69. static char *modename[] = {
  70. "auto",
  71. "satai",
  72. "sataii",
  73. };
  74. static char *flagname[] = {
  75. "llba",
  76. "smart",
  77. "power",
  78. "nop",
  79. "atapi",
  80. "atapi16",
  81. };
  82. typedef struct {
  83. Lock;
  84. Ctlr *ctlr;
  85. SDunit *unit;
  86. char name[10];
  87. Aport *port;
  88. Aportm portm;
  89. Aportc portc; /* redundant ptr to port and portm. */
  90. uchar mediachange;
  91. uchar state;
  92. uchar smartrs;
  93. uvlong sectors;
  94. ulong intick;
  95. int wait;
  96. uchar mode; /* DMautoneg, satai or sataii. */
  97. uchar active;
  98. char serial[20+1];
  99. char firmware[8+1];
  100. char model[40+1];
  101. ushort info[0x200];
  102. int driveno; /* ctlr*NCtlrdrv + unit */
  103. /* controller port # != driveno when not all ports are enabled */
  104. int portno;
  105. } Drive;
  106. struct Ctlr {
  107. Lock;
  108. int type;
  109. int enabled;
  110. SDev *sdev;
  111. Pcidev *pci;
  112. uchar *mmio;
  113. ulong *lmmio;
  114. Ahba *hba;
  115. Drive rawdrive[NCtlrdrv];
  116. Drive* drive[NCtlrdrv];
  117. int ndrive;
  118. };
  119. static Ctlr iactlr[NCtlr];
  120. static SDev sdevs[NCtlr];
  121. static int niactlr;
  122. static Drive *iadrive[NDrive];
  123. static int niadrive;
  124. static int debug;
  125. static int prid = 1;
  126. static int datapi = 0;
  127. static char stab[] = {
  128. [0] 'i', 'm',
  129. [8] 't', 'c', 'p', 'e',
  130. [16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  131. };
  132. static void
  133. serrstr(ulong r, char *s, char *e)
  134. {
  135. int i;
  136. e -= 3;
  137. for(i = 0; i < nelem(stab) && s < e; i++)
  138. if(r & (1<<i) && stab[i]){
  139. *s++ = stab[i];
  140. if(SerrBad & (1<<i))
  141. *s++ = '*';
  142. }
  143. *s = 0;
  144. }
  145. static char ntab[] = "0123456789abcdef";
  146. static void
  147. preg(uchar *reg, int n)
  148. {
  149. int i;
  150. char buf[25*3+1], *e;
  151. e = buf;
  152. for(i = 0; i < n; i++){
  153. *e++ = ntab[reg[i]>>4];
  154. *e++ = ntab[reg[i]&0xf];
  155. *e++ = ' ';
  156. }
  157. *e++ = '\n';
  158. *e = 0;
  159. dprint(buf);
  160. }
  161. static void
  162. dreg(char *s, Aport *p)
  163. {
  164. dprint("%stask=%ux; cmd=%ux; ci=%ux; is=%ux\n", s, p->task, p->cmd,
  165. p->ci, p->isr);
  166. }
  167. static void
  168. esleep(int ms)
  169. {
  170. if(waserror())
  171. return;
  172. tsleep(&up->sleep, return0, 0, ms);
  173. poperror();
  174. }
  175. typedef struct {
  176. Aport *p;
  177. int i;
  178. }Asleep;
  179. static int
  180. ahciclear(void *v)
  181. {
  182. Asleep *s;
  183. s = v;
  184. return (s->p->ci & s->i) == 0;
  185. }
  186. static void
  187. aesleep(Aportm *m, Asleep *a, int ms)
  188. {
  189. if(waserror())
  190. return;
  191. tsleep(m, ahciclear, a, ms);
  192. poperror();
  193. }
  194. static int
  195. ahciwait(Aportc *c, int ms)
  196. {
  197. Asleep as;
  198. Aport *p;
  199. p = c->p;
  200. p->ci = 1;
  201. as.p = p;
  202. as.i = 1;
  203. aesleep(c->m, &as, ms);
  204. if((p->task&1) == 0 && p->ci == 0)
  205. return 0;
  206. dreg("ahciwait timeout ", c->p);
  207. return -1;
  208. }
  209. static int
  210. nop(Aportc *pc)
  211. {
  212. uchar *c;
  213. Actab *t;
  214. Alist *l;
  215. if((pc->m->feat & Dnop) == 0)
  216. return -1;
  217. t = pc->m->ctab;
  218. c = t->cfis;
  219. memset(c, 0, 0x20);
  220. c[0] = 0x27;
  221. c[1] = 0x80;
  222. c[2] = 0x00;
  223. c[7] = 0xa0; /* obsolete device bits */
  224. l = pc->m->list;
  225. l->flags = Lwrite | 0x5;
  226. l->len = 0;
  227. l->ctab = PCIWADDR(t);
  228. l->ctabhi = 0;
  229. return ahciwait(pc, 3*1000);
  230. }
  231. static int
  232. setfeatures(Aportc *pc, uchar f)
  233. {
  234. uchar *c;
  235. Actab *t;
  236. Alist *l;
  237. t = pc->m->ctab;
  238. c = t->cfis;
  239. memset(c, 0, 0x20);
  240. c[0] = 0x27;
  241. c[1] = 0x80;
  242. c[2] = 0xef;
  243. c[3] = f;
  244. c[7] = 0xa0; /* obsolete device bits */
  245. l = pc->m->list;
  246. l->flags = Lwrite | 0x5;
  247. l->len = 0;
  248. l->ctab = PCIWADDR(t);
  249. l->ctabhi = 0;
  250. return ahciwait(pc, 3*1000);
  251. }
  252. static int
  253. setudmamode(Aportc *pc, uchar f)
  254. {
  255. uchar *c;
  256. Actab *t;
  257. Alist *l;
  258. /* hack */
  259. if((pc->p->sig >> 16) == 0xeb14)
  260. return 0;
  261. t = pc->m->ctab;
  262. c = t->cfis;
  263. memset(c, 0, 0x20);
  264. c[0] = 0x27;
  265. c[1] = 0x80;
  266. c[2] = 0xef;
  267. c[3] = 3; /* set transfer mode */
  268. c[7] = 0xa0; /* obsolete device bits */
  269. c[12] = 0x40 | f; /* sector count */
  270. l = pc->m->list;
  271. l->flags = Lwrite | 0x5;
  272. l->len = 0;
  273. l->ctab = PCIWADDR(t);
  274. l->ctabhi = 0;
  275. return ahciwait(pc, 3*1000);
  276. }
  277. static void
  278. asleep(int ms)
  279. {
  280. if(up == nil)
  281. delay(ms);
  282. else
  283. esleep(ms);
  284. }
  285. static int
  286. ahciportreset(Aportc *c)
  287. {
  288. u32int *cmd, i;
  289. Aport *p;
  290. p = c->p;
  291. cmd = &p->cmd;
  292. *cmd &= ~(Afre|Ast);
  293. for(i = 0; i < 500; i += 25){
  294. if((*cmd&Acr) == 0)
  295. break;
  296. asleep(25);
  297. }
  298. p->sctl = 1|(p->sctl&~7);
  299. delay(1);
  300. p->sctl &= ~7;
  301. return 0;
  302. }
  303. static int
  304. smart(Aportc *pc, int n)
  305. {
  306. uchar *c;
  307. Actab *t;
  308. Alist *l;
  309. if((pc->m->feat&Dsmart) == 0)
  310. return -1;
  311. t = pc->m->ctab;
  312. c = t->cfis;
  313. memset(c, 0, 0x20);
  314. c[0] = 0x27;
  315. c[1] = 0x80;
  316. c[2] = 0xb0;
  317. c[3] = 0xd8 + n; /* able smart */
  318. c[5] = 0x4f;
  319. c[6] = 0xc2;
  320. c[7] = 0xa0;
  321. l = pc->m->list;
  322. l->flags = Lwrite | 0x5;
  323. l->len = 0;
  324. l->ctab = PCIWADDR(t);
  325. l->ctabhi = 0;
  326. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  327. dprint("smart fail %ux\n", pc->p->task);
  328. // preg(pc->m->fis.r, 20);
  329. return -1;
  330. }
  331. if(n)
  332. return 0;
  333. return 1;
  334. }
  335. static int
  336. smartrs(Aportc *pc)
  337. {
  338. uchar *c;
  339. Actab *t;
  340. Alist *l;
  341. t = pc->m->ctab;
  342. c = t->cfis;
  343. memset(c, 0, 0x20);
  344. c[0] = 0x27;
  345. c[1] = 0x80;
  346. c[2] = 0xb0;
  347. c[3] = 0xda; /* return smart status */
  348. c[5] = 0x4f;
  349. c[6] = 0xc2;
  350. c[7] = 0xa0;
  351. l = pc->m->list;
  352. l->flags = Lwrite | 0x5;
  353. l->len = 0;
  354. l->ctab = PCIWADDR(t);
  355. l->ctabhi = 0;
  356. c = pc->m->fis.r;
  357. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  358. dprint("smart fail %ux\n", pc->p->task);
  359. preg(c, 20);
  360. return -1;
  361. }
  362. if(c[5] == 0x4f && c[6] == 0xc2)
  363. return 1;
  364. return 0;
  365. }
  366. static int
  367. flushcache(Aportc *pc)
  368. {
  369. uchar *c, llba;
  370. Actab *t;
  371. Alist *l;
  372. static uchar tab[2] = {0xe7, 0xea};
  373. llba = pc->m->feat&Dllba? 1: 0;
  374. t = pc->m->ctab;
  375. c = t->cfis;
  376. memset(c, 0, 0x20);
  377. c[0] = 0x27;
  378. c[1] = 0x80;
  379. c[2] = tab[llba];
  380. c[7] = 0xa0;
  381. l = pc->m->list;
  382. l->flags = Lwrite | 0x5;
  383. l->len = 0;
  384. l->ctab = PCIWADDR(t);
  385. l->ctabhi = 0;
  386. if(ahciwait(pc, 60000) == -1 || pc->p->task & (1|32)){
  387. dprint("flushcache fail %ux\n", pc->p->task);
  388. // preg( pc->m->fis.r, 20);
  389. return -1;
  390. }
  391. return 0;
  392. }
  393. static ushort
  394. gbit16(void *a)
  395. {
  396. ushort j;
  397. uchar *i;
  398. i = a;
  399. j = i[1] << 8;
  400. j |= i[0];
  401. return j;
  402. }
  403. static u32int
  404. gbit32(void *a)
  405. {
  406. u32int j;
  407. uchar *i;
  408. i = a;
  409. j = i[3] << 24;
  410. j |= i[2] << 16;
  411. j |= i[1] << 8;
  412. j |= i[0];
  413. return j;
  414. }
  415. static uvlong
  416. gbit64(void *a)
  417. {
  418. uchar *i;
  419. i = a;
  420. return (uvlong)gbit32(i+4) << 32 | gbit32(a);
  421. }
  422. static int
  423. ahciidentify0(Aportc *pc, void *id, int atapi)
  424. {
  425. uchar *c;
  426. Actab *t;
  427. Alist *l;
  428. Aprdt *p;
  429. static uchar tab[] = { 0xec, 0xa1, };
  430. t = pc->m->ctab;
  431. c = t->cfis;
  432. memset(c, 0, 0x20);
  433. c[0] = 0x27;
  434. c[1] = 0x80;
  435. c[2] = tab[atapi];
  436. c[7] = 0xa0; /* obsolete device bits */
  437. l = pc->m->list;
  438. l->flags = 1<<16 | 0x5;
  439. l->len = 0;
  440. l->ctab = PCIWADDR(t);
  441. l->ctabhi = 0;
  442. memset(id, 0, 0x100);
  443. p = &t->prdt;
  444. p->dba = PCIWADDR(id);
  445. p->dbahi = 0;
  446. p->count = 1<<31 | (0x200-2) | 1;
  447. return ahciwait(pc, 3*1000);
  448. }
  449. static vlong
  450. ahciidentify(Aportc *pc, ushort *id)
  451. {
  452. int i, sig;
  453. vlong s;
  454. Aportm *m;
  455. m = pc->m;
  456. m->feat = 0;
  457. m->smart = 0;
  458. i = 0;
  459. sig = pc->p->sig >> 16;
  460. if(sig == 0xeb14){
  461. m->feat |= Datapi;
  462. i = 1;
  463. }
  464. if(ahciidentify0(pc, id, i) == -1)
  465. return -1;
  466. i = gbit16(id+83) | gbit16(id+86);
  467. if(i & (1<<10)){
  468. m->feat |= Dllba;
  469. s = gbit64(id+100);
  470. }else
  471. s = gbit32(id+60);
  472. if(m->feat&Datapi){
  473. i = gbit16(id+0);
  474. if(i&1)
  475. m->feat |= Datapi16;
  476. }
  477. i = gbit16(id+83);
  478. if((i>>14) == 1) {
  479. if(i & (1<<3))
  480. m->feat |= Dpower;
  481. i = gbit16(id+82);
  482. if(i & 1)
  483. m->feat |= Dsmart;
  484. if(i & (1<<14))
  485. m->feat |= Dnop;
  486. }
  487. return s;
  488. }
  489. static int
  490. ahciquiet(Aport *a)
  491. {
  492. u32int *p, i;
  493. p = &a->cmd;
  494. *p &= ~Ast;
  495. for(i = 0; i < 500; i += 50){
  496. if((*p & Acr) == 0)
  497. goto stop;
  498. asleep(50);
  499. }
  500. return -1;
  501. stop:
  502. if((a->task & (ASdrq|ASbsy)) == 0){
  503. *p |= Ast;
  504. return 0;
  505. }
  506. *p |= Aclo;
  507. for(i = 0; i < 500; i += 50){
  508. if((*p & Aclo) == 0)
  509. goto stop1;
  510. asleep(50);
  511. }
  512. return -1;
  513. stop1:
  514. /* extra check */
  515. dprint("clo clear %x\n", a->task);
  516. if(a->task & ASbsy)
  517. return -1;
  518. *p |= Ast;
  519. return 0;
  520. }
  521. static int
  522. ahcicomreset(Aportc *pc)
  523. {
  524. uchar *c;
  525. Actab *t;
  526. Alist *l;
  527. dprint("ahcicomreset\n");
  528. dreg("comreset ", pc->p);
  529. if(ahciquiet(pc->p) == -1){
  530. dprint("ahciquiet fails\n");
  531. return -1;
  532. }
  533. dreg("comreset ", pc->p);
  534. t = pc->m->ctab;
  535. c = t->cfis;
  536. memset(c, 0, 0x20);
  537. c[0] = 0x27;
  538. c[1] = 0x00;
  539. c[7] = 0xa0; /* obsolete device bits */
  540. c[15] = 1<<2; /* srst */
  541. l = pc->m->list;
  542. l->flags = Lclear | Lreset | 0x5;
  543. l->len = 0;
  544. l->ctab = PCIWADDR(t);
  545. l->ctabhi = 0;
  546. if(ahciwait(pc, 500) == -1){
  547. dprint("first command in comreset fails\n");
  548. return -1;
  549. }
  550. microdelay(250);
  551. dreg("comreset ", pc->p);
  552. memset(c, 0, 0x20);
  553. c[0] = 0x27;
  554. c[1] = 0x00;
  555. c[7] = 0xa0; /* obsolete device bits */
  556. l = pc->m->list;
  557. l->flags = Lwrite | 0x5;
  558. l->len = 0;
  559. l->ctab = PCIWADDR(t);
  560. l->ctabhi = 0;
  561. if(ahciwait(pc, 150) == -1){
  562. dprint("second command in comreset fails\n");
  563. return -1;
  564. }
  565. dreg("comreset ", pc->p);
  566. return 0;
  567. }
  568. static int
  569. ahciidle(Aport *port)
  570. {
  571. u32int *p, i, r;
  572. p = &port->cmd;
  573. if((*p & Arun) == 0)
  574. return 0;
  575. *p &= ~Ast;
  576. r = 0;
  577. for(i = 0; i < 500; i += 25){
  578. if((*p & Acr) == 0)
  579. goto stop;
  580. asleep(25);
  581. }
  582. r = -1;
  583. stop:
  584. if((*p & Afre) == 0)
  585. return r;
  586. *p &= ~Afre;
  587. for(i = 0; i < 500; i += 25){
  588. if((*p & Afre) == 0)
  589. return 0;
  590. asleep(25);
  591. }
  592. return -1;
  593. }
  594. /*
  595. * § 6.2.2.1 first part; comreset handled by reset disk.
  596. * - remainder is handled by configdisk.
  597. * - ahcirecover is a quick recovery from a failed command.
  598. */
  599. int
  600. ahciswreset(Aportc *pc)
  601. {
  602. int i;
  603. i = ahciidle(pc->p);
  604. pc->p->cmd |= Afre;
  605. if(i == -1)
  606. return -1;
  607. if(pc->p->task & (ASdrq|ASbsy))
  608. return -1;
  609. return 0;
  610. }
  611. int
  612. ahcirecover(Aportc *pc)
  613. {
  614. ahciswreset(pc);
  615. pc->p->cmd |= Ast;
  616. if(setudmamode(pc, 5) == -1)
  617. return -1;
  618. return 0;
  619. }
  620. static void*
  621. malign(int size, int align)
  622. {
  623. void *v;
  624. v = xspanalloc(size, align, 0);
  625. memset(v, 0, size);
  626. return v;
  627. }
  628. static void
  629. setupfis(Afis *f)
  630. {
  631. f->base = malign(0x100, 0x100);
  632. f->d = f->base + 0;
  633. f->p = f->base + 0x20;
  634. f->r = f->base + 0x40;
  635. f->u = f->base + 0x60;
  636. f->devicebits = (u32int*)(f->base + 0x58);
  637. }
  638. static int
  639. ahciconfigdrive(Ahba *h, Aportc *c, int mode)
  640. {
  641. Aportm *m;
  642. Aport *p;
  643. p = c->p;
  644. m = c->m;
  645. if(m->list == 0){
  646. setupfis(&m->fis);
  647. m->list = malign(sizeof *m->list, 1024);
  648. m->ctab = malign(sizeof *m->ctab, 128);
  649. }
  650. if(p->sstatus & 3 && h->cap & Hsss){
  651. dprint("configdrive: spinning up ... [%ux]\n", p->sstatus);
  652. p->cmd |= Apod|Asud;
  653. asleep(1400);
  654. }
  655. p->serror = SerrAll;
  656. p->list = PCIWADDR(m->list);
  657. p->listhi = 0;
  658. p->fis = PCIWADDR(m->fis.base);
  659. p->fishi = 0;
  660. p->cmd |= Afre|Ast;
  661. /* disable power managment sequence from book. */
  662. p->sctl = (3*Aipm) | (mode*Aspd) | 0*Adet;
  663. p->cmd &= ~Aalpe;
  664. p->ie = IEM;
  665. return 0;
  666. }
  667. static int
  668. ahcienable(Ahba *h)
  669. {
  670. h->ghc |= Hie;
  671. return 0;
  672. }
  673. static int
  674. ahcidisable(Ahba *h)
  675. {
  676. h->ghc &= ~Hie;
  677. return 0;
  678. }
  679. static int
  680. countbits(ulong u)
  681. {
  682. int i, n;
  683. n = 0;
  684. for(i = 0; i < 32; i++)
  685. if(u & (1<<i))
  686. n++;
  687. return n;
  688. }
  689. static int
  690. ahciconf(Ctlr *ctlr)
  691. {
  692. Ahba *h;
  693. u32int u;
  694. h = ctlr->hba = (Ahba*)ctlr->mmio;
  695. u = h->cap;
  696. if((u&Hsam) == 0)
  697. h->ghc |= Hae;
  698. print("#S/sd%c: ahci: port %#p: hba sss %d; ncs %d; coal %d; "
  699. "mports %d; led %d; clo %d; ems %d;\n",
  700. ctlr->sdev->idno, h,
  701. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1,
  702. (u>>24) & 1, (u>>6) & 1);
  703. return countbits(h->pi);
  704. }
  705. static int
  706. ahcihbareset(Ahba *h)
  707. {
  708. int wait;
  709. h->ghc |= 1;
  710. for(wait = 0; wait < 1000; wait += 100){
  711. if(h->ghc == 0)
  712. return 0;
  713. delay(100);
  714. }
  715. return -1;
  716. }
  717. static void
  718. idmove(char *p, ushort *a, int n)
  719. {
  720. int i;
  721. char *op, *e;
  722. op = p;
  723. for(i = 0; i < n/2; i++){
  724. *p++ = a[i] >> 8;
  725. *p++ = a[i];
  726. }
  727. *p = 0;
  728. while(p > op && *--p == ' ')
  729. *p = 0;
  730. e = p;
  731. p = op;
  732. while(*p == ' ')
  733. p++;
  734. memmove(op, p, n - (e - p));
  735. }
  736. static int
  737. identify(Drive *d)
  738. {
  739. u16int *id;
  740. vlong osectors, s;
  741. uchar oserial[21];
  742. SDunit *u;
  743. id = d->info;
  744. s = ahciidentify(&d->portc, id);
  745. if(s == -1){
  746. d->state = Derror;
  747. return -1;
  748. }
  749. osectors = d->sectors;
  750. memmove(oserial, d->serial, sizeof d->serial);
  751. d->sectors = s;
  752. d->smartrs = 0;
  753. idmove(d->serial, id+10, 20);
  754. idmove(d->firmware, id+23, 8);
  755. idmove(d->model, id+27, 40);
  756. u = d->unit;
  757. memset(u->inquiry, 0, sizeof u->inquiry);
  758. u->inquiry[2] = 2;
  759. u->inquiry[3] = 2;
  760. u->inquiry[4] = sizeof u->inquiry - 4;
  761. memmove(u->inquiry+8, d->model, 40);
  762. if((osectors == 0 || osectors != s) &&
  763. memcmp(oserial, d->serial, sizeof oserial) != 0){
  764. d->mediachange = 1;
  765. u->sectors = 0;
  766. }
  767. return 0;
  768. }
  769. static void
  770. clearci(Aport *p)
  771. {
  772. if(p->cmd & Ast) {
  773. p->cmd &= ~Ast;
  774. p->cmd |= Ast;
  775. }
  776. }
  777. static void
  778. updatedrive(Drive *d)
  779. {
  780. u32int cause, serr, s0, pr, ewake;
  781. char *name;
  782. Aport *p;
  783. static u32int last;
  784. pr = 1;
  785. ewake = 0;
  786. p = d->port;
  787. cause = p->isr;
  788. serr = p->serror;
  789. p->isr = cause;
  790. name = "??";
  791. if(d->unit && d->unit->name)
  792. name = d->unit->name;
  793. if(p->ci == 0){
  794. d->portm.flag |= Fdone;
  795. wakeup(&d->portm);
  796. pr = 0;
  797. }else if(cause & Adps)
  798. pr = 0;
  799. if(cause & Ifatal){
  800. ewake = 1;
  801. dprint("Fatal\n");
  802. }
  803. if(cause & Adhrs){
  804. if(p->task & 33){
  805. dprint("Adhrs cause = %ux; serr = %ux; task=%ux\n",
  806. cause, serr, p->task);
  807. d->portm.flag |= Ferror;
  808. ewake = 1;
  809. }
  810. pr = 0;
  811. }
  812. if(0 && p->task & 1 && last != cause)
  813. dprint("err ca %ux serr %ux task %ux sstat %ux\n",
  814. cause, serr, p->task, p->sstatus);
  815. if(pr)
  816. dprint("%s: upd %ux ta %ux\n", name, cause, p->task);
  817. if(cause & (Aprcs|Aifs)){
  818. s0 = d->state;
  819. switch(p->sstatus & 7){
  820. case 0:
  821. d->state = Dmissing;
  822. break;
  823. case 1:
  824. d->state = Derror;
  825. break;
  826. case 3:
  827. /* power mgnt crap for suprise removal */
  828. p->ie |= Aprcs|Apcs; /* is this required? */
  829. d->state = Dreset;
  830. break;
  831. case 4:
  832. d->state = Doffline;
  833. break;
  834. }
  835. dprint("%s: %s → %s [Apcrs] %ux\n", name, diskstates[s0],
  836. diskstates[d->state], p->sstatus);
  837. /* print pulled message here. */
  838. if(s0 == Dready && d->state != Dready)
  839. idprint("%s: pulled\n", name);
  840. if(d->state != Dready)
  841. d->portm.flag |= Ferror;
  842. ewake = 1;
  843. }
  844. p->serror = serr;
  845. if(ewake){
  846. clearci(p);
  847. wakeup(&d->portm);
  848. }
  849. last = cause;
  850. }
  851. static void
  852. pstatus(Drive *d, ulong s)
  853. {
  854. /*
  855. * bogus code because the first interrupt is currently dropped.
  856. * likely my fault. serror is maybe cleared at the wrong time.
  857. */
  858. switch(s){
  859. case 0:
  860. d->state = Dmissing;
  861. break;
  862. case 2: /* should this be missing? need testcase. */
  863. dprint("pstatus 2\n");
  864. /* fallthrough */
  865. case 3:
  866. d->wait = 0;
  867. d->state = Dnew;
  868. break;
  869. case 4:
  870. d->state = Doffline;
  871. break;
  872. }
  873. }
  874. static int
  875. configdrive(Drive *d)
  876. {
  877. if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1)
  878. return -1;
  879. ilock(d);
  880. pstatus(d, d->port->sstatus & 7);
  881. iunlock(d);
  882. return 0;
  883. }
  884. static void
  885. resetdisk(Drive *d)
  886. {
  887. uint state, det, stat;
  888. Aport *p;
  889. p = d->port;
  890. det = p->sctl & 7;
  891. stat = p->sstatus & 7;
  892. state = (p->cmd>>28) & 0xf;
  893. dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat);
  894. if(stat != 3){
  895. ilock(d);
  896. d->state = Dportreset;
  897. iunlock(d);
  898. return;
  899. }
  900. ilock(d);
  901. state = d->state;
  902. if(d->state != Dready || d->state != Dnew)
  903. d->portm.flag |= Ferror;
  904. clearci(p); /* satisfy sleep condition. */
  905. wakeup(&d->portm);
  906. iunlock(d);
  907. qlock(&d->portm);
  908. if(p->cmd&Ast && ahciswreset(&d->portc) == -1){
  909. ilock(d);
  910. d->state = Dportreset; /* get a bigger stick. */
  911. iunlock(d);
  912. } else {
  913. ilock(d);
  914. d->state = Dmissing;
  915. iunlock(d);
  916. configdrive(d);
  917. }
  918. dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]);
  919. qunlock(&d->portm);
  920. }
  921. static int
  922. newdrive(Drive *d)
  923. {
  924. char *name, *s;
  925. Aportc *c;
  926. Aportm *m;
  927. c = &d->portc;
  928. m = &d->portm;
  929. name = d->unit->name;
  930. if(name == 0)
  931. name = "??";
  932. if(d->port->task == 0x80)
  933. return -1;
  934. qlock(c->m);
  935. if(setudmamode(c, 5) == -1){
  936. dprint("%s: can't set udma mode\n", name);
  937. goto lose;
  938. }
  939. if(identify(d) == -1){
  940. dprint("%s: identify failure\n", name);
  941. goto lose;
  942. }
  943. if(m->feat & Dpower && setfeatures(c, 0x85) == -1){
  944. m->feat &= ~Dpower;
  945. if(ahcirecover(c) == -1)
  946. goto lose;
  947. }
  948. ilock(d);
  949. d->state = Dready;
  950. iunlock(d);
  951. qunlock(c->m);
  952. s = "";
  953. if(m->feat & Dllba)
  954. s = "L";
  955. idprint("%s: %sLBA %,lld sectors\n", d->unit->name, s, d->sectors);
  956. idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial,
  957. d->mediachange?"[mediachange]":"");
  958. return 0;
  959. lose:
  960. qunlock(c->m);
  961. return -1;
  962. }
  963. enum {
  964. Nms = 256,
  965. Mphywait = 2*1024/Nms - 1,
  966. Midwait = 16*1024/Nms - 1,
  967. Mcomrwait = 64*1024/Nms - 1,
  968. };
  969. static void
  970. westerndigitalhung(Drive *d)
  971. {
  972. if((d->portm.feat&Datapi) == 0 && d->active &&
  973. TK2MS(MACHP(0)->ticks-d->intick) > 5000){
  974. dprint("%s: drive hung; resetting [%ux] ci=%x\n",
  975. d->unit->name, d->port->task, d->port->ci);
  976. d->state = Dreset;
  977. }
  978. }
  979. static ushort olds[NCtlr*NCtlrdrv];
  980. static int
  981. doportreset(Drive *d)
  982. {
  983. int i;
  984. i = -1;
  985. qlock(&d->portm);
  986. if(ahciportreset(&d->portc) == -1)
  987. dprint("ahciportreset fails\n");
  988. else
  989. i = 0;
  990. qunlock(&d->portm);
  991. dprint("portreset → %s [task %ux]\n",
  992. diskstates[d->state], d->port->task);
  993. return i;
  994. }
  995. static void
  996. checkdrive(Drive *d, int i)
  997. {
  998. ushort s;
  999. char *name;
  1000. ilock(d);
  1001. name = d->unit->name;
  1002. s = d->port->sstatus;
  1003. if(s != olds[i]){
  1004. dprint("%s: status: %04ux -> %04ux: %s\n",
  1005. name, olds[i], s, diskstates[d->state]);
  1006. olds[i] = s;
  1007. d->wait = 0;
  1008. }
  1009. westerndigitalhung(d);
  1010. switch(d->state){
  1011. case Dnull:
  1012. case Dready:
  1013. break;
  1014. case Dmissing:
  1015. case Dnew:
  1016. switch(s & 0x107){
  1017. case 0:
  1018. case 1:
  1019. break;
  1020. default:
  1021. dprint("%s: unknown status %04ux\n", name, s);
  1022. case 0x100:
  1023. if(++d->wait&Mphywait)
  1024. break;
  1025. reset:
  1026. if(++d->mode > DMsataii)
  1027. d->mode = 0;
  1028. if(d->mode == DMsatai){ /* we tried everything */
  1029. d->state = Dportreset;
  1030. goto portreset;
  1031. }
  1032. dprint("%s: reset; new mode %s\n", name,
  1033. modename[d->mode]);
  1034. iunlock(d);
  1035. resetdisk(d);
  1036. ilock(d);
  1037. break;
  1038. case 0x103:
  1039. if((++d->wait&Midwait) == 0){
  1040. dprint("%s: slow reset %04ux task=%ux; %d\n",
  1041. name, s, d->port->task, d->wait);
  1042. goto reset;
  1043. }
  1044. s = d->port->task&0xff;
  1045. if(s == 0x7f || ((d->port->sig >> 16) != 0xeb14 &&
  1046. (s & ~0x17) != (1<<6)))
  1047. break;
  1048. iunlock(d);
  1049. newdrive(d);
  1050. ilock(d);
  1051. break;
  1052. }
  1053. break;
  1054. case Doffline:
  1055. if(d->wait++ & Mcomrwait)
  1056. break;
  1057. /* fallthrough */
  1058. case Derror:
  1059. case Dreset:
  1060. dprint("%s: reset [%s]: mode %d; status %04ux\n",
  1061. name, diskstates[d->state], d->mode, s);
  1062. iunlock(d);
  1063. resetdisk(d);
  1064. ilock(d);
  1065. break;
  1066. case Dportreset:
  1067. portreset:
  1068. if(d->wait++ & 0xff && (s & 0x100) == 0)
  1069. break;
  1070. dprint("%s: portreset [%s]: mode %d; status %04ux\n",
  1071. name, diskstates[d->state], d->mode, s);
  1072. d->portm.flag |= Ferror;
  1073. clearci(d->port);
  1074. wakeup(&d->portm);
  1075. if((s & 7) == 0){
  1076. d->state = Dmissing;
  1077. break;
  1078. }
  1079. iunlock(d);
  1080. doportreset(d);
  1081. ilock(d);
  1082. break;
  1083. }
  1084. iunlock(d);
  1085. }
  1086. static void
  1087. satakproc(void*)
  1088. {
  1089. int i;
  1090. memset(olds, 0xff, sizeof olds);
  1091. for(;;){
  1092. tsleep(&up->sleep, return0, 0, Nms);
  1093. for(i = 0; i < niadrive; i++)
  1094. checkdrive(iadrive[i], i);
  1095. }
  1096. }
  1097. static void
  1098. iainterrupt(Ureg*, void *a)
  1099. {
  1100. int i;
  1101. ulong cause, m;
  1102. Ctlr *c;
  1103. Drive *d;
  1104. c = a;
  1105. ilock(c);
  1106. cause = c->hba->isr;
  1107. for(i = 0; i < c->ndrive; i++){
  1108. m = 1 << i;
  1109. if((cause & m) == 0)
  1110. continue;
  1111. d = c->rawdrive + i;
  1112. ilock(d);
  1113. if(d->port->isr && c->hba->pi & m)
  1114. updatedrive(d);
  1115. c->hba->isr = m;
  1116. iunlock(d);
  1117. }
  1118. iunlock(c);
  1119. }
  1120. static int
  1121. iaverify(SDunit *u)
  1122. {
  1123. Ctlr *c;
  1124. Drive *d;
  1125. c = u->dev->ctlr;
  1126. d = c->drive[u->subno];
  1127. ilock(c);
  1128. ilock(d);
  1129. d->unit = u;
  1130. iunlock(d);
  1131. iunlock(c);
  1132. return 1;
  1133. }
  1134. static int
  1135. iaenable(SDev *s)
  1136. {
  1137. char name[32];
  1138. static int once;
  1139. Ctlr *c;
  1140. c = s->ctlr;
  1141. ilock(c);
  1142. if(!c->enabled) {
  1143. if(once++ == 0)
  1144. kproc("iasata", satakproc, 0);
  1145. pcisetbme(c->pci);
  1146. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1147. intrenable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1148. /* supposed to squelch leftover interrupts here. */
  1149. ahcienable(c->hba);
  1150. }
  1151. c->enabled = 1;
  1152. iunlock(c);
  1153. return 1;
  1154. }
  1155. static int
  1156. iadisable(SDev *s)
  1157. {
  1158. char name[32];
  1159. Ctlr *c;
  1160. c = s->ctlr;
  1161. ilock(c);
  1162. ahcidisable(c->hba);
  1163. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1164. intrdisable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1165. c->enabled = 0;
  1166. iunlock(c);
  1167. return 1;
  1168. }
  1169. static int
  1170. iaonline(SDunit *unit)
  1171. {
  1172. int r;
  1173. Ctlr *c;
  1174. Drive *d;
  1175. c = unit->dev->ctlr;
  1176. d = c->drive[unit->subno];
  1177. r = 0;
  1178. if(d->portm.feat & Datapi && d->mediachange){
  1179. r = scsionline(unit);
  1180. if(r > 0)
  1181. d->mediachange = 0;
  1182. return r;
  1183. }
  1184. ilock(d);
  1185. if(d->mediachange){
  1186. r = 2;
  1187. d->mediachange = 0;
  1188. /* devsd resets this after online is called; why? */
  1189. unit->sectors = d->sectors;
  1190. unit->secsize = 512;
  1191. } else if(d->state == Dready)
  1192. r = 1;
  1193. iunlock(d);
  1194. return r;
  1195. }
  1196. /* returns locked list! */
  1197. static Alist*
  1198. ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba)
  1199. {
  1200. uchar *c, acmd, dir, llba;
  1201. Alist *l;
  1202. Actab *t;
  1203. Aprdt *p;
  1204. static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35, };
  1205. dir = *cmd != 0x28;
  1206. llba = m->feat&Dllba? 1: 0;
  1207. acmd = tab[dir][llba];
  1208. qlock(m);
  1209. l = m->list;
  1210. t = m->ctab;
  1211. c = t->cfis;
  1212. c[0] = 0x27;
  1213. c[1] = 0x80;
  1214. c[2] = acmd;
  1215. c[3] = 0;
  1216. c[4] = lba; /* sector lba low 7:0 */
  1217. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1218. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1219. c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */
  1220. if(llba == 0)
  1221. c[7] |= (lba>>24) & 7;
  1222. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1223. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1224. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1225. c[11] = 0; /* features (exp); */
  1226. c[12] = n; /* sector count */
  1227. c[13] = n >> 8; /* sector count (exp) */
  1228. c[14] = 0; /* r */
  1229. c[15] = 0; /* control */
  1230. *(ulong*)(c + 16) = 0;
  1231. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1232. if(dir == Write)
  1233. l->flags |= Lwrite;
  1234. l->len = 0;
  1235. l->ctab = PCIWADDR(t);
  1236. l->ctabhi = 0;
  1237. p = &t->prdt;
  1238. p->dba = PCIWADDR(data);
  1239. p->dbahi = 0;
  1240. p->count = 1<<31 | (512*n - 2) | 1;
  1241. return l;
  1242. }
  1243. static Alist*
  1244. ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n)
  1245. {
  1246. int fill, len;
  1247. uchar *c;
  1248. Alist *l;
  1249. Actab *t;
  1250. Aprdt *p;
  1251. qlock(m);
  1252. l = m->list;
  1253. t = m->ctab;
  1254. c = t->cfis;
  1255. fill = m->feat&Datapi16? 16: 12;
  1256. if((len = r->clen) > fill)
  1257. len = fill;
  1258. memmove(t->atapi, r->cmd, len);
  1259. memset(t->atapi+len, 0, fill-len);
  1260. c[0] = 0x27;
  1261. c[1] = 0x80;
  1262. c[2] = 0xa0;
  1263. if(n != 0)
  1264. c[3] = 1; /* dma */
  1265. else
  1266. c[3] = 0; /* features (exp); */
  1267. c[4] = 0; /* sector lba low 7:0 */
  1268. c[5] = n; /* cylinder low lba mid 15:8 */
  1269. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1270. c[7] = 0xa0; /* obsolete device bits */
  1271. *(ulong*)(c + 8) = 0;
  1272. *(ulong*)(c + 12) = 0;
  1273. *(ulong*)(c + 16) = 0;
  1274. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1275. if(r->write != 0 && data)
  1276. l->flags |= Lwrite;
  1277. l->len = 0;
  1278. l->ctab = PCIWADDR(t);
  1279. l->ctabhi = 0;
  1280. if(data == 0)
  1281. return l;
  1282. p = &t->prdt;
  1283. p->dba = PCIWADDR(data);
  1284. p->dbahi = 0;
  1285. p->count = 1<<31 | (n - 2) | 1;
  1286. return l;
  1287. }
  1288. static int
  1289. waitready(Drive *d)
  1290. {
  1291. u32int s, t, i;
  1292. for(i = 0; i < 120; i++){
  1293. ilock(d);
  1294. s = d->port->sstatus;
  1295. t = d->port->task;
  1296. iunlock(d);
  1297. if((s & 0x100) == 0)
  1298. return -1;
  1299. if(d->state == Dready && (s & 7) == 3)
  1300. return 0;
  1301. if((i+1) % 30 == 0)
  1302. print("%s: waitready: [%s] task=%ux sstat=%ux\n",
  1303. d->unit->name, diskstates[d->state], t, s);
  1304. esleep(1000);
  1305. }
  1306. print("%s: not responding; offline\n", d->unit->name);
  1307. ilock(d);
  1308. d->state = Doffline;
  1309. iunlock(d);
  1310. return -1;
  1311. }
  1312. static int
  1313. iariopkt(SDreq *r, Drive *d)
  1314. {
  1315. int n, count, try, max, flag, task;
  1316. char *name;
  1317. uchar *cmd, *data;
  1318. Aport *p;
  1319. Asleep as;
  1320. cmd = r->cmd;
  1321. name = d->unit->name;
  1322. p = d->port;
  1323. aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write],
  1324. r->dlen, r->data);
  1325. if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1326. return sdmodesense(r, cmd, d->info, sizeof d->info);
  1327. r->rlen = 0;
  1328. count = r->dlen;
  1329. max = 65536;
  1330. try = 0;
  1331. retry:
  1332. if(waitready(d) == -1)
  1333. return SDeio;
  1334. data = r->data;
  1335. n = count;
  1336. if(n > max)
  1337. n = max;
  1338. d->active++;
  1339. ahcibuildpkt(&d->portm, r, data, n);
  1340. ilock(d);
  1341. d->portm.flag = 0;
  1342. iunlock(d);
  1343. p->ci = 1;
  1344. as.p = p;
  1345. as.i = 1;
  1346. d->intick = MACHP(0)->ticks;
  1347. while(waserror())
  1348. ;
  1349. sleep(&d->portm, ahciclear, &as);
  1350. poperror();
  1351. ilock(d);
  1352. flag = d->portm.flag;
  1353. task = d->port->task;
  1354. iunlock(d);
  1355. if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){
  1356. d->port->ci = 0; /* @? */
  1357. ahcirecover(&d->portc);
  1358. task = d->port->task;
  1359. }
  1360. d->active--;
  1361. qunlock(&d->portm);
  1362. if(flag == 0){
  1363. if(++try == 10){
  1364. print("%s: bad disk\n", name);
  1365. r->status = SDcheck;
  1366. return SDcheck;
  1367. }
  1368. iprint("%s: retry\n", name);
  1369. esleep(1000);
  1370. goto retry;
  1371. }
  1372. if(flag & Ferror){
  1373. iprint("%s: i/o error %ux\n", name, task);
  1374. r->status = SDcheck;
  1375. return SDcheck;
  1376. }
  1377. data += n;
  1378. r->rlen = data - (uchar*)r->data;
  1379. r->status = SDok;
  1380. return SDok;
  1381. }
  1382. static int
  1383. iario(SDreq *r)
  1384. {
  1385. int i, n, count, try, max, flag, task;
  1386. vlong lba;
  1387. char *name;
  1388. uchar *cmd, *data;
  1389. Aport *p;
  1390. Asleep as;
  1391. Ctlr *c;
  1392. Drive *d;
  1393. SDunit *unit;
  1394. unit = r->unit;
  1395. c = unit->dev->ctlr;
  1396. d = c->drive[unit->subno];
  1397. if(d->portm.feat & Datapi)
  1398. return iariopkt(r, d);
  1399. cmd = r->cmd;
  1400. name = d->unit->name;
  1401. p = d->port;
  1402. if(r->cmd[0] == 0x35 || r->cmd[0] == 0x91){
  1403. qlock(&d->portm);
  1404. i = flushcache(&d->portc);
  1405. qunlock(&d->portm);
  1406. if(i == 0)
  1407. return sdsetsense(r, SDok, 0, 0, 0);
  1408. return sdsetsense(r, SDcheck, 3, 0xc, 2);
  1409. }
  1410. if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){
  1411. r->status = i;
  1412. return i;
  1413. }
  1414. if(*cmd != 0x28 && *cmd != 0x2a){
  1415. print("%s: bad cmd 0x%.2ux\n", name, cmd[0]);
  1416. r->status = SDcheck;
  1417. return SDcheck;
  1418. }
  1419. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1420. count = cmd[7]<<8 | cmd[8];
  1421. if(r->data == nil)
  1422. return SDok;
  1423. if(r->dlen < count * unit->secsize)
  1424. count = r->dlen / unit->secsize;
  1425. max = 128;
  1426. try = 0;
  1427. retry:
  1428. if(waitready(d) == -1)
  1429. return SDeio;
  1430. data = r->data;
  1431. while(count > 0){
  1432. n = count;
  1433. if(n > max)
  1434. n = max;
  1435. d->active++;
  1436. ahcibuild(&d->portm, cmd, data, n, lba);
  1437. ilock(d);
  1438. d->portm.flag = 0;
  1439. iunlock(d);
  1440. p->ci = 1;
  1441. as.p = p;
  1442. as.i = 1;
  1443. d->intick = MACHP(0)->ticks;
  1444. while(waserror())
  1445. ;
  1446. sleep(&d->portm, ahciclear, &as);
  1447. poperror();
  1448. ilock(d);
  1449. flag = d->portm.flag;
  1450. task = d->port->task;
  1451. iunlock(d);
  1452. if(task & (Efatal<<8) ||
  1453. task & (ASbsy|ASdrq) && d->state == Dready){
  1454. d->port->ci = 0; /* @? */
  1455. ahcirecover(&d->portc);
  1456. task = d->port->task;
  1457. }
  1458. d->active--;
  1459. qunlock(&d->portm);
  1460. if(flag == 0){
  1461. if(++try == 10){
  1462. print("%s: bad disk\n", name);
  1463. r->status = SDeio;
  1464. return SDeio;
  1465. }
  1466. iprint("%s: retry %lld\n", name, lba);
  1467. esleep(1000);
  1468. goto retry;
  1469. }
  1470. if(flag & Ferror){
  1471. iprint("%s: i/o error %ux @%,lld\n", name, task, lba);
  1472. r->status = SDeio;
  1473. return SDeio;
  1474. }
  1475. count -= n;
  1476. lba += n;
  1477. data += n * unit->secsize;
  1478. }
  1479. r->rlen = data - (uchar*)r->data;
  1480. r->status = SDok;
  1481. return SDok;
  1482. }
  1483. /*
  1484. * configure drives 0-5 as ahci sata (c.f. errata)
  1485. */
  1486. static int
  1487. iaahcimode(Pcidev *p)
  1488. {
  1489. dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91), pcicfgr8(p, 92),
  1490. pcicfgr8(p, 93));
  1491. pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */
  1492. // pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */
  1493. return 0;
  1494. }
  1495. static void
  1496. iasetupahci(Ctlr *c)
  1497. {
  1498. /* disable cmd block decoding. */
  1499. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1500. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1501. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1502. c->lmmio[0xc/4] = (1 << 6) - 1; /* 5 ports. (supposedly ro pi reg.) */
  1503. /* enable ahci mode; from ich9 datasheet */
  1504. pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5);
  1505. }
  1506. static SDev*
  1507. iapnp(void)
  1508. {
  1509. int i, n, nunit, type;
  1510. ulong io;
  1511. Ctlr *c;
  1512. Drive *d;
  1513. Pcidev *p;
  1514. SDev *head, *tail, *s;
  1515. static int done;
  1516. if(done++)
  1517. return nil;
  1518. p = nil;
  1519. head = tail = nil;
  1520. loop:
  1521. while((p = pcimatch(p, 0, 0)) != nil){
  1522. if(p->vid == 0x8086 && (p->did & 0xfffc) == 0x2680)
  1523. type = Tesb;
  1524. else if(p->vid == 0x8086 && (p->did & 0xfffe) == 0x27c4)
  1525. type = Tich; /* 82801g[bh]m */
  1526. else if(p->vid == 0x1002 && p->did == 0x4380)
  1527. type = Tsb600;
  1528. else
  1529. continue;
  1530. if(niactlr == NCtlr){
  1531. print("%spnp: too many controllers\n", tname[type]);
  1532. break;
  1533. }
  1534. c = iactlr + niactlr;
  1535. s = sdevs + niactlr;
  1536. memset(c, 0, sizeof *c);
  1537. memset(s, 0, sizeof *s);
  1538. io = p->mem[Abar].bar & ~0xf;
  1539. c->mmio = vmap(io, p->mem[0].size);
  1540. if(c->mmio == 0){
  1541. print("%s: address 0x%luX in use did=%x\n",
  1542. tname[type], io, p->did);
  1543. continue;
  1544. }
  1545. c->lmmio = (ulong*)c->mmio;
  1546. c->pci = p;
  1547. c->type = type;
  1548. s->ifc = &sd63xxesbifc;
  1549. s->idno = 'E' + niactlr;
  1550. s->ctlr = c;
  1551. c->sdev = s;
  1552. if(Intel(c->type) && p->did != 0x2681)
  1553. iasetupahci(c);
  1554. nunit = ahciconf(c);
  1555. // ahcihbareset((Ahba*)c->mmio);
  1556. if(Intel(c->type) && iaahcimode(p) == -1)
  1557. break;
  1558. if(nunit < 1){
  1559. vunmap(c->mmio, p->mem[0].size);
  1560. continue;
  1561. }
  1562. s->nunit = nunit;
  1563. i = (c->hba->cap >> 21) & 1;
  1564. print("#S/sd%c: %s: sata-%s with %d ports\n", s->idno,
  1565. tname[c->type], "I\0II" + i*2, nunit);
  1566. /* map the drives -- they don't all need to be enabled. */
  1567. memset(c->rawdrive, 0, sizeof c->rawdrive);
  1568. n = 0;
  1569. for(i = 0; i < NCtlrdrv; i++) {
  1570. d = c->rawdrive + i;
  1571. d->portno = i;
  1572. d->driveno = -1;
  1573. d->sectors = 0;
  1574. d->ctlr = c;
  1575. if((c->hba->pi & (1<<i)) == 0)
  1576. continue;
  1577. d->port = (Aport*)(c->mmio + 0x80*i + 0x100);
  1578. d->portc.p = d->port;
  1579. d->portc.m = &d->portm;
  1580. d->driveno = n++;
  1581. c->drive[i] = d;
  1582. iadrive[d->driveno] = d;
  1583. }
  1584. for(i = 0; i < n; i++)
  1585. if(ahciidle(c->drive[i]->port) == -1){
  1586. dprint("%s: port %d wedged; abort\n",
  1587. tname[c->type], i);
  1588. goto loop;
  1589. }
  1590. for(i = 0; i < n; i++){
  1591. c->drive[i]->mode = DMsatai;
  1592. configdrive(c->drive[i]);
  1593. }
  1594. niadrive += nunit;
  1595. niactlr++;
  1596. if(head)
  1597. tail->next = s;
  1598. else
  1599. head = s;
  1600. tail = s;
  1601. }
  1602. return head;
  1603. }
  1604. static char* smarttab[] = {
  1605. "unset",
  1606. "error",
  1607. "threshold exceeded",
  1608. "normal"
  1609. };
  1610. static char *
  1611. pflag(char *s, char *e, uchar f)
  1612. {
  1613. uchar i;
  1614. for(i = 0; i < 8; i++)
  1615. if(f & (1 << i))
  1616. s = seprint(s, e, "%s ", flagname[i]);
  1617. return seprint(s, e, "\n");
  1618. }
  1619. static int
  1620. iarctl(SDunit *u, char *p, int l)
  1621. {
  1622. char buf[32];
  1623. char *e, *op;
  1624. Aport *o;
  1625. Ctlr *c;
  1626. Drive *d;
  1627. if((c = u->dev->ctlr) == nil)
  1628. return 0;
  1629. d = c->drive[u->subno];
  1630. o = d->port;
  1631. e = p+l;
  1632. op = p;
  1633. if(d->state == Dready){
  1634. p = seprint(p, e, "model\t%s\n", d->model);
  1635. p = seprint(p, e, "serial\t%s\n", d->serial);
  1636. p = seprint(p, e, "firm\t%s\n", d->firmware);
  1637. if(d->smartrs == 0xff)
  1638. p = seprint(p, e, "smart\tenable error\n");
  1639. else if(d->smartrs == 0)
  1640. p = seprint(p, e, "smart\tdisabled\n");
  1641. else
  1642. p = seprint(p, e, "smart\t%s\n",
  1643. smarttab[d->portm.smart]);
  1644. p = seprint(p, e, "flag\t");
  1645. p = pflag(p, e, d->portm.feat);
  1646. }else
  1647. p = seprint(p, e, "no disk present [%s]\n", diskstates[d->state]);
  1648. serrstr(o->serror, buf, buf + sizeof buf - 1);
  1649. p = seprint(p, e, "reg\ttask %ux cmd %ux serr %ux %s ci %ux is %ux; "
  1650. "sig %ux sstatus %04x\n", o->task, o->cmd, o->serror, buf,
  1651. o->ci, o->isr, o->sig, o->sstatus);
  1652. p = seprint(p, e, "geometry %llud 512\n", d->sectors);
  1653. return p - op;
  1654. }
  1655. static void
  1656. runflushcache(Drive *d)
  1657. {
  1658. long t0;
  1659. t0 = MACHP(0)->ticks;
  1660. qlock(&d->portm);
  1661. flushcache(&d->portc);
  1662. qunlock(&d->portm);
  1663. dprint("flush in %ldms\n", TK2MS(MACHP(0)->ticks-t0));
  1664. }
  1665. static void
  1666. forcemode(Drive *d, char *mode)
  1667. {
  1668. int i;
  1669. for(i = 0; i < nelem(modename); i++)
  1670. if(strcmp(mode, modename[i]) == 0)
  1671. break;
  1672. if(i == nelem(modename))
  1673. i = 0;
  1674. ilock(d);
  1675. d->mode = i;
  1676. iunlock(d);
  1677. }
  1678. static void
  1679. runsmartable(Drive *d, int i)
  1680. {
  1681. if(waserror()){
  1682. qunlock(&d->portm);
  1683. d->smartrs = 0;
  1684. nexterror();
  1685. }
  1686. qlock(&d->portm);
  1687. d->smartrs = smart(&d->portc, i);
  1688. d->portm.smart = 0;
  1689. qunlock(&d->portm);
  1690. poperror();
  1691. }
  1692. static void
  1693. forcestate(Drive *d, char *state)
  1694. {
  1695. int i;
  1696. for(i = 0; i < nelem(diskstates); i++)
  1697. if(strcmp(state, diskstates[i]) == 0)
  1698. break;
  1699. if(i == nelem(diskstates))
  1700. i = 0;
  1701. ilock(d);
  1702. d->state = i;
  1703. if(i == Dnull){
  1704. d->mediachange = 1;
  1705. d->unit->sectors = 0; /* force disk to disappear. */
  1706. }
  1707. iunlock(d);
  1708. }
  1709. static int
  1710. iawctl(SDunit *u, Cmdbuf *cmd)
  1711. {
  1712. char **f;
  1713. Ctlr *c;
  1714. Drive *d;
  1715. c = u->dev->ctlr;
  1716. d = c->drive[u->subno];
  1717. f = cmd->f;
  1718. if(strcmp(f[0], "flushcache") == 0)
  1719. runflushcache(d);
  1720. else if(strcmp(f[0], "identify") == 0){
  1721. uint i;
  1722. i = strtoul(f[1]? f[1]: "0", 0, 0);
  1723. if(i > 0xff)
  1724. i = 0;
  1725. dprint("%04d %ux\n", i, d->info[i]);
  1726. }else if(strcmp(f[0], "mode") == 0)
  1727. forcemode(d, f[1]? f[1]: "satai");
  1728. else if(strcmp(f[0], "nop") == 0){
  1729. if((d->portm.feat & Dnop) == 0){
  1730. cmderror(cmd, "nop command not supported");
  1731. return -1;
  1732. }
  1733. if(waserror()){
  1734. qunlock(&d->portm);
  1735. nexterror();
  1736. }
  1737. qlock(&d->portm);
  1738. nop(&d->portc);
  1739. qunlock(&d->portm);
  1740. poperror();
  1741. }else if(strcmp(f[0], "reset") == 0)
  1742. forcestate(d, "reset");
  1743. else if(strcmp(f[0], "smart") == 0){
  1744. if(d->smartrs == 0){
  1745. cmderror(cmd, "smart not enabled");
  1746. return -1;
  1747. }
  1748. if(waserror()){
  1749. qunlock(&d->portm);
  1750. d->smartrs = 0;
  1751. nexterror();
  1752. }
  1753. qlock(&d->portm);
  1754. d->portm.smart = 2 + smartrs(&d->portc);
  1755. qunlock(&d->portm);
  1756. poperror();
  1757. }else if(strcmp(f[0], "smartdisable") == 0)
  1758. runsmartable(d, 1);
  1759. else if(strcmp(f[0], "smartenable") == 0)
  1760. runsmartable(d, 0);
  1761. else if(strcmp(f[0], "state") == 0)
  1762. forcestate(d, f[1]? f[1]: "null");
  1763. else{
  1764. cmderror(cmd, Ebadctl);
  1765. return -1;
  1766. }
  1767. return 0;
  1768. }
  1769. static char *
  1770. portr(char *p, char *e, uint x)
  1771. {
  1772. int i, a;
  1773. p[0] = 0;
  1774. a = -1;
  1775. for(i = 0; i < 32; i++){
  1776. if((x & (1<<i)) == 0){
  1777. if(a != -1 && i - 1 != a)
  1778. p = seprint(p, e, "-%d", i - 1);
  1779. a = -1;
  1780. continue;
  1781. }
  1782. if(a == -1){
  1783. if(i > 0)
  1784. p = seprint(p, e, ", ");
  1785. p = seprint(p, e, "%d", a = i);
  1786. }
  1787. }
  1788. if(a != -1 && i - 1 != a)
  1789. p = seprint(p, e, "-%d", i - 1);
  1790. return p;
  1791. }
  1792. #define has(x, s) if(u & (x)) p = seprint(p, e, (s))
  1793. static char*
  1794. iartopctl(SDev *s, char *p, char *e)
  1795. {
  1796. u32int u;
  1797. char name[10], pr[25];
  1798. Ahba *h;
  1799. Ctlr *c;
  1800. c = s->ctlr;
  1801. snprint(name, sizeof name, "sd%c", s->idno);
  1802. p = seprint(p, e, "%s ahci ", name);
  1803. u = c->hba->cap;
  1804. has(Hs64a, "64a ");
  1805. has(Hsncq, "ncq ");
  1806. has(Hssntf, "ntf ");
  1807. has(Hsmps, "mps ");
  1808. has(Hsss, "ss ");
  1809. has(Hsalp, "alp ");
  1810. has(Hsal, "led ");
  1811. has(Hsclo, "clo ");
  1812. has(Hsam, "am ");
  1813. has(Hspm, "pm ");
  1814. has(Hssc, "slum ");
  1815. has(Hpsc, "pslum ");
  1816. has(Hcccs, "coal ");
  1817. has(Hems, "ems ");
  1818. has(Hsxs, "sxs ");
  1819. p = seprint(p, e, "\n");
  1820. p = seprint(p, e, "%s iss %d ncs %d np %d\n", name, (u>>20) & 0xf,
  1821. (u>>8) & 0x1f, 1 + (u & 0x1f));
  1822. h = c->hba;
  1823. portr(pr, pr + sizeof pr, h->pi);
  1824. p = seprint(p, e, "%s ghc %ux isr %ux pi %ux %s ver %ux\n",
  1825. name, h->ghc, h->isr, h->pi, pr, h->ver);
  1826. return p;
  1827. }
  1828. static int
  1829. iawtopctl(SDev *, Cmdbuf *cmd)
  1830. {
  1831. int *v;
  1832. char **f;
  1833. f = cmd->f;
  1834. v = 0;
  1835. if(strcmp(f[0], "debug") == 0)
  1836. v = &debug;
  1837. else if(strcmp(f[0], "idprint") == 0)
  1838. v = &prid;
  1839. else if(strcmp(f[0], "aprint") == 0)
  1840. v = &datapi;
  1841. else
  1842. cmderror(cmd, Ebadctl);
  1843. switch(cmd->nf){
  1844. default:
  1845. cmderror(cmd, Ebadarg);
  1846. case 1:
  1847. *v ^= 1;
  1848. break;
  1849. case 2:
  1850. *v = (strcmp(f[1], "on") == 0);
  1851. break;
  1852. }
  1853. return 0;
  1854. }
  1855. SDifc sd63xxesbifc = {
  1856. "iahci",
  1857. iapnp,
  1858. nil, /* legacy */
  1859. iaenable,
  1860. iadisable,
  1861. iaverify,
  1862. iaonline,
  1863. iario,
  1864. iarctl,
  1865. iawctl,
  1866. scsibio,
  1867. nil, /* probe */
  1868. nil, /* clear */
  1869. iartopctl,
  1870. iawtopctl,
  1871. };