dat.h 7.4 KB

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  1. typedef struct BIOS32si BIOS32si;
  2. typedef struct BIOS32ci BIOS32ci;
  3. typedef struct Conf Conf;
  4. typedef struct Confmem Confmem;
  5. typedef struct FPsave FPsave;
  6. typedef struct ISAConf ISAConf;
  7. typedef struct Label Label;
  8. typedef struct Lock Lock;
  9. typedef struct MMU MMU;
  10. typedef struct Mach Mach;
  11. typedef struct Notsave Notsave;
  12. typedef struct PCArch PCArch;
  13. typedef struct Pcidev Pcidev;
  14. typedef struct PCMmap PCMmap;
  15. typedef struct PCMslot PCMslot;
  16. typedef struct Page Page;
  17. typedef struct PMMU PMMU;
  18. typedef struct Proc Proc;
  19. typedef struct Segdesc Segdesc;
  20. typedef vlong Tval;
  21. typedef struct Ureg Ureg;
  22. typedef struct Vctl Vctl;
  23. #pragma incomplete BIOS32si
  24. #pragma incomplete Pcidev
  25. #pragma incomplete Ureg
  26. #define MAXSYSARG 5 /* for mount(fd, afd, mpt, flag, arg) */
  27. /*
  28. * parameters for sysproc.c
  29. */
  30. #define AOUT_MAGIC (I_MAGIC)
  31. struct Lock
  32. {
  33. ulong key;
  34. ulong sr;
  35. ulong pc;
  36. Proc *p;
  37. Mach *m;
  38. ushort isilock;
  39. long lockcycles;
  40. };
  41. struct Label
  42. {
  43. ulong sp;
  44. ulong pc;
  45. };
  46. /*
  47. * FPsave.status
  48. */
  49. enum
  50. {
  51. /* this is a state */
  52. FPinit= 0,
  53. FPactive= 1,
  54. FPinactive= 2,
  55. /* the following is a bit that can be or'd into the state */
  56. FPillegal= 0x100,
  57. };
  58. struct FPsave
  59. {
  60. ushort control;
  61. ushort r1;
  62. ushort status;
  63. ushort r2;
  64. ushort tag;
  65. ushort r3;
  66. ulong pc;
  67. ushort selector;
  68. ushort r4;
  69. ulong operand;
  70. ushort oselector;
  71. ushort r5;
  72. uchar regs[80]; /* floating point registers */
  73. };
  74. struct Confmem
  75. {
  76. ulong base;
  77. ulong npage;
  78. ulong kbase;
  79. ulong klimit;
  80. };
  81. struct Conf
  82. {
  83. ulong nmach; /* processors */
  84. ulong nproc; /* processes */
  85. ulong monitor; /* has monitor? */
  86. Confmem mem[4]; /* physical memory */
  87. ulong npage; /* total physical pages of memory */
  88. ulong upages; /* user page pool */
  89. ulong nimage; /* number of page cache image headers */
  90. ulong nswap; /* number of swap pages */
  91. int nswppo; /* max # of pageouts per segment pass */
  92. ulong base0; /* base of bank 0 */
  93. ulong base1; /* base of bank 1 */
  94. ulong copymode; /* 0 is copy on write, 1 is copy on reference */
  95. ulong ialloc; /* max interrupt time allocation in bytes */
  96. ulong pipeqsize; /* size in bytes of pipe queues */
  97. int nuart; /* number of uart devices */
  98. };
  99. /*
  100. * MMU stuff in proc
  101. */
  102. #define NCOLOR 1
  103. struct PMMU
  104. {
  105. Page* mmupdb; /* page directory base */
  106. Page* mmufree; /* unused page table pages */
  107. Page* mmuused; /* used page table pages */
  108. Page* kmaptable; /* page table used by kmap */
  109. uint lastkmap; /* last entry used by kmap */
  110. int nkmap; /* number of current kmaps */
  111. };
  112. /*
  113. * things saved in the Proc structure during a notify
  114. */
  115. struct Notsave
  116. {
  117. ulong svflags;
  118. ulong svcs;
  119. ulong svss;
  120. };
  121. #include "../port/portdat.h"
  122. typedef struct {
  123. ulong link; /* link (old TSS selector) */
  124. ulong esp0; /* privilege level 0 stack pointer */
  125. ulong ss0; /* privilege level 0 stack selector */
  126. ulong esp1; /* privilege level 1 stack pointer */
  127. ulong ss1; /* privilege level 1 stack selector */
  128. ulong esp2; /* privilege level 2 stack pointer */
  129. ulong ss2; /* privilege level 2 stack selector */
  130. ulong xcr3; /* page directory base register - not used because we don't use trap gates */
  131. ulong eip; /* instruction pointer */
  132. ulong eflags; /* flags register */
  133. ulong eax; /* general registers */
  134. ulong ecx;
  135. ulong edx;
  136. ulong ebx;
  137. ulong esp;
  138. ulong ebp;
  139. ulong esi;
  140. ulong edi;
  141. ulong es; /* segment selectors */
  142. ulong cs;
  143. ulong ss;
  144. ulong ds;
  145. ulong fs;
  146. ulong gs;
  147. ulong ldt; /* selector for task's LDT */
  148. ulong iomap; /* I/O map base address + T-bit */
  149. } Tss;
  150. struct Segdesc
  151. {
  152. ulong d0;
  153. ulong d1;
  154. };
  155. struct Mach
  156. {
  157. int machno; /* physical id of processor (KNOWN TO ASSEMBLY) */
  158. ulong splpc; /* pc of last caller to splhi */
  159. ulong* pdb; /* page directory base for this processor (va) */
  160. Tss* tss; /* tss for this processor */
  161. Segdesc *gdt; /* gdt for this processor */
  162. Proc* proc; /* current process on this processor */
  163. Proc* externup; /* extern register Proc *up */
  164. Page* pdbpool;
  165. int pdbcnt;
  166. ulong ticks; /* of the clock since boot time */
  167. Label sched; /* scheduler wakeup */
  168. Lock alarmlock; /* access to alarm list */
  169. void* alarm; /* alarms bound to this clock */
  170. int inclockintr;
  171. Proc* readied; /* for runproc */
  172. ulong schedticks; /* next forced context switch */
  173. int tlbfault;
  174. int tlbpurge;
  175. int pfault;
  176. int cs;
  177. int syscall;
  178. int load;
  179. int intr;
  180. int flushmmu; /* make current proc flush it's mmu state */
  181. int ilockdepth;
  182. Perf perf; /* performance counters */
  183. ulong spuriousintr;
  184. int lastintr;
  185. int loopconst;
  186. Lock apictimerlock;
  187. int cpumhz;
  188. uvlong cyclefreq; /* Frequency of user readable cycle counter */
  189. uvlong cpuhz;
  190. int cpuidax;
  191. int cpuiddx;
  192. char cpuidid[16];
  193. char* cpuidtype;
  194. int havetsc;
  195. int havepge;
  196. uvlong tscticks;
  197. int pdballoc;
  198. int pdbfree;
  199. vlong mtrrcap;
  200. vlong mtrrdef;
  201. vlong mtrrfix[11];
  202. vlong mtrrvar[32]; /* 256 max. */
  203. int stack[1];
  204. };
  205. /*
  206. * KMap the structure doesn't exist, but the functions do.
  207. */
  208. typedef struct KMap KMap;
  209. #define VA(k) ((void*)(k))
  210. KMap* kmap(Page*);
  211. void kunmap(KMap*);
  212. struct
  213. {
  214. Lock;
  215. int machs; /* bitmap of active CPUs */
  216. int exiting; /* shutdown */
  217. int ispanic; /* shutdown in response to a panic */
  218. int thunderbirdsarego; /* lets the added processors continue to schedinit */
  219. }active;
  220. /*
  221. * routines for things outside the PC model, like power management
  222. */
  223. struct PCArch
  224. {
  225. char* id;
  226. int (*ident)(void); /* this should be in the model */
  227. void (*reset)(void); /* this should be in the model */
  228. int (*serialpower)(int); /* 1 == on, 0 == off */
  229. int (*modempower)(int); /* 1 == on, 0 == off */
  230. void (*intrinit)(void);
  231. int (*intrenable)(Vctl*);
  232. int (*intrvecno)(int);
  233. int (*intrdisable)(int);
  234. void (*introff)(void);
  235. void (*intron)(void);
  236. void (*clockenable)(void);
  237. uvlong (*fastclock)(uvlong*);
  238. void (*timerset)(uvlong);
  239. };
  240. /* cpuid instruction result register bits */
  241. enum {
  242. /* dx */
  243. Fpuonchip = 1<<0,
  244. // Pse = 1<<3, /* page size extensions */
  245. Tsc = 1<<4, /* time-stamp counter */
  246. Cpumsr = 1<<5, /* model-specific registers, rdmsr/wrmsr */
  247. Pae = 1<<6, /* physical-addr extensions */
  248. Mce = 1<<7, /* machine-check exception */
  249. Cmpxchg8b = 1<<8,
  250. Cpuapic = 1<<9,
  251. Mtrr = 1<<12, /* memory-type range regs. */
  252. Pge = 1<<13, /* page global extension */
  253. // Pse2 = 1<<17, /* more page size extensions */
  254. Clflush = 1<<19,
  255. Mmx = 1<<23,
  256. Sse = 1<<25, /* thus sfence instr. */
  257. Sse2 = 1<<26, /* thus mfence & lfence instr.s */
  258. };
  259. /*
  260. * a parsed plan9.ini line
  261. */
  262. #define NISAOPT 8
  263. struct ISAConf {
  264. char *type;
  265. ulong port;
  266. int irq;
  267. ulong dma;
  268. ulong mem;
  269. ulong size;
  270. ulong freq;
  271. int nopt;
  272. char *opt[NISAOPT];
  273. };
  274. extern PCArch *arch; /* PC architecture */
  275. /*
  276. * Each processor sees its own Mach structure at address MACHADDR.
  277. * However, the Mach structures must also be available via the per-processor
  278. * MMU information array machp, mainly for disambiguation and access to
  279. * the clock which is only maintained by the bootstrap processor (0).
  280. */
  281. Mach* machp[MAXMACH];
  282. #define MACHP(n) (machp[n])
  283. extern Mach *m;
  284. #define up (((Mach*)MACHADDR)->externup)
  285. /*
  286. * hardware info about a device
  287. */
  288. typedef struct {
  289. ulong port;
  290. int size;
  291. } Devport;
  292. struct DevConf
  293. {
  294. ulong intnum; /* interrupt number */
  295. char *type; /* card type, malloced */
  296. int nports; /* Number of ports */
  297. Devport *ports; /* The ports themselves */
  298. };
  299. typedef struct BIOS32ci { /* BIOS32 Calling Interface */
  300. u32int eax;
  301. u32int ebx;
  302. u32int ecx;
  303. u32int edx;
  304. u32int esi;
  305. u32int edi;
  306. } BIOS32ci;