devarch.c 20 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "ureg.h"
  8. #include "../port/error.h"
  9. typedef struct IOMap IOMap;
  10. struct IOMap
  11. {
  12. IOMap *next;
  13. int reserved;
  14. char tag[13];
  15. ulong start;
  16. ulong end;
  17. };
  18. static struct
  19. {
  20. Lock;
  21. IOMap *m;
  22. IOMap *free;
  23. IOMap maps[32]; /* some initial free maps */
  24. QLock ql; /* lock for reading map */
  25. } iomap;
  26. enum {
  27. Qdir = 0,
  28. Qioalloc = 1,
  29. Qiob,
  30. Qiow,
  31. Qiol,
  32. Qbase,
  33. Qmax = 16,
  34. };
  35. typedef long Rdwrfn(Chan*, void*, long, vlong);
  36. static Rdwrfn *readfn[Qmax];
  37. static Rdwrfn *writefn[Qmax];
  38. static Dirtab archdir[Qmax] = {
  39. ".", { Qdir, 0, QTDIR }, 0, 0555,
  40. "ioalloc", { Qioalloc, 0 }, 0, 0444,
  41. "iob", { Qiob, 0 }, 0, 0660,
  42. "iow", { Qiow, 0 }, 0, 0660,
  43. "iol", { Qiol, 0 }, 0, 0660,
  44. };
  45. Lock archwlock; /* the lock is only for changing archdir */
  46. int narchdir = Qbase;
  47. int (*_pcmspecial)(char*, ISAConf*);
  48. void (*_pcmspecialclose)(int);
  49. static int doi8253set = 1;
  50. /*
  51. * Add a file to the #P listing. Once added, you can't delete it.
  52. * You can't add a file with the same name as one already there,
  53. * and you get a pointer to the Dirtab entry so you can do things
  54. * like change the Qid version. Changing the Qid path is disallowed.
  55. */
  56. Dirtab*
  57. addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
  58. {
  59. int i;
  60. Dirtab d;
  61. Dirtab *dp;
  62. memset(&d, 0, sizeof d);
  63. strcpy(d.name, name);
  64. d.perm = perm;
  65. lock(&archwlock);
  66. if(narchdir >= Qmax){
  67. unlock(&archwlock);
  68. return nil;
  69. }
  70. for(i=0; i<narchdir; i++)
  71. if(strcmp(archdir[i].name, name) == 0){
  72. unlock(&archwlock);
  73. return nil;
  74. }
  75. d.qid.path = narchdir;
  76. archdir[narchdir] = d;
  77. readfn[narchdir] = rdfn;
  78. writefn[narchdir] = wrfn;
  79. dp = &archdir[narchdir++];
  80. unlock(&archwlock);
  81. return dp;
  82. }
  83. void
  84. ioinit(void)
  85. {
  86. char *excluded;
  87. int i;
  88. for(i = 0; i < nelem(iomap.maps)-1; i++)
  89. iomap.maps[i].next = &iomap.maps[i+1];
  90. iomap.maps[i].next = nil;
  91. iomap.free = iomap.maps;
  92. /*
  93. * This is necessary to make the IBM X20 boot.
  94. * Have not tracked down the reason.
  95. * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
  96. */
  97. ioalloc(0x0fff, 1, 0, "dummy");
  98. if ((excluded = getconf("ioexclude")) != nil) {
  99. char *s;
  100. s = excluded;
  101. while (s && *s != '\0' && *s != '\n') {
  102. char *ends;
  103. int io_s, io_e;
  104. io_s = (int)strtol(s, &ends, 0);
  105. if (ends == nil || ends == s || *ends != '-') {
  106. print("ioinit: cannot parse option string\n");
  107. break;
  108. }
  109. s = ++ends;
  110. io_e = (int)strtol(s, &ends, 0);
  111. if (ends && *ends == ',')
  112. *ends++ = '\0';
  113. s = ends;
  114. ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
  115. }
  116. }
  117. }
  118. /*
  119. * Reserve a range to be ioalloced later.
  120. * This is in particular useful for exchangable cards, such
  121. * as pcmcia and cardbus cards.
  122. */
  123. int
  124. ioreserve(int, int size, int align, char *tag)
  125. {
  126. IOMap *m, **l;
  127. int i, port;
  128. lock(&iomap);
  129. /* find a free port above 0x400 and below 0x1000 */
  130. port = 0x400;
  131. for(l = &iomap.m; *l; l = &(*l)->next){
  132. m = *l;
  133. if (m->start < 0x400) continue;
  134. i = m->start - port;
  135. if(i > size)
  136. break;
  137. if(align > 0)
  138. port = ((port+align-1)/align)*align;
  139. else
  140. port = m->end;
  141. }
  142. if(*l == nil){
  143. unlock(&iomap);
  144. return -1;
  145. }
  146. m = iomap.free;
  147. if(m == nil){
  148. print("ioalloc: out of maps");
  149. unlock(&iomap);
  150. return port;
  151. }
  152. iomap.free = m->next;
  153. m->next = *l;
  154. m->start = port;
  155. m->end = port + size;
  156. m->reserved = 1;
  157. strncpy(m->tag, tag, sizeof(m->tag));
  158. m->tag[sizeof(m->tag)-1] = 0;
  159. *l = m;
  160. archdir[0].qid.vers++;
  161. unlock(&iomap);
  162. return m->start;
  163. }
  164. /*
  165. * alloc some io port space and remember who it was
  166. * alloced to. if port < 0, find a free region.
  167. */
  168. int
  169. ioalloc(int port, int size, int align, char *tag)
  170. {
  171. IOMap *m, **l;
  172. int i;
  173. lock(&iomap);
  174. if(port < 0){
  175. /* find a free port above 0x400 and below 0x1000 */
  176. port = 0x400;
  177. for(l = &iomap.m; *l; l = &(*l)->next){
  178. m = *l;
  179. if (m->start < 0x400) continue;
  180. i = m->start - port;
  181. if(i > size)
  182. break;
  183. if(align > 0)
  184. port = ((port+align-1)/align)*align;
  185. else
  186. port = m->end;
  187. }
  188. if(*l == nil){
  189. unlock(&iomap);
  190. return -1;
  191. }
  192. } else {
  193. /* Only 64KB I/O space on the x86. */
  194. if((port+size) > 0x10000){
  195. unlock(&iomap);
  196. return -1;
  197. }
  198. /* see if the space clashes with previously allocated ports */
  199. for(l = &iomap.m; *l; l = &(*l)->next){
  200. m = *l;
  201. if(m->end <= port)
  202. continue;
  203. if(m->reserved && m->start == port && m->end == port + size) {
  204. m->reserved = 0;
  205. unlock(&iomap);
  206. return m->start;
  207. }
  208. if(m->start >= port+size)
  209. break;
  210. unlock(&iomap);
  211. return -1;
  212. }
  213. }
  214. m = iomap.free;
  215. if(m == nil){
  216. print("ioalloc: out of maps");
  217. unlock(&iomap);
  218. return port;
  219. }
  220. iomap.free = m->next;
  221. m->next = *l;
  222. m->start = port;
  223. m->end = port + size;
  224. strncpy(m->tag, tag, sizeof(m->tag));
  225. m->tag[sizeof(m->tag)-1] = 0;
  226. *l = m;
  227. archdir[0].qid.vers++;
  228. unlock(&iomap);
  229. return m->start;
  230. }
  231. void
  232. iofree(int port)
  233. {
  234. IOMap *m, **l;
  235. lock(&iomap);
  236. for(l = &iomap.m; *l; l = &(*l)->next){
  237. if((*l)->start == port){
  238. m = *l;
  239. *l = m->next;
  240. m->next = iomap.free;
  241. iomap.free = m;
  242. break;
  243. }
  244. if((*l)->start > port)
  245. break;
  246. }
  247. archdir[0].qid.vers++;
  248. unlock(&iomap);
  249. }
  250. int
  251. iounused(int start, int end)
  252. {
  253. IOMap *m;
  254. for(m = iomap.m; m; m = m->next){
  255. if(start >= m->start && start < m->end
  256. || start <= m->start && end > m->start)
  257. return 0;
  258. }
  259. return 1;
  260. }
  261. static void
  262. checkport(int start, int end)
  263. {
  264. /* standard vga regs are OK */
  265. if(start >= 0x2b0 && end <= 0x2df+1)
  266. return;
  267. if(start >= 0x3c0 && end <= 0x3da+1)
  268. return;
  269. if(iounused(start, end))
  270. return;
  271. error(Eperm);
  272. }
  273. static Chan*
  274. archattach(char* spec)
  275. {
  276. return devattach('P', spec);
  277. }
  278. Walkqid*
  279. archwalk(Chan* c, Chan *nc, char** name, int nname)
  280. {
  281. return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
  282. }
  283. static int
  284. archstat(Chan* c, uchar* dp, int n)
  285. {
  286. return devstat(c, dp, n, archdir, narchdir, devgen);
  287. }
  288. static Chan*
  289. archopen(Chan* c, int omode)
  290. {
  291. return devopen(c, omode, archdir, narchdir, devgen);
  292. }
  293. static void
  294. archclose(Chan*)
  295. {
  296. }
  297. enum
  298. {
  299. Linelen= 31,
  300. };
  301. static long
  302. archread(Chan *c, void *a, long n, vlong offset)
  303. {
  304. char *buf, *p;
  305. int port;
  306. ushort *sp;
  307. ulong *lp;
  308. IOMap *m;
  309. Rdwrfn *fn;
  310. switch((ulong)c->qid.path){
  311. case Qdir:
  312. return devdirread(c, a, n, archdir, narchdir, devgen);
  313. case Qiob:
  314. port = offset;
  315. checkport(offset, offset+n);
  316. for(p = a; port < offset+n; port++)
  317. *p++ = inb(port);
  318. return n;
  319. case Qiow:
  320. if(n & 1)
  321. error(Ebadarg);
  322. checkport(offset, offset+n);
  323. sp = a;
  324. for(port = offset; port < offset+n; port += 2)
  325. *sp++ = ins(port);
  326. return n;
  327. case Qiol:
  328. if(n & 3)
  329. error(Ebadarg);
  330. checkport(offset, offset+n);
  331. lp = a;
  332. for(port = offset; port < offset+n; port += 4)
  333. *lp++ = inl(port);
  334. return n;
  335. case Qioalloc:
  336. break;
  337. default:
  338. if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
  339. return fn(c, a, n, offset);
  340. error(Eperm);
  341. break;
  342. }
  343. if((buf = malloc(n)) == nil)
  344. error(Enomem);
  345. p = buf;
  346. n = n/Linelen;
  347. offset = offset/Linelen;
  348. lock(&iomap);
  349. for(m = iomap.m; n > 0 && m != nil; m = m->next){
  350. if(offset-- > 0)
  351. continue;
  352. sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
  353. p += Linelen;
  354. n--;
  355. }
  356. unlock(&iomap);
  357. n = p - buf;
  358. memmove(a, buf, n);
  359. free(buf);
  360. return n;
  361. }
  362. static long
  363. archwrite(Chan *c, void *a, long n, vlong offset)
  364. {
  365. char *p;
  366. int port;
  367. ushort *sp;
  368. ulong *lp;
  369. Rdwrfn *fn;
  370. switch((ulong)c->qid.path){
  371. case Qiob:
  372. p = a;
  373. checkport(offset, offset+n);
  374. for(port = offset; port < offset+n; port++)
  375. outb(port, *p++);
  376. return n;
  377. case Qiow:
  378. if(n & 1)
  379. error(Ebadarg);
  380. checkport(offset, offset+n);
  381. sp = a;
  382. for(port = offset; port < offset+n; port += 2)
  383. outs(port, *sp++);
  384. return n;
  385. case Qiol:
  386. if(n & 3)
  387. error(Ebadarg);
  388. checkport(offset, offset+n);
  389. lp = a;
  390. for(port = offset; port < offset+n; port += 4)
  391. outl(port, *lp++);
  392. return n;
  393. default:
  394. if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
  395. return fn(c, a, n, offset);
  396. error(Eperm);
  397. break;
  398. }
  399. return 0;
  400. }
  401. Dev archdevtab = {
  402. 'P',
  403. "arch",
  404. devreset,
  405. devinit,
  406. devshutdown,
  407. archattach,
  408. archwalk,
  409. archstat,
  410. archopen,
  411. devcreate,
  412. archclose,
  413. archread,
  414. devbread,
  415. archwrite,
  416. devbwrite,
  417. devremove,
  418. devwstat,
  419. };
  420. /*
  421. * the following is a generic version of the
  422. * architecture specific stuff
  423. */
  424. static int
  425. unimplemented(int)
  426. {
  427. return 0;
  428. }
  429. static void
  430. nop(void)
  431. {
  432. }
  433. static void
  434. archreset(void)
  435. {
  436. i8042reset();
  437. /*
  438. * Often the BIOS hangs during restart if a conventional 8042
  439. * warm-boot sequence is tried. The following is Intel specific and
  440. * seems to perform a cold-boot, but at least it comes back.
  441. * And sometimes there is no keyboard...
  442. *
  443. * The reset register (0xcf9) is usually in one of the bridge
  444. * chips. The actual location and sequence could be extracted from
  445. * ACPI but why bother, this is the end of the line anyway.
  446. */
  447. print("Takes a licking and keeps on ticking...\n");
  448. *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
  449. outb(0xcf9, 0x02);
  450. outb(0xcf9, 0x06);
  451. for(;;)
  452. idle();
  453. }
  454. /*
  455. * 386 has no compare-and-swap instruction.
  456. * Run it with interrupts turned off instead.
  457. */
  458. static int
  459. cmpswap386(long *addr, long old, long new)
  460. {
  461. int r, s;
  462. s = splhi();
  463. if(r = (*addr == old))
  464. *addr = new;
  465. splx(s);
  466. return r;
  467. }
  468. /*
  469. * On a uniprocessor, you'd think that coherence could be nop,
  470. * but it can't. We still need a barrier when using coherence() in
  471. * device drivers.
  472. *
  473. * On VMware, it's safe (and a huge win) to set this to nop.
  474. * Aux/vmware does this via the #P/archctl file.
  475. */
  476. void (*coherence)(void) = nop;
  477. int (*cmpswap)(long*, long, long) = cmpswap386;
  478. PCArch* arch;
  479. extern PCArch* knownarch[];
  480. PCArch archgeneric = {
  481. .id= "generic",
  482. .ident= 0,
  483. .reset= archreset,
  484. .serialpower= unimplemented,
  485. .modempower= unimplemented,
  486. .intrinit= i8259init,
  487. .intrenable= i8259enable,
  488. .intrvecno= i8259vecno,
  489. .intrdisable= i8259disable,
  490. .intron= i8259on,
  491. .introff= i8259off,
  492. .clockenable= i8253enable,
  493. .fastclock= i8253read,
  494. .timerset= i8253timerset,
  495. };
  496. typedef struct X86type X86type;
  497. struct X86type {
  498. int family;
  499. int model;
  500. int aalcycles;
  501. char* name;
  502. };
  503. static X86type x86intel[] =
  504. {
  505. { 4, 0, 22, "486DX", }, /* known chips */
  506. { 4, 1, 22, "486DX50", },
  507. { 4, 2, 22, "486SX", },
  508. { 4, 3, 22, "486DX2", },
  509. { 4, 4, 22, "486SL", },
  510. { 4, 5, 22, "486SX2", },
  511. { 4, 7, 22, "DX2WB", }, /* P24D */
  512. { 4, 8, 22, "DX4", }, /* P24C */
  513. { 4, 9, 22, "DX4WB", }, /* P24CT */
  514. { 5, 0, 23, "P5", },
  515. { 5, 1, 23, "P5", },
  516. { 5, 2, 23, "P54C", },
  517. { 5, 3, 23, "P24T", },
  518. { 5, 4, 23, "P55C MMX", },
  519. { 5, 7, 23, "P54C VRT", },
  520. { 6, 1, 16, "PentiumPro", },/* trial and error */
  521. { 6, 3, 16, "PentiumII", },
  522. { 6, 5, 16, "PentiumII/Xeon", },
  523. { 6, 6, 16, "Celeron", },
  524. { 6, 7, 16, "PentiumIII/Xeon", },
  525. { 6, 8, 16, "PentiumIII/Xeon", },
  526. { 6, 0xB, 16, "PentiumIII/Xeon", },
  527. { 6, 0xF, 16, "Xeon5000-series", },
  528. { 0xF, 1, 16, "P4", }, /* P4 */
  529. { 0xF, 2, 16, "PentiumIV/Xeon", },
  530. { 3, -1, 32, "386", }, /* family defaults */
  531. { 4, -1, 22, "486", },
  532. { 5, -1, 23, "P5", },
  533. { 6, -1, 16, "P6", },
  534. { 0xF, -1, 16, "P4", }, /* P4 */
  535. { -1, -1, 16, "unknown", }, /* total default */
  536. };
  537. /*
  538. * The AMD processors all implement the CPUID instruction.
  539. * The later ones also return the processor name via functions
  540. * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
  541. * and DX:
  542. * K5 "AMD-K5(tm) Processor"
  543. * K6 "AMD-K6tm w/ multimedia extensions"
  544. * K6 3D "AMD-K6(tm) 3D processor"
  545. * K6 3D+ ?
  546. */
  547. static X86type x86amd[] =
  548. {
  549. { 5, 0, 23, "AMD-K5", }, /* guesswork */
  550. { 5, 1, 23, "AMD-K5", }, /* guesswork */
  551. { 5, 2, 23, "AMD-K5", }, /* guesswork */
  552. { 5, 3, 23, "AMD-K5", }, /* guesswork */
  553. { 5, 4, 23, "AMD Geode GX1", }, /* guesswork */
  554. { 5, 5, 23, "AMD Geode GX2", }, /* guesswork */
  555. { 5, 6, 11, "AMD-K6", }, /* trial and error */
  556. { 5, 7, 11, "AMD-K6", }, /* trial and error */
  557. { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
  558. { 5, 9, 11, "AMD-K6-III", },/* trial and error */
  559. { 5, 0xa, 23, "AMD Geode LX", }, /* guesswork */
  560. { 6, 1, 11, "AMD-Athlon", },/* trial and error */
  561. { 6, 2, 11, "AMD-Athlon", },/* trial and error */
  562. { 4, -1, 22, "Am486", }, /* guesswork */
  563. { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
  564. { 6, -1, 11, "AMD-Athlon", },/* guesswork */
  565. { 0xF, -1, 11, "AMD64", }, /* guesswork */
  566. { -1, -1, 11, "unknown", }, /* total default */
  567. };
  568. /*
  569. * WinChip 240MHz
  570. */
  571. static X86type x86winchip[] =
  572. {
  573. {5, 4, 23, "Winchip",}, /* guesswork */
  574. {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
  575. {6, 8, 23, "Via C3 Ezra-T",},
  576. {6, 9, 23, "Via C3 Eden-N",},
  577. { -1, -1, 23, "unknown", }, /* total default */
  578. };
  579. /*
  580. * SiS 55x
  581. */
  582. static X86type x86sis[] =
  583. {
  584. {5, 0, 23, "SiS 55x",}, /* guesswork */
  585. { -1, -1, 23, "unknown", }, /* total default */
  586. };
  587. static X86type *cputype;
  588. static void simplecycles(uvlong*);
  589. void (*cycles)(uvlong*) = simplecycles;
  590. void _cycles(uvlong*); /* in l.s */
  591. static void
  592. simplecycles(uvlong*x)
  593. {
  594. *x = m->ticks;
  595. }
  596. void
  597. cpuidprint(void)
  598. {
  599. int i;
  600. char buf[128];
  601. i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
  602. if(m->cpuidid[0])
  603. i += sprint(buf+i, "%12.12s ", m->cpuidid);
  604. seprint(buf+i, buf + sizeof buf - 1,
  605. "%s (cpuid: AX 0x%4.4uX DX 0x%4.4uX)\n",
  606. m->cpuidtype, m->cpuidax, m->cpuiddx);
  607. print(buf);
  608. }
  609. /*
  610. * figure out:
  611. * - cpu type
  612. * - whether or not we have a TSC (cycle counter)
  613. * - whether or not it supports page size extensions
  614. * (if so turn it on)
  615. * - whether or not it supports machine check exceptions
  616. * (if so turn it on)
  617. * - whether or not it supports the page global flag
  618. * (if so turn it on)
  619. */
  620. int
  621. cpuidentify(void)
  622. {
  623. char *p;
  624. int family, model, nomce;
  625. X86type *t, *tab;
  626. ulong cr4;
  627. vlong mca, mct;
  628. cpuid(m->cpuidid, &m->cpuidax, &m->cpuiddx);
  629. if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0 ||
  630. strncmp(m->cpuidid, "Geode by NSC", 12) == 0)
  631. tab = x86amd;
  632. else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
  633. tab = x86winchip;
  634. else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
  635. tab = x86sis;
  636. else
  637. tab = x86intel;
  638. family = X86FAMILY(m->cpuidax);
  639. model = X86MODEL(m->cpuidax);
  640. for(t=tab; t->name; t++)
  641. if((t->family == family && t->model == model)
  642. || (t->family == family && t->model == -1)
  643. || (t->family == -1))
  644. break;
  645. m->cpuidtype = t->name;
  646. /*
  647. * if there is one, set tsc to a known value
  648. */
  649. if(m->cpuiddx & Tsc){
  650. m->havetsc = 1;
  651. cycles = _cycles;
  652. if(m->cpuiddx & Cpumsr)
  653. wrmsr(0x10, 0);
  654. }
  655. /*
  656. * use i8253 to guess our cpu speed
  657. */
  658. guesscpuhz(t->aalcycles);
  659. /*
  660. * If machine check exception, page size extensions or page global bit
  661. * are supported enable them in CR4 and clear any other set extensions.
  662. * If machine check was enabled clear out any lingering status.
  663. */
  664. if(m->cpuiddx & (Pge|Mce|0x8)){
  665. cr4 = 0;
  666. if(m->cpuiddx & 0x08)
  667. cr4 |= 0x10; /* page size extensions */
  668. if(p = getconf("*nomce"))
  669. nomce = strtoul(p, 0, 0);
  670. else
  671. nomce = 0;
  672. if((m->cpuiddx & Mce) && !nomce){
  673. cr4 |= 0x40; /* machine check enable */
  674. if(family == 5){
  675. rdmsr(0x00, &mca);
  676. rdmsr(0x01, &mct);
  677. }
  678. }
  679. /*
  680. * Detect whether the chip supports the global bit
  681. * in page directory and page table entries. When set
  682. * in a particular entry, it means ``don't bother removing
  683. * this from the TLB when CR3 changes.''
  684. *
  685. * We flag all kernel pages with this bit. Doing so lessens the
  686. * overhead of switching processes on bare hardware,
  687. * even more so on VMware. See mmu.c:/^memglobal.
  688. *
  689. * For future reference, should we ever need to do a
  690. * full TLB flush, it can be accomplished by clearing
  691. * the PGE bit in CR4, writing to CR3, and then
  692. * restoring the PGE bit.
  693. */
  694. if(m->cpuiddx & Pge){
  695. cr4 |= 0x80; /* page global enable bit */
  696. m->havepge = 1;
  697. }
  698. putcr4(cr4);
  699. if(m->cpuiddx & Mce)
  700. rdmsr(0x01, &mct);
  701. }
  702. cputype = t;
  703. return t->family;
  704. }
  705. static long
  706. cputyperead(Chan*, void *a, long n, vlong offset)
  707. {
  708. char str[32];
  709. ulong mhz;
  710. mhz = (m->cpuhz+999999)/1000000;
  711. snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
  712. return readstr(offset, a, n, str);
  713. }
  714. static long
  715. archctlread(Chan*, void *a, long nn, vlong offset)
  716. {
  717. char buf[256];
  718. int n;
  719. n = snprint(buf, sizeof buf, "cpu %s %lud%s\n",
  720. cputype->name, (ulong)(m->cpuhz+999999)/1000000,
  721. m->havepge ? " pge" : "");
  722. n += snprint(buf+n, sizeof buf-n, "pge %s\n", getcr4()&0x80 ? "on" : "off");
  723. n += snprint(buf+n, sizeof buf-n, "coherence ");
  724. if(coherence == mb386)
  725. n += snprint(buf+n, sizeof buf-n, "mb386\n");
  726. else if(coherence == mb586)
  727. n += snprint(buf+n, sizeof buf-n, "mb586\n");
  728. else if(coherence == mfence)
  729. n += snprint(buf+n, sizeof buf-n, "mfence\n");
  730. else if(coherence == nop)
  731. n += snprint(buf+n, sizeof buf-n, "nop\n");
  732. else
  733. n += snprint(buf+n, sizeof buf-n, "0x%p\n", coherence);
  734. n += snprint(buf+n, sizeof buf-n, "cmpswap ");
  735. if(cmpswap == cmpswap386)
  736. n += snprint(buf+n, sizeof buf-n, "cmpswap386\n");
  737. else if(cmpswap == cmpswap486)
  738. n += snprint(buf+n, sizeof buf-n, "cmpswap486\n");
  739. else
  740. n += snprint(buf+n, sizeof buf-n, "0x%p\n", cmpswap);
  741. n += snprint(buf+n, sizeof buf-n, "i8253set %s\n", doi8253set ? "on" : "off");
  742. buf[n] = 0;
  743. return readstr(offset, a, nn, buf);
  744. }
  745. enum
  746. {
  747. CMpge,
  748. CMcoherence,
  749. CMi8253set,
  750. };
  751. static Cmdtab archctlmsg[] =
  752. {
  753. CMpge, "pge", 2,
  754. CMcoherence, "coherence", 2,
  755. CMi8253set, "i8253set", 2,
  756. };
  757. static long
  758. archctlwrite(Chan*, void *a, long n, vlong)
  759. {
  760. Cmdbuf *cb;
  761. Cmdtab *ct;
  762. cb = parsecmd(a, n);
  763. if(waserror()){
  764. free(cb);
  765. nexterror();
  766. }
  767. ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
  768. switch(ct->index){
  769. case CMpge:
  770. if(!m->havepge)
  771. error("processor does not support pge");
  772. if(strcmp(cb->f[1], "on") == 0)
  773. putcr4(getcr4() | 0x80);
  774. else if(strcmp(cb->f[1], "off") == 0)
  775. putcr4(getcr4() & ~0x80);
  776. else
  777. cmderror(cb, "invalid pge ctl");
  778. break;
  779. case CMcoherence:
  780. if(strcmp(cb->f[1], "mb386") == 0)
  781. coherence = mb386;
  782. else if(strcmp(cb->f[1], "mb586") == 0){
  783. if(X86FAMILY(m->cpuidax) < 5)
  784. error("invalid coherence ctl on this cpu family");
  785. coherence = mb586;
  786. }else if(strcmp(cb->f[1], "mfence") == 0){
  787. if((m->cpuiddx & Sse2) == 0)
  788. error("invalid coherence ctl on this cpu family");
  789. coherence = mfence;
  790. }else if(strcmp(cb->f[1], "nop") == 0){
  791. /* only safe on vmware */
  792. if(conf.nmach > 1)
  793. error("cannot disable coherence on a multiprocessor");
  794. coherence = nop;
  795. }else
  796. cmderror(cb, "invalid coherence ctl");
  797. break;
  798. case CMi8253set:
  799. if(strcmp(cb->f[1], "on") == 0)
  800. doi8253set = 1;
  801. else if(strcmp(cb->f[1], "off") == 0){
  802. doi8253set = 0;
  803. (*arch->timerset)(0);
  804. }else
  805. cmderror(cb, "invalid i2853set ctl");
  806. break;
  807. }
  808. free(cb);
  809. poperror();
  810. return n;
  811. }
  812. void
  813. archinit(void)
  814. {
  815. PCArch **p;
  816. arch = 0;
  817. for(p = knownarch; *p; p++){
  818. if((*p)->ident && (*p)->ident() == 0){
  819. arch = *p;
  820. break;
  821. }
  822. }
  823. if(arch == 0)
  824. arch = &archgeneric;
  825. else{
  826. if(arch->id == 0)
  827. arch->id = archgeneric.id;
  828. if(arch->reset == 0)
  829. arch->reset = archgeneric.reset;
  830. if(arch->serialpower == 0)
  831. arch->serialpower = archgeneric.serialpower;
  832. if(arch->modempower == 0)
  833. arch->modempower = archgeneric.modempower;
  834. if(arch->intrinit == 0)
  835. arch->intrinit = archgeneric.intrinit;
  836. if(arch->intrenable == 0)
  837. arch->intrenable = archgeneric.intrenable;
  838. }
  839. /*
  840. * Decide whether to use copy-on-reference (386 and mp).
  841. * We get another chance to set it in mpinit() for a
  842. * multiprocessor.
  843. */
  844. if(X86FAMILY(m->cpuidax) == 3)
  845. conf.copymode = 1;
  846. if(X86FAMILY(m->cpuidax) >= 4)
  847. cmpswap = cmpswap486;
  848. if(X86FAMILY(m->cpuidax) >= 5)
  849. coherence = mb586;
  850. if(m->cpuiddx & Sse2)
  851. coherence = mfence;
  852. addarchfile("cputype", 0444, cputyperead, nil);
  853. addarchfile("archctl", 0664, archctlread, archctlwrite);
  854. }
  855. /*
  856. * call either the pcmcia or pccard device setup
  857. */
  858. int
  859. pcmspecial(char *idstr, ISAConf *isa)
  860. {
  861. return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
  862. }
  863. /*
  864. * call either the pcmcia or pccard device teardown
  865. */
  866. void
  867. pcmspecialclose(int a)
  868. {
  869. if (_pcmspecialclose != nil)
  870. _pcmspecialclose(a);
  871. }
  872. /*
  873. * return value and speed of timer set in arch->clockenable
  874. */
  875. uvlong
  876. fastticks(uvlong *hz)
  877. {
  878. return (*arch->fastclock)(hz);
  879. }
  880. ulong
  881. µs(void)
  882. {
  883. return fastticks2us((*arch->fastclock)(nil));
  884. }
  885. /*
  886. * set next timer interrupt
  887. */
  888. void
  889. timerset(Tval x)
  890. {
  891. if(doi8253set)
  892. (*arch->timerset)(x);
  893. }