devi82365.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044
  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "../port/error.h"
  7. #include "io.h"
  8. /*
  9. * Intel 82365SL PCIC controller and compatibles.
  10. */
  11. enum
  12. {
  13. /*
  14. * registers indices
  15. */
  16. Rid= 0x0, /* identification and revision */
  17. Ris= 0x1, /* interface status */
  18. Rpc= 0x2, /* power control */
  19. Foutena= (1<<7), /* output enable */
  20. Fautopower= (1<<5), /* automatic power switching */
  21. Fcardena= (1<<4), /* PC card enable */
  22. Rigc= 0x3, /* interrupt and general control */
  23. Fiocard= (1<<5), /* I/O card (vs memory) */
  24. Fnotreset= (1<<6), /* reset if not set */
  25. FSMIena= (1<<4), /* enable change interrupt on SMI */
  26. Rcsc= 0x4, /* card status change */
  27. Rcscic= 0x5, /* card status change interrupt config */
  28. Fchangeena= (1<<3), /* card changed */
  29. Fbwarnena= (1<<1), /* card battery warning */
  30. Fbdeadena= (1<<0), /* card battery dead */
  31. Rwe= 0x6, /* address window enable */
  32. Fmem16= (1<<5), /* use A23-A12 to decode address */
  33. Rio= 0x7, /* I/O control */
  34. Fwidth16= (1<<0), /* 16 bit data width */
  35. Fiocs16= (1<<1), /* IOCS16 determines data width */
  36. Fzerows= (1<<2), /* zero wait state */
  37. Ftiming= (1<<3), /* timing register to use */
  38. Riobtm0lo= 0x8, /* I/O address 0 start low byte */
  39. Riobtm0hi= 0x9, /* I/O address 0 start high byte */
  40. Riotop0lo= 0xa, /* I/O address 0 stop low byte */
  41. Riotop0hi= 0xb, /* I/O address 0 stop high byte */
  42. Riobtm1lo= 0xc, /* I/O address 1 start low byte */
  43. Riobtm1hi= 0xd, /* I/O address 1 start high byte */
  44. Riotop1lo= 0xe, /* I/O address 1 stop low byte */
  45. Riotop1hi= 0xf, /* I/O address 1 stop high byte */
  46. Rmap= 0x10, /* map 0 */
  47. /*
  48. * CL-PD67xx extension registers
  49. */
  50. Rmisc1= 0x16, /* misc control 1 */
  51. F5Vdetect= (1<<0),
  52. Fvcc3V= (1<<1),
  53. Fpmint= (1<<2),
  54. Fpsirq= (1<<3),
  55. Fspeaker= (1<<4),
  56. Finpack= (1<<7),
  57. Rfifo= 0x17, /* fifo control */
  58. Fflush= (1<<7), /* flush fifo */
  59. Rmisc2= 0x1E, /* misc control 2 */
  60. Flowpow= (1<<1), /* low power mode */
  61. Rchipinfo= 0x1F, /* chip information */
  62. Ratactl= 0x26, /* ATA control */
  63. /*
  64. * offsets into the system memory address maps
  65. */
  66. Mbtmlo= 0x0, /* System mem addr mapping start low byte */
  67. Mbtmhi= 0x1, /* System mem addr mapping start high byte */
  68. F16bit= (1<<7), /* 16-bit wide data path */
  69. Mtoplo= 0x2, /* System mem addr mapping stop low byte */
  70. Mtophi= 0x3, /* System mem addr mapping stop high byte */
  71. Ftimer1= (1<<6), /* timer set 1 */
  72. Mofflo= 0x4, /* Card memory offset address low byte */
  73. Moffhi= 0x5, /* Card memory offset address high byte */
  74. Fregactive= (1<<6), /* attribute memory */
  75. /*
  76. * configuration registers - they start at an offset in attribute
  77. * memory found in the CIS.
  78. */
  79. Rconfig= 0,
  80. Creset= (1<<7), /* reset device */
  81. Clevel= (1<<6), /* level sensitive interrupt line */
  82. Cirq= (1<<2), /* IRQ enable */
  83. Cdecode= (1<<1), /* address decode */
  84. Cfunc= (1<<0), /* function enable */
  85. Riobase0= 5,
  86. Riobase1= 6,
  87. Riosize= 9,
  88. };
  89. #define MAP(x,o) (Rmap + (x)*0x8 + o)
  90. typedef struct I82365 I82365;
  91. /* a controller */
  92. enum
  93. {
  94. Ti82365,
  95. Tpd6710,
  96. Tpd6720,
  97. Tvg46x,
  98. };
  99. struct I82365
  100. {
  101. int type;
  102. int dev;
  103. int nslot;
  104. int xreg; /* index register address */
  105. int dreg; /* data register address */
  106. int irq;
  107. };
  108. static I82365 *controller[4];
  109. static int ncontroller;
  110. static PCMslot *slot;
  111. static PCMslot *lastslot;
  112. static nslot;
  113. static void i82365intr(Ureg*, void*);
  114. static int pcmio(int, ISAConf*);
  115. static long pcmread(int, int, void*, long, vlong);
  116. static long pcmwrite(int, int, void*, long, vlong);
  117. static void i82365dump(PCMslot*);
  118. /*
  119. * reading and writing card registers
  120. */
  121. static uchar
  122. rdreg(PCMslot *pp, int index)
  123. {
  124. outb(((I82365*)pp->cp)->xreg, pp->base + index);
  125. return inb(((I82365*)pp->cp)->dreg);
  126. }
  127. static void
  128. wrreg(PCMslot *pp, int index, uchar val)
  129. {
  130. outb(((I82365*)pp->cp)->xreg, pp->base + index);
  131. outb(((I82365*)pp->cp)->dreg, val);
  132. }
  133. /*
  134. * get info about card
  135. */
  136. static void
  137. slotinfo(PCMslot *pp)
  138. {
  139. uchar isr;
  140. isr = rdreg(pp, Ris);
  141. pp->occupied = (isr & (3<<2)) == (3<<2);
  142. pp->powered = isr & (1<<6);
  143. pp->battery = (isr & 3) == 3;
  144. pp->wrprot = isr & (1<<4);
  145. pp->busy = isr & (1<<5);
  146. pp->msec = TK2MS(MACHP(0)->ticks);
  147. }
  148. static int
  149. vcode(int volt)
  150. {
  151. switch(volt){
  152. case 5:
  153. return 1;
  154. case 12:
  155. return 2;
  156. default:
  157. return 0;
  158. }
  159. }
  160. /*
  161. * enable the slot card
  162. */
  163. static void
  164. slotena(PCMslot *pp)
  165. {
  166. if(pp->enabled)
  167. return;
  168. /* power up and unreset, wait's are empirical (???) */
  169. wrreg(pp, Rpc, Fautopower|Foutena|Fcardena);
  170. delay(300);
  171. wrreg(pp, Rigc, 0);
  172. delay(100);
  173. wrreg(pp, Rigc, Fnotreset);
  174. delay(500);
  175. /* get configuration */
  176. slotinfo(pp);
  177. if(pp->occupied){
  178. pcmcisread(pp);
  179. pp->enabled = 1;
  180. } else
  181. wrreg(pp, Rpc, Fautopower);
  182. }
  183. /*
  184. * disable the slot card
  185. */
  186. static void
  187. slotdis(PCMslot *pp)
  188. {
  189. wrreg(pp, Rpc, 0); /* turn off card power */
  190. wrreg(pp, Rwe, 0); /* no windows */
  191. pp->enabled = 0;
  192. }
  193. /*
  194. * status change interrupt
  195. */
  196. static void
  197. i82365intr(Ureg *, void *)
  198. {
  199. uchar csc, was;
  200. PCMslot *pp;
  201. if(slot == 0)
  202. return;
  203. for(pp = slot; pp < lastslot; pp++){
  204. csc = rdreg(pp, Rcsc);
  205. was = pp->occupied;
  206. slotinfo(pp);
  207. if(csc & (1<<3) && was != pp->occupied){
  208. if(!pp->occupied)
  209. slotdis(pp);
  210. }
  211. }
  212. }
  213. enum
  214. {
  215. Mshift= 12,
  216. Mgran= (1<<Mshift), /* granularity of maps */
  217. Mmask= ~(Mgran-1), /* mask for address bits important to the chip */
  218. };
  219. /*
  220. * get a map for pc card region, return corrected len
  221. */
  222. PCMmap*
  223. pcmmap(int slotno, ulong offset, int len, int attr)
  224. {
  225. PCMslot *pp;
  226. uchar we, bit;
  227. PCMmap *m, *nm;
  228. int i;
  229. ulong e;
  230. pp = slot + slotno;
  231. lock(&pp->mlock);
  232. /* convert offset to granularity */
  233. if(len <= 0)
  234. len = 1;
  235. e = ROUND(offset+len, Mgran);
  236. offset &= Mmask;
  237. len = e - offset;
  238. /* look for a map that covers the right area */
  239. we = rdreg(pp, Rwe);
  240. bit = 1;
  241. nm = 0;
  242. for(m = pp->mmap; m < &pp->mmap[nelem(pp->mmap)]; m++){
  243. if((we & bit))
  244. if(m->attr == attr)
  245. if(offset >= m->ca && e <= m->cea){
  246. m->ref++;
  247. unlock(&pp->mlock);
  248. return m;
  249. }
  250. bit <<= 1;
  251. if(nm == 0 && m->ref == 0)
  252. nm = m;
  253. }
  254. m = nm;
  255. if(m == 0){
  256. unlock(&pp->mlock);
  257. return 0;
  258. }
  259. /* if isa space isn't big enough, free it and get more */
  260. if(m->len < len){
  261. if(m->isa){
  262. umbfree(m->isa, m->len);
  263. m->len = 0;
  264. }
  265. m->isa = PADDR(umbmalloc(0, len, Mgran));
  266. if(m->isa == 0){
  267. print("pcmmap: out of isa space\n");
  268. unlock(&pp->mlock);
  269. return 0;
  270. }
  271. m->len = len;
  272. }
  273. /* set up new map */
  274. m->ca = offset;
  275. m->cea = m->ca + m->len;
  276. m->attr = attr;
  277. i = m-pp->mmap;
  278. bit = 1<<i;
  279. wrreg(pp, Rwe, we & ~bit); /* disable map before changing it */
  280. wrreg(pp, MAP(i, Mbtmlo), m->isa>>Mshift);
  281. wrreg(pp, MAP(i, Mbtmhi), (m->isa>>(Mshift+8)) | F16bit);
  282. wrreg(pp, MAP(i, Mtoplo), (m->isa+m->len-1)>>Mshift);
  283. wrreg(pp, MAP(i, Mtophi), ((m->isa+m->len-1)>>(Mshift+8)));
  284. offset -= m->isa;
  285. offset &= (1<<25)-1;
  286. offset >>= Mshift;
  287. wrreg(pp, MAP(i, Mofflo), offset);
  288. wrreg(pp, MAP(i, Moffhi), (offset>>8) | (attr ? Fregactive : 0));
  289. wrreg(pp, Rwe, we | bit); /* enable map */
  290. m->ref = 1;
  291. unlock(&pp->mlock);
  292. return m;
  293. }
  294. void
  295. pcmunmap(int slotno, PCMmap* m)
  296. {
  297. PCMslot *pp;
  298. pp = slot + slotno;
  299. lock(&pp->mlock);
  300. m->ref--;
  301. unlock(&pp->mlock);
  302. }
  303. static void
  304. increfp(PCMslot *pp)
  305. {
  306. lock(pp);
  307. if(pp->ref++ == 0)
  308. slotena(pp);
  309. unlock(pp);
  310. }
  311. static void
  312. decrefp(PCMslot *pp)
  313. {
  314. lock(pp);
  315. if(pp->ref-- == 1)
  316. slotdis(pp);
  317. unlock(pp);
  318. }
  319. /*
  320. * look for a card whose version contains 'idstr'
  321. */
  322. static int
  323. pcmcia_pcmspecial(char *idstr, ISAConf *isa)
  324. {
  325. PCMslot *pp;
  326. extern char *strstr(char*, char*);
  327. int enabled;
  328. for(pp = slot; pp < lastslot; pp++){
  329. if(pp->special)
  330. continue; /* already taken */
  331. /*
  332. * make sure we don't power on cards when we already know what's
  333. * in them. We'll reread every two minutes if necessary
  334. */
  335. enabled = 0;
  336. if (pp->msec == ~0 || TK2MS(MACHP(0)->ticks) - pp->msec > 120000){
  337. increfp(pp);
  338. enabled++;
  339. }
  340. if(pp->occupied) {
  341. if(strstr(pp->verstr, idstr)){
  342. if (!enabled){
  343. enabled = 1;
  344. increfp(pp);
  345. }
  346. if(isa == 0 || pcmio(pp->slotno, isa) == 0){
  347. pp->special = 1;
  348. return pp->slotno;
  349. }
  350. }
  351. } else
  352. pp->special = 1;
  353. if (enabled)
  354. decrefp(pp);
  355. }
  356. return -1;
  357. }
  358. static void
  359. pcmcia_pcmspecialclose(int slotno)
  360. {
  361. PCMslot *pp;
  362. if(slotno >= nslot)
  363. panic("pcmspecialclose");
  364. pp = slot + slotno;
  365. pp->special = 0;
  366. decrefp(pp);
  367. }
  368. enum
  369. {
  370. Qdir,
  371. Qmem,
  372. Qattr,
  373. Qctl,
  374. Nents = 3,
  375. };
  376. #define SLOTNO(c) ((ulong)((c->qid.path>>8)&0xff))
  377. #define TYPE(c) ((ulong)(c->qid.path&0xff))
  378. #define QID(s,t) (((s)<<8)|(t))
  379. static int
  380. pcmgen(Chan *c, char*, Dirtab *, int , int i, Dir *dp)
  381. {
  382. int slotno;
  383. Qid qid;
  384. long len;
  385. PCMslot *pp;
  386. if(i == DEVDOTDOT){
  387. mkqid(&qid, Qdir, 0, QTDIR);
  388. devdir(c, qid, "#y", 0, eve, 0555, dp);
  389. return 1;
  390. }
  391. if(i >= Nents*nslot)
  392. return -1;
  393. slotno = i/Nents;
  394. pp = slot + slotno;
  395. len = 0;
  396. switch(i%Nents){
  397. case 0:
  398. qid.path = QID(slotno, Qmem);
  399. snprint(up->genbuf, sizeof up->genbuf, "pcm%dmem", slotno);
  400. len = pp->memlen;
  401. break;
  402. case 1:
  403. qid.path = QID(slotno, Qattr);
  404. snprint(up->genbuf, sizeof up->genbuf, "pcm%dattr", slotno);
  405. len = pp->memlen;
  406. break;
  407. case 2:
  408. qid.path = QID(slotno, Qctl);
  409. snprint(up->genbuf, sizeof up->genbuf, "pcm%dctl", slotno);
  410. break;
  411. }
  412. qid.vers = 0;
  413. qid.type = QTFILE;
  414. devdir(c, qid, up->genbuf, len, eve, 0660, dp);
  415. return 1;
  416. }
  417. static char *chipname[] =
  418. {
  419. [Ti82365] "Intel 82365SL",
  420. [Tpd6710] "Cirrus Logic CL-PD6710",
  421. [Tpd6720] "Cirrus Logic CL-PD6720",
  422. [Tvg46x] "Vadem VG-46x",
  423. };
  424. static I82365*
  425. i82365probe(int x, int d, int dev)
  426. {
  427. uchar c, id;
  428. I82365 *cp;
  429. ISAConf isa;
  430. int i, nslot;
  431. outb(x, Rid + (dev<<7));
  432. id = inb(d);
  433. if((id & 0xf0) != 0x80)
  434. return 0; /* not a memory & I/O card */
  435. if((id & 0x0f) == 0x00)
  436. return 0; /* no revision number, not possible */
  437. cp = xalloc(sizeof(I82365));
  438. cp->xreg = x;
  439. cp->dreg = d;
  440. cp->dev = dev;
  441. cp->type = Ti82365;
  442. cp->nslot = 2;
  443. switch(id){
  444. case 0x82:
  445. case 0x83:
  446. case 0x84:
  447. /* could be a cirrus */
  448. outb(x, Rchipinfo + (dev<<7));
  449. outb(d, 0);
  450. c = inb(d);
  451. if((c & 0xc0) != 0xc0)
  452. break;
  453. c = inb(d);
  454. if((c & 0xc0) != 0x00)
  455. break;
  456. if(c & 0x20){
  457. cp->type = Tpd6720;
  458. } else {
  459. cp->type = Tpd6710;
  460. cp->nslot = 1;
  461. }
  462. /* low power mode */
  463. outb(x, Rmisc2 + (dev<<7));
  464. c = inb(d);
  465. outb(d, c & ~Flowpow);
  466. break;
  467. }
  468. /* if it's not a Cirrus, it could be a Vadem... */
  469. if(cp->type == Ti82365){
  470. /* unlock the Vadem extended regs */
  471. outb(x, 0x0E + (dev<<7));
  472. outb(x, 0x37 + (dev<<7));
  473. /* make the id register show the Vadem id */
  474. outb(x, 0x3A + (dev<<7));
  475. c = inb(d);
  476. outb(d, c|0xC0);
  477. outb(x, Rid + (dev<<7));
  478. c = inb(d);
  479. if(c & 0x08)
  480. cp->type = Tvg46x;
  481. /* go back to Intel compatible id */
  482. outb(x, 0x3A + (dev<<7));
  483. c = inb(d);
  484. outb(d, c & ~0xC0);
  485. }
  486. memset(&isa, 0, sizeof(ISAConf));
  487. if(isaconfig("pcmcia", ncontroller, &isa) && isa.irq)
  488. cp->irq = isa.irq;
  489. else
  490. cp->irq = IrqPCMCIA;
  491. for(i = 0; i < isa.nopt; i++){
  492. if(cistrncmp(isa.opt[i], "nslot=", 6))
  493. continue;
  494. nslot = strtol(&isa.opt[i][6], nil, 0);
  495. if(nslot > 0 && nslot <= 2)
  496. cp->nslot = nslot;
  497. }
  498. controller[ncontroller++] = cp;
  499. return cp;
  500. }
  501. static void
  502. i82365dump(PCMslot *pp)
  503. {
  504. int i;
  505. for(i = 0; i < 0x40; i++){
  506. if((i&0x0F) == 0)
  507. print("\n%2.2uX: ", i);
  508. print("%2.2uX ", rdreg(pp, i));
  509. if(((i+1) & 0x0F) == 0x08)
  510. print(" - ");
  511. }
  512. print("\n");
  513. }
  514. /*
  515. * set up for slot cards
  516. */
  517. void
  518. devi82365link(void)
  519. {
  520. static int already;
  521. int i, j;
  522. I82365 *cp;
  523. PCMslot *pp;
  524. char buf[32], *p;
  525. if(already)
  526. return;
  527. already = 1;
  528. if((p=getconf("pcmcia0")) && strncmp(p, "disabled", 8)==0)
  529. return;
  530. if(_pcmspecial)
  531. return;
  532. /* look for controllers if the ports aren't already taken */
  533. if(ioalloc(0x3E0, 2, 0, "i82365.0") >= 0){
  534. i82365probe(0x3E0, 0x3E1, 0);
  535. i82365probe(0x3E0, 0x3E1, 1);
  536. if(ncontroller == 0)
  537. iofree(0x3E0);
  538. }
  539. if(ioalloc(0x3E2, 2, 0, "i82365.1") >= 0){
  540. i = ncontroller;
  541. i82365probe(0x3E2, 0x3E3, 0);
  542. i82365probe(0x3E2, 0x3E3, 1);
  543. if(ncontroller == i)
  544. iofree(0x3E2);
  545. }
  546. if(ncontroller == 0)
  547. return;
  548. _pcmspecial = pcmcia_pcmspecial;
  549. _pcmspecialclose = pcmcia_pcmspecialclose;
  550. for(i = 0; i < ncontroller; i++)
  551. nslot += controller[i]->nslot;
  552. slot = xalloc(nslot * sizeof(PCMslot));
  553. lastslot = slot;
  554. for(i = 0; i < ncontroller; i++){
  555. cp = controller[i];
  556. print("#y%d: %d slot %s: port 0x%uX irq %d\n",
  557. i, cp->nslot, chipname[cp->type], cp->xreg, cp->irq);
  558. for(j = 0; j < cp->nslot; j++){
  559. pp = lastslot++;
  560. pp->slotno = pp - slot;
  561. pp->memlen = 64*MB;
  562. pp->base = (cp->dev<<7) | (j<<6);
  563. pp->cp = cp;
  564. pp->msec = ~0;
  565. pp->verstr[0] = 0;
  566. slotdis(pp);
  567. /* interrupt on status change */
  568. wrreg(pp, Rcscic, (cp->irq<<4) | Fchangeena);
  569. rdreg(pp, Rcsc);
  570. }
  571. /* for card management interrupts */
  572. snprint(buf, sizeof buf, "i82365.%d", i);
  573. intrenable(cp->irq, i82365intr, 0, BUSUNKNOWN, buf);
  574. }
  575. }
  576. static Chan*
  577. i82365attach(char *spec)
  578. {
  579. return devattach('y', spec);
  580. }
  581. static Walkqid*
  582. i82365walk(Chan *c, Chan *nc, char **name, int nname)
  583. {
  584. return devwalk(c, nc, name, nname, 0, 0, pcmgen);
  585. }
  586. static int
  587. i82365stat(Chan *c, uchar *db, int n)
  588. {
  589. return devstat(c, db, n, 0, 0, pcmgen);
  590. }
  591. static Chan*
  592. i82365open(Chan *c, int omode)
  593. {
  594. if(c->qid.type & QTDIR){
  595. if(omode != OREAD)
  596. error(Eperm);
  597. } else
  598. increfp(slot + SLOTNO(c));
  599. c->mode = openmode(omode);
  600. c->flag |= COPEN;
  601. c->offset = 0;
  602. return c;
  603. }
  604. static void
  605. i82365close(Chan *c)
  606. {
  607. if(c->flag & COPEN)
  608. if((c->qid.type & QTDIR) == 0)
  609. decrefp(slot+SLOTNO(c));
  610. }
  611. /* a memmove using only bytes */
  612. static void
  613. memmoveb(uchar *to, uchar *from, int n)
  614. {
  615. while(n-- > 0)
  616. *to++ = *from++;
  617. }
  618. /* a memmove using only shorts & bytes */
  619. static void
  620. memmoves(uchar *to, uchar *from, int n)
  621. {
  622. ushort *t, *f;
  623. if((((ulong)to) & 1) || (((ulong)from) & 1) || (n & 1)){
  624. while(n-- > 0)
  625. *to++ = *from++;
  626. } else {
  627. n = n/2;
  628. t = (ushort*)to;
  629. f = (ushort*)from;
  630. while(n-- > 0)
  631. *t++ = *f++;
  632. }
  633. }
  634. static long
  635. pcmread(int slotno, int attr, void *a, long n, vlong off)
  636. {
  637. int i, len;
  638. PCMmap *m;
  639. uchar *ac;
  640. PCMslot *pp;
  641. ulong offset = off;
  642. pp = slot + slotno;
  643. if(pp->memlen < offset)
  644. return 0;
  645. if(pp->memlen < offset + n)
  646. n = pp->memlen - offset;
  647. m = 0;
  648. if(waserror()){
  649. if(m)
  650. pcmunmap(pp->slotno, m);
  651. nexterror();
  652. }
  653. ac = a;
  654. for(len = n; len > 0; len -= i){
  655. m = pcmmap(pp->slotno, offset, 0, attr);
  656. if(m == 0)
  657. error("cannot map PCMCIA card");
  658. if(offset + len > m->cea)
  659. i = m->cea - offset;
  660. else
  661. i = len;
  662. memmoveb(ac, KADDR(m->isa + offset - m->ca), i);
  663. pcmunmap(pp->slotno, m);
  664. offset += i;
  665. ac += i;
  666. }
  667. poperror();
  668. return n;
  669. }
  670. static long
  671. i82365read(Chan *c, void *a, long n, vlong off)
  672. {
  673. char *p, *buf, *e;
  674. PCMslot *pp;
  675. ulong offset = off;
  676. switch(TYPE(c)){
  677. case Qdir:
  678. return devdirread(c, a, n, 0, 0, pcmgen);
  679. case Qmem:
  680. case Qattr:
  681. return pcmread(SLOTNO(c), TYPE(c) == Qattr, a, n, off);
  682. case Qctl:
  683. buf = p = malloc(READSTR);
  684. e = p + READSTR;
  685. pp = slot + SLOTNO(c);
  686. buf[0] = 0;
  687. if(pp->occupied){
  688. p = seprint(p, e, "occupied\n");
  689. if(pp->verstr[0])
  690. p = seprint(p, e, "version %s\n", pp->verstr);
  691. }
  692. if(pp->enabled)
  693. p = seprint(p, e, "enabled\n");
  694. if(pp->powered)
  695. p = seprint(p, e, "powered\n");
  696. if(pp->configed)
  697. p = seprint(p, e, "configed\n");
  698. if(pp->wrprot)
  699. p = seprint(p, e, "write protected\n");
  700. if(pp->busy)
  701. p = seprint(p, e, "busy\n");
  702. seprint(p, e, "battery lvl %d\n", pp->battery);
  703. n = readstr(offset, a, n, buf);
  704. free(buf);
  705. return n;
  706. }
  707. error(Ebadarg);
  708. return -1; /* not reached */
  709. }
  710. static long
  711. pcmwrite(int dev, int attr, void *a, long n, vlong off)
  712. {
  713. int i, len;
  714. PCMmap *m;
  715. uchar *ac;
  716. PCMslot *pp;
  717. ulong offset = off;
  718. pp = slot + dev;
  719. if(pp->memlen < offset)
  720. return 0;
  721. if(pp->memlen < offset + n)
  722. n = pp->memlen - offset;
  723. m = 0;
  724. if(waserror()){
  725. if(m)
  726. pcmunmap(pp->slotno, m);
  727. nexterror();
  728. }
  729. ac = a;
  730. for(len = n; len > 0; len -= i){
  731. m = pcmmap(pp->slotno, offset, 0, attr);
  732. if(m == 0)
  733. error("cannot map PCMCIA card");
  734. if(offset + len > m->cea)
  735. i = m->cea - offset;
  736. else
  737. i = len;
  738. memmoveb(KADDR(m->isa + offset - m->ca), ac, i);
  739. pcmunmap(pp->slotno, m);
  740. offset += i;
  741. ac += i;
  742. }
  743. poperror();
  744. return n;
  745. }
  746. static long
  747. i82365write(Chan *c, void *a, long n, vlong off)
  748. {
  749. PCMslot *pp;
  750. char buf[32];
  751. switch(TYPE(c)){
  752. case Qctl:
  753. if(n >= sizeof(buf))
  754. n = sizeof(buf) - 1;
  755. strncpy(buf, a, n);
  756. buf[n] = 0;
  757. pp = slot + SLOTNO(c);
  758. if(!pp->occupied)
  759. error(Eio);
  760. /* set vpp on card */
  761. if(strncmp(buf, "vpp", 3) == 0)
  762. wrreg(pp, Rpc, vcode(atoi(buf+3))|Fautopower|Foutena|Fcardena);
  763. return n;
  764. case Qmem:
  765. case Qattr:
  766. pp = slot + SLOTNO(c);
  767. if(pp->occupied == 0 || pp->enabled == 0)
  768. error(Eio);
  769. n = pcmwrite(pp->slotno, TYPE(c) == Qattr, a, n, off);
  770. if(n < 0)
  771. error(Eio);
  772. return n;
  773. }
  774. error(Ebadarg);
  775. return -1; /* not reached */
  776. }
  777. Dev i82365devtab = {
  778. 'y',
  779. "i82365",
  780. devreset,
  781. devinit,
  782. devshutdown,
  783. i82365attach,
  784. i82365walk,
  785. i82365stat,
  786. i82365open,
  787. devcreate,
  788. i82365close,
  789. i82365read,
  790. devbread,
  791. i82365write,
  792. devbwrite,
  793. devremove,
  794. devwstat,
  795. };
  796. /*
  797. * configure the PCMslot for IO. We assume very heavily that we can read
  798. * configuration info from the CIS. If not, we won't set up correctly.
  799. */
  800. static int
  801. pcmio(int slotno, ISAConf *isa)
  802. {
  803. uchar we, x, *p;
  804. PCMslot *pp;
  805. PCMconftab *ct, *et, *t;
  806. PCMmap *m;
  807. int i, index, irq;
  808. char *cp;
  809. irq = isa->irq;
  810. if(irq == 2)
  811. irq = 9;
  812. if(slotno > nslot)
  813. return -1;
  814. pp = slot + slotno;
  815. if(!pp->occupied)
  816. return -1;
  817. et = &pp->ctab[pp->nctab];
  818. ct = 0;
  819. for(i = 0; i < isa->nopt; i++){
  820. if(strncmp(isa->opt[i], "index=", 6))
  821. continue;
  822. index = strtol(&isa->opt[i][6], &cp, 0);
  823. if(cp == &isa->opt[i][6] || index >= pp->nctab)
  824. return -1;
  825. ct = &pp->ctab[index];
  826. }
  827. if(ct == 0){
  828. /* assume default is right */
  829. if(pp->def)
  830. ct = pp->def;
  831. else
  832. ct = pp->ctab;
  833. /* try for best match */
  834. if(ct->nio == 0
  835. || ct->io[0].start != isa->port || ((1<<irq) & ct->irqs) == 0){
  836. for(t = pp->ctab; t < et; t++)
  837. if(t->nio
  838. && t->io[0].start == isa->port
  839. && ((1<<irq) & t->irqs)){
  840. ct = t;
  841. break;
  842. }
  843. }
  844. if(ct->nio == 0 || ((1<<irq) & ct->irqs) == 0){
  845. for(t = pp->ctab; t < et; t++)
  846. if(t->nio && ((1<<irq) & t->irqs)){
  847. ct = t;
  848. break;
  849. }
  850. }
  851. if(ct->nio == 0){
  852. for(t = pp->ctab; t < et; t++)
  853. if(t->nio){
  854. ct = t;
  855. break;
  856. }
  857. }
  858. }
  859. if(ct == et || ct->nio == 0)
  860. return -1;
  861. if(isa->port == 0 && ct->io[0].start == 0)
  862. return -1;
  863. /* route interrupts */
  864. isa->irq = irq;
  865. wrreg(pp, Rigc, irq | Fnotreset | Fiocard);
  866. /* set power and enable device */
  867. x = vcode(ct->vpp1);
  868. wrreg(pp, Rpc, x|Fautopower|Foutena|Fcardena);
  869. /* 16-bit data path */
  870. if(ct->bit16)
  871. x = Ftiming|Fiocs16|Fwidth16;
  872. else
  873. x = Ftiming;
  874. if(ct->nio == 2 && ct->io[1].start)
  875. x |= x<<4;
  876. wrreg(pp, Rio, x);
  877. /*
  878. * enable io port map 0
  879. * the 'top' register value includes the last valid address
  880. */
  881. if(isa->port == 0)
  882. isa->port = ct->io[0].start;
  883. we = rdreg(pp, Rwe);
  884. wrreg(pp, Riobtm0lo, isa->port);
  885. wrreg(pp, Riobtm0hi, isa->port>>8);
  886. i = isa->port+ct->io[0].len-1;
  887. wrreg(pp, Riotop0lo, i);
  888. wrreg(pp, Riotop0hi, i>>8);
  889. we |= 1<<6;
  890. if(ct->nio >= 2 && ct->io[1].start){
  891. wrreg(pp, Riobtm1lo, ct->io[1].start);
  892. wrreg(pp, Riobtm1hi, ct->io[1].start>>8);
  893. i = ct->io[1].start+ct->io[1].len-1;
  894. wrreg(pp, Riotop1lo, i);
  895. wrreg(pp, Riotop1hi, i>>8);
  896. we |= 1<<7;
  897. }
  898. wrreg(pp, Rwe, we);
  899. /* only touch Rconfig if it is present */
  900. m = pcmmap(slotno, pp->cfg[0].caddr + Rconfig, 0x20, 1);
  901. p = KADDR(m->isa + pp->cfg[0].caddr - m->ca);
  902. if(pp->cfg[0].cpresent & (1<<Rconfig)){
  903. /* Reset adapter */
  904. /* set configuration and interrupt type.
  905. * if level is possible on the card, use it.
  906. */
  907. x = ct->index;
  908. if(ct->irqtype & 0x20)
  909. x |= Clevel;
  910. /* enable the device, enable address decode and
  911. * irq enable.
  912. */
  913. x |= Cfunc|Cdecode|Cirq;
  914. p[0] = x;
  915. //delay(5);
  916. microdelay(40);
  917. }
  918. if(pp->cfg[0].cpresent & (1<<Riobase0)){
  919. /* set up the iobase 0 */
  920. p[Riobase0 << 1] = isa->port;
  921. p[Riobase1 << 1] = isa->port >> 8;
  922. }
  923. if(pp->cfg[0].cpresent & (1<<Riosize))
  924. p[Riosize << 1] = ct->io[0].len;
  925. pcmunmap(slotno, m);
  926. return 0;
  927. }