devpccard.c 38 KB

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  1. /*
  2. cardbus and pcmcia (grmph) support.
  3. */
  4. #include "u.h"
  5. #include "../port/lib.h"
  6. #include "mem.h"
  7. #include "dat.h"
  8. #include "fns.h"
  9. #include "../port/error.h"
  10. #include "io.h"
  11. #define DEBUG 0
  12. #pragma varargck type "T" int
  13. #define MAP(x,o) (Rmap + (x)*0x8 + o)
  14. enum {
  15. TI_vid = 0x104c,
  16. TI_1131_did = 0xAC15,
  17. TI_1250_did = 0xAC16,
  18. TI_1450_did = 0xAC1B,
  19. TI_1251A_did = 0xAC1D,
  20. TI_1420_did = 0xAC51,
  21. Ricoh_vid = 0x1180,
  22. Ricoh_475_did = 0x0475,
  23. Ricoh_476_did = 0x0476,
  24. Ricoh_478_did = 0x0478,
  25. O2_vid = 0x1217,
  26. O2_OZ711M3_did = 0x7134,
  27. Nslots = 4, /* Maximum number of CardBus slots to use */
  28. K = 1024,
  29. M = K * K,
  30. LegacyAddr = 0x3e0,
  31. NUMEVENTS = 10,
  32. TI1131xSC = 0x80, /* system control */
  33. TI122X_SC_INTRTIE = 1 << 29,
  34. TI12xxIM = 0x8c, /* */
  35. TI1131xCC = 0x91, /* card control */
  36. TI113X_CC_RIENB = 1 << 7,
  37. TI113X_CC_ZVENABLE = 1 << 6,
  38. TI113X_CC_PCI_IRQ_ENA = 1 << 5,
  39. TI113X_CC_PCI_IREQ = 1 << 4,
  40. TI113X_CC_PCI_CSC = 1 << 3,
  41. TI113X_CC_SPKROUTEN = 1 << 1,
  42. TI113X_CC_IFG = 1 << 0,
  43. TI1131xDC = 0x92, /* device control */
  44. };
  45. typedef struct Variant Variant;
  46. struct Variant {
  47. ushort vid;
  48. ushort did;
  49. char *name;
  50. };
  51. static Variant variant[] = {
  52. { Ricoh_vid, Ricoh_475_did, "Ricoh 475 PCI/Cardbus bridge", },
  53. { Ricoh_vid, Ricoh_476_did, "Ricoh 476 PCI/Cardbus bridge", },
  54. { Ricoh_vid, Ricoh_478_did, "Ricoh 478 PCI/Cardbus bridge", },
  55. { TI_vid, TI_1131_did, "TI PCI-1131 Cardbus Controller", },
  56. { TI_vid, TI_1250_did, "TI PCI-1250 Cardbus Controller", },
  57. { TI_vid, TI_1450_did, "TI PCI-1450 Cardbus Controller", },
  58. { TI_vid, TI_1251A_did, "TI PCI-1251A Cardbus Controller", },
  59. { TI_vid, TI_1420_did, "TI PCI-1420 Cardbus Controller", },
  60. { O2_vid, O2_OZ711M3_did, "O2Micro OZ711M3 MemoryCardBus", },
  61. };
  62. /* Cardbus registers */
  63. enum {
  64. SocketEvent = 0,
  65. SE_CCD = 3 << 1,
  66. SE_POWER = 1 << 3,
  67. SocketMask = 1,
  68. SocketState = 2,
  69. SS_CCD = 3 << 1,
  70. SS_POWER = 1 << 3,
  71. SS_PC16 = 1 << 4,
  72. SS_CBC = 1 << 5,
  73. SS_NOTCARD = 1 << 7,
  74. SS_BADVCC = 1 << 9,
  75. SS_5V = 1 << 10,
  76. SS_3V = 1 << 11,
  77. SocketForce = 3,
  78. SocketControl = 4,
  79. SC_5V = 0x22,
  80. SC_3V = 0x33,
  81. };
  82. enum {
  83. PciPCR_IO = 1 << 0,
  84. PciPCR_MEM = 1 << 1,
  85. PciPCR_Master = 1 << 2,
  86. PciPMC = 0xa4,
  87. Nbars = 6,
  88. Ncmd = 10,
  89. CBIRQ = 9,
  90. PC16,
  91. PC32,
  92. };
  93. enum {
  94. Ti82365,
  95. Tpd6710,
  96. Tpd6720,
  97. Tvg46x,
  98. };
  99. /*
  100. * Intel 82365SL PCIC controller for the PCMCIA or
  101. * Cirrus Logic PD6710/PD6720 which is mostly register compatible
  102. */
  103. enum
  104. {
  105. /*
  106. * registers indices
  107. */
  108. Rid= 0x0, /* identification and revision */
  109. Ris= 0x1, /* interface status */
  110. Rpc= 0x2, /* power control */
  111. Foutena= (1<<7), /* output enable */
  112. Fautopower= (1<<5), /* automatic power switching */
  113. Fcardena= (1<<4), /* PC card enable */
  114. Rigc= 0x3, /* interrupt and general control */
  115. Fiocard= (1<<5), /* I/O card (vs memory) */
  116. Fnotreset= (1<<6), /* reset if not set */
  117. FSMIena= (1<<4), /* enable change interrupt on SMI */
  118. Rcsc= 0x4, /* card status change */
  119. Rcscic= 0x5, /* card status change interrupt config */
  120. Fchangeena= (1<<3), /* card changed */
  121. Fbwarnena= (1<<1), /* card battery warning */
  122. Fbdeadena= (1<<0), /* card battery dead */
  123. Rwe= 0x6, /* address window enable */
  124. Fmem16= (1<<5), /* use A23-A12 to decode address */
  125. Rio= 0x7, /* I/O control */
  126. Fwidth16= (1<<0), /* 16 bit data width */
  127. Fiocs16= (1<<1), /* IOCS16 determines data width */
  128. Fzerows= (1<<2), /* zero wait state */
  129. Ftiming= (1<<3), /* timing register to use */
  130. Riobtm0lo= 0x8, /* I/O address 0 start low byte */
  131. Riobtm0hi= 0x9, /* I/O address 0 start high byte */
  132. Riotop0lo= 0xa, /* I/O address 0 stop low byte */
  133. Riotop0hi= 0xb, /* I/O address 0 stop high byte */
  134. Riobtm1lo= 0xc, /* I/O address 1 start low byte */
  135. Riobtm1hi= 0xd, /* I/O address 1 start high byte */
  136. Riotop1lo= 0xe, /* I/O address 1 stop low byte */
  137. Riotop1hi= 0xf, /* I/O address 1 stop high byte */
  138. Rmap= 0x10, /* map 0 */
  139. /*
  140. * CL-PD67xx extension registers
  141. */
  142. Rmisc1= 0x16, /* misc control 1 */
  143. F5Vdetect= (1<<0),
  144. Fvcc3V= (1<<1),
  145. Fpmint= (1<<2),
  146. Fpsirq= (1<<3),
  147. Fspeaker= (1<<4),
  148. Finpack= (1<<7),
  149. Rfifo= 0x17, /* fifo control */
  150. Fflush= (1<<7), /* flush fifo */
  151. Rmisc2= 0x1E, /* misc control 2 */
  152. Flowpow= (1<<1), /* low power mode */
  153. Rchipinfo= 0x1F, /* chip information */
  154. Ratactl= 0x26, /* ATA control */
  155. /*
  156. * offsets into the system memory address maps
  157. */
  158. Mbtmlo= 0x0, /* System mem addr mapping start low byte */
  159. Mbtmhi= 0x1, /* System mem addr mapping start high byte */
  160. F16bit= (1<<7), /* 16-bit wide data path */
  161. Mtoplo= 0x2, /* System mem addr mapping stop low byte */
  162. Mtophi= 0x3, /* System mem addr mapping stop high byte */
  163. Ftimer1= (1<<6), /* timer set 1 */
  164. Mofflo= 0x4, /* Card memory offset address low byte */
  165. Moffhi= 0x5, /* Card memory offset address high byte */
  166. Fregactive= (1<<6), /* attribute memory */
  167. /*
  168. * configuration registers - they start at an offset in attribute
  169. * memory found in the CIS.
  170. */
  171. Rconfig= 0,
  172. Creset= (1<<7), /* reset device */
  173. Clevel= (1<<6), /* level sensitive interrupt line */
  174. };
  175. /*
  176. * read and crack the card information structure enough to set
  177. * important parameters like power
  178. */
  179. /* cis memory walking */
  180. typedef struct Cisdat Cisdat;
  181. struct Cisdat {
  182. uchar *cisbase;
  183. int cispos;
  184. int cisskip;
  185. int cislen;
  186. };
  187. typedef struct Pcminfo Pcminfo;
  188. struct Pcminfo {
  189. char verstr[512]; /* Version string */
  190. PCMmap mmap[4]; /* maps, last is always for the kernel */
  191. ulong conf_addr; /* Config address */
  192. uchar conf_present; /* Config register present */
  193. int nctab; /* In use configuration tables */
  194. PCMconftab ctab[8]; /* Configuration tables */
  195. PCMconftab *defctab; /* Default conftab */
  196. int port; /* Actual port usage */
  197. int irq; /* Actual IRQ usage */
  198. };
  199. typedef struct Cardbus Cardbus;
  200. struct Cardbus {
  201. Lock;
  202. Variant *variant; /* Which CardBus chipset */
  203. Pcidev *pci; /* The bridge itself */
  204. ulong *regs; /* Cardbus registers */
  205. int ltype; /* Legacy type */
  206. int lindex; /* Legacy port index address */
  207. int ldata; /* Legacy port data address */
  208. int lbase; /* Base register for this socket */
  209. int state; /* Current state of card */
  210. int type; /* Type of card */
  211. Pcminfo linfo; /* PCMCIA slot info */
  212. int special; /* card is allocated to a driver */
  213. int refs; /* Number of refs to slot */
  214. Lock refslock; /* inc/dev ref lock */
  215. };
  216. static int managerstarted;
  217. enum {
  218. Mshift= 12,
  219. Mgran= (1<<Mshift), /* granularity of maps */
  220. Mmask= ~(Mgran-1), /* mask for address bits important to the chip */
  221. };
  222. static Cardbus cbslots[Nslots];
  223. static int nslots;
  224. static ulong exponent[8] = {
  225. 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
  226. };
  227. static ulong vmant[16] = {
  228. 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80, 90,
  229. };
  230. static ulong mantissa[16] = {
  231. 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80,
  232. };
  233. static char Enocard[] = "No card in slot";
  234. enum
  235. {
  236. CMdown,
  237. CMpower,
  238. };
  239. static Cmdtab pccardctlmsg[] =
  240. {
  241. CMdown, "down", 2,
  242. CMpower, "power", 1,
  243. };
  244. static int powerup(Cardbus *);
  245. static void configure(Cardbus *);
  246. static void powerdown(Cardbus *cb);
  247. static void unconfigure(Cardbus *cb);
  248. static void i82365probe(Cardbus *cb, int lindex, int ldata);
  249. static void i82365configure(Cardbus *cb);
  250. static PCMmap *isamap(Cardbus *cb, ulong offset, int len, int attr);
  251. static void isaunmap(PCMmap* m);
  252. static uchar rdreg(Cardbus *cb, int index);
  253. static void wrreg(Cardbus *cb, int index, uchar val);
  254. static int readc(Cisdat *cis, uchar *x);
  255. static void tvers1(Cardbus *cb, Cisdat *cis, int );
  256. static void tcfig(Cardbus *cb, Cisdat *cis, int );
  257. static void tentry(Cardbus *cb, Cisdat *cis, int );
  258. static int vcode(int volt);
  259. static int pccard_pcmspecial(char *idstr, ISAConf *isa);
  260. static void pccard_pcmspecialclose(int slotno);
  261. enum {
  262. CardDetected,
  263. CardPowered,
  264. CardEjected,
  265. CardConfigured,
  266. };
  267. static char *messages[] = {
  268. [CardDetected] "CardDetected",
  269. [CardPowered] "CardPowered",
  270. [CardEjected] "CardEjected",
  271. [CardConfigured] "CardConfigured",
  272. };
  273. enum {
  274. SlotEmpty,
  275. SlotFull,
  276. SlotPowered,
  277. SlotConfigured,
  278. };
  279. static char *states[] = {
  280. [SlotEmpty] "SlotEmpty",
  281. [SlotFull] "SlotFull",
  282. [SlotPowered] "SlotPowered",
  283. [SlotConfigured] "SlotConfigured",
  284. };
  285. static void
  286. engine(Cardbus *cb, int message)
  287. {
  288. if(DEBUG)
  289. print("engine(%ld): %s(%s)\n", cb - cbslots,
  290. states[cb->state], messages[message]);
  291. switch (cb->state) {
  292. case SlotEmpty:
  293. switch (message) {
  294. case CardDetected:
  295. cb->state = SlotFull;
  296. powerup(cb);
  297. break;
  298. case CardEjected:
  299. break;
  300. default:
  301. if(DEBUG)
  302. print("#Y%ld: Invalid message %s in SlotEmpty state\n",
  303. cb - cbslots, messages[message]);
  304. break;
  305. }
  306. break;
  307. case SlotFull:
  308. switch (message) {
  309. case CardPowered:
  310. cb->state = SlotPowered;
  311. configure(cb);
  312. break;
  313. case CardEjected:
  314. cb->state = SlotEmpty;
  315. powerdown(cb);
  316. break;
  317. default:
  318. if(DEBUG)
  319. print("#Y%ld: Invalid message %s in SlotFull state\n",
  320. cb - cbslots, messages[message]);
  321. break;
  322. }
  323. break;
  324. case SlotPowered:
  325. switch (message) {
  326. case CardConfigured:
  327. cb->state = SlotConfigured;
  328. break;
  329. case CardEjected:
  330. cb->state = SlotEmpty;
  331. unconfigure(cb);
  332. powerdown(cb);
  333. break;
  334. default:
  335. print("#Y%ld: Invalid message %s in SlotPowered state\n",
  336. cb - cbslots, messages[message]);
  337. break;
  338. }
  339. break;
  340. case SlotConfigured:
  341. switch (message) {
  342. case CardEjected:
  343. cb->state = SlotEmpty;
  344. unconfigure(cb);
  345. powerdown(cb);
  346. break;
  347. default:
  348. if(DEBUG)
  349. print("#Y%ld: Invalid message %s in SlotConfigured state\n",
  350. cb - cbslots, messages[message]);
  351. break;
  352. }
  353. break;
  354. }
  355. }
  356. static void
  357. qengine(Cardbus *cb, int message)
  358. {
  359. lock(cb);
  360. engine(cb, message);
  361. unlock(cb);
  362. }
  363. typedef struct Events Events;
  364. struct Events {
  365. Cardbus *cb;
  366. int message;
  367. };
  368. static Lock levents;
  369. static Events events[NUMEVENTS];
  370. static Rendez revents;
  371. static int nevents;
  372. static void
  373. iengine(Cardbus *cb, int message)
  374. {
  375. if (nevents >= NUMEVENTS) {
  376. print("#Y: Too many events queued, discarding request\n");
  377. return;
  378. }
  379. ilock(&levents);
  380. events[nevents].cb = cb;
  381. events[nevents].message = message;
  382. nevents++;
  383. iunlock(&levents);
  384. wakeup(&revents);
  385. }
  386. static int
  387. eventoccured(void)
  388. {
  389. return nevents > 0;
  390. }
  391. static void
  392. processevents(void *)
  393. {
  394. while (1) {
  395. int message;
  396. Cardbus *cb;
  397. sleep(&revents, (int (*)(void *))eventoccured, nil);
  398. cb = nil;
  399. message = 0;
  400. ilock(&levents);
  401. if (nevents > 0) {
  402. cb = events[0].cb;
  403. message = events[0].message;
  404. nevents--;
  405. if (nevents > 0)
  406. memmove(events, &events[1], nevents * sizeof(Events));
  407. }
  408. iunlock(&levents);
  409. if (cb)
  410. qengine(cb, message);
  411. }
  412. }
  413. static void
  414. cbinterrupt(Ureg *, void *)
  415. {
  416. int i;
  417. for (i = 0; i != nslots; i++) {
  418. Cardbus *cb = &cbslots[i];
  419. ulong event, state;
  420. event = cb->regs[SocketEvent];
  421. if(!(event & (SE_POWER|SE_CCD)))
  422. continue;
  423. state = cb->regs[SocketState];
  424. rdreg(cb, Rcsc); /* Ack the interrupt */
  425. if(DEBUG)
  426. print("#Y%ld: interrupt: event %.8lX, state %.8lX, (%s)\n",
  427. cb - cbslots, event, state, states[cb->state]);
  428. if (event & SE_CCD) {
  429. cb->regs[SocketEvent] |= SE_CCD; /* Ack interrupt */
  430. if (state & SE_CCD) {
  431. if (cb->state != SlotEmpty) {
  432. print("#Y: take cardejected interrupt\n");
  433. iengine(cb, CardEjected);
  434. }
  435. }
  436. else
  437. iengine(cb, CardDetected);
  438. }
  439. if (event & SE_POWER) {
  440. cb->regs[SocketEvent] |= SE_POWER; /* Ack interrupt */
  441. iengine(cb, CardPowered);
  442. }
  443. }
  444. }
  445. void
  446. devpccardlink(void)
  447. {
  448. static int initialized;
  449. Pcidev *pci;
  450. int i;
  451. uchar intl;
  452. char *p;
  453. void *baddrva;
  454. if (initialized)
  455. return;
  456. initialized = 1;
  457. if((p=getconf("pccard0")) && strncmp(p, "disabled", 8)==0)
  458. return;
  459. if(_pcmspecial)
  460. return;
  461. /* Allocate legacy space */
  462. if (ioalloc(LegacyAddr, 2, 0, "i82365.0") < 0)
  463. print("#Y: WARNING: Cannot allocate legacy ports\n");
  464. /* Find all CardBus controllers */
  465. pci = nil;
  466. intl = 0xff;
  467. while ((pci = pcimatch(pci, 0, 0)) != nil) {
  468. ulong baddr;
  469. Cardbus *cb;
  470. int slot;
  471. uchar pin;
  472. if(pci->ccrb != 6 || pci->ccru != 7)
  473. continue;
  474. for (i = 0; i != nelem(variant); i++)
  475. if (pci->vid == variant[i].vid && pci->did == variant[i].did)
  476. break;
  477. if (i == nelem(variant))
  478. continue;
  479. /* initialize this slot */
  480. slot = nslots++;
  481. cb = &cbslots[slot];
  482. cb->pci = pci;
  483. cb->variant = &variant[i];
  484. if (pci->vid != TI_vid) {
  485. /*
  486. * Gross hack, needs a fix. Inherit the mappings from
  487. * 9load for the TIs (pb)
  488. */
  489. pcicfgw32(pci, PciCBMBR0, 0xffffffff);
  490. pcicfgw32(pci, PciCBMLR0, 0);
  491. pcicfgw32(pci, PciCBMBR1, 0xffffffff);
  492. pcicfgw32(pci, PciCBMLR1, 0);
  493. pcicfgw32(pci, PciCBIBR0, 0xffffffff);
  494. pcicfgw32(pci, PciCBILR0, 0);
  495. pcicfgw32(pci, PciCBIBR1, 0xffffffff);
  496. pcicfgw32(pci, PciCBILR1, 0);
  497. }
  498. /* Set up PCI bus numbers if needed. */
  499. if (pcicfgr8(pci, PciSBN) == 0) {
  500. static int busbase = 0x20;
  501. pcicfgw8(pci, PciSBN, busbase);
  502. pcicfgw8(pci, PciUBN, busbase + 2);
  503. busbase += 3;
  504. }
  505. /* Patch up intl if needed. */
  506. if ((pin = pcicfgr8(pci, PciINTP)) != 0 &&
  507. (pci->intl == 0xff || pci->intl == 0)) {
  508. pci->intl = pciipin(nil, pin);
  509. pcicfgw8(pci, PciINTL, pci->intl);
  510. if (pci->intl == 0xff || pci->intl == 0)
  511. print("#Y%ld: No interrupt?\n", cb - cbslots);
  512. }
  513. /* Don't you love standards! */
  514. if (pci->vid == TI_vid) {
  515. if (pci->did <= TI_1131_did) {
  516. uchar cc;
  517. cc = pcicfgr8(pci, TI1131xCC);
  518. cc &= ~(TI113X_CC_PCI_IRQ_ENA |
  519. TI113X_CC_PCI_IREQ |
  520. TI113X_CC_PCI_CSC |
  521. TI113X_CC_ZVENABLE);
  522. cc |= TI113X_CC_PCI_IRQ_ENA |
  523. TI113X_CC_PCI_IREQ |
  524. TI113X_CC_SPKROUTEN;
  525. pcicfgw8(pci, TI1131xCC, cc);
  526. /* PCI interrupts only */
  527. pcicfgw8(pci, TI1131xDC,
  528. pcicfgr8(pci, TI1131xDC) & ~6);
  529. /* CSC ints to PCI bus. */
  530. wrreg(cb, Rigc, rdreg(cb, Rigc) | 0x10);
  531. }
  532. else if (pci->did == TI_1250_did) {
  533. print("No support yet for the TI_1250_did, prod pb\n");
  534. }
  535. else if (pci->did == TI_1420_did) {
  536. /* Disable Vcc protection */
  537. pcicfgw32(cb->pci, 0x80,
  538. pcicfgr32(cb->pci, 0x80) | (1 << 21));
  539. }
  540. pcicfgw16(cb->pci, PciPMC, pcicfgr16(cb->pci, PciPMC) & ~3);
  541. }
  542. if (pci->vid == O2_vid) {
  543. if(DEBUG)
  544. print("writing O2 config\n");
  545. pcicfgw8(cb->pci, 0x94, 0xCA);
  546. pcicfgw8(cb->pci, 0xD4, 0xCA);
  547. }
  548. if (intl != 0xff && intl != pci->intl)
  549. intrenable(pci->intl, cbinterrupt, cb, pci->tbdf, "cardbus");
  550. intl = pci->intl;
  551. if ((baddr = pcicfgr32(cb->pci, PciBAR0)) == 0) {
  552. int size = (pci->did == Ricoh_478_did)? 0x10000: 0x1000;
  553. baddr = upaalloc(size, size);
  554. baddrva = vmap(baddr, size);
  555. pcicfgw32(cb->pci, PciBAR0, baddr);
  556. cb->regs = (ulong *)baddrva;
  557. }
  558. else
  559. cb->regs = (ulong *)vmap(baddr, 4096);
  560. cb->state = SlotEmpty;
  561. /* Don't really know what to do with this... */
  562. i82365probe(cb, LegacyAddr, LegacyAddr + 1);
  563. print("#Y%ld: %s, %.8ulX intl %d\n", cb - cbslots,
  564. variant[i].name, baddr, pci->intl);
  565. }
  566. if (nslots == 0){
  567. iofree(LegacyAddr);
  568. return;
  569. }
  570. _pcmspecial = pccard_pcmspecial;
  571. _pcmspecialclose = pccard_pcmspecialclose;
  572. for (i = 0; i != nslots; i++) {
  573. Cardbus *cb = &cbslots[i];
  574. if ((cb->regs[SocketState] & SE_CCD) == 0)
  575. engine(cb, CardDetected);
  576. }
  577. delay(500); /* Allow time for power up */
  578. for (i = 0; i != nslots; i++) {
  579. Cardbus *cb = &cbslots[i];
  580. if (cb->regs[SocketState] & SE_POWER)
  581. engine(cb, CardPowered);
  582. /* Ack and enable interrupts on all events */
  583. // cb->regs[SocketEvent] = cb->regs[SocketEvent];
  584. cb->regs[SocketMask] |= 0xF;
  585. wrreg(cb, Rcscic, 0xC);
  586. }
  587. }
  588. static int
  589. powerup(Cardbus *cb)
  590. {
  591. ulong state;
  592. ushort bcr;
  593. state = cb->regs[SocketState];
  594. if (state & SS_PC16) {
  595. if(DEBUG)
  596. print("#Y%ld: Probed a PC16 card, powering up card\n",
  597. cb - cbslots);
  598. cb->type = PC16;
  599. memset(&cb->linfo, 0, sizeof(Pcminfo));
  600. /* power up and unreset, wait's are empirical (???) */
  601. wrreg(cb, Rpc, Fautopower|Foutena|Fcardena);
  602. delay(300);
  603. wrreg(cb, Rigc, 0);
  604. delay(100);
  605. wrreg(cb, Rigc, Fnotreset);
  606. delay(500);
  607. // return 1;
  608. }
  609. if (state & SS_CCD)
  610. return 0;
  611. if (state & SS_NOTCARD) {
  612. print("#Y%ld: No card inserted\n", cb - cbslots);
  613. return 0;
  614. }
  615. if ((state & SS_3V) == 0 && (state & SS_5V) == 0) {
  616. print("#Y%ld: Unsupported voltage, powering down card!\n",
  617. cb - cbslots);
  618. cb->regs[SocketControl] = 0;
  619. return 0;
  620. }
  621. if(DEBUG)
  622. print("#Y%ld: card %spowered at %d volt\n", cb - cbslots,
  623. (state & SS_POWER)? "": "not ",
  624. (state & SS_3V)? 3: (state & SS_5V)? 5: -1);
  625. /* Power up the card
  626. * and make sure the secondary bus is not in reset.
  627. */
  628. cb->regs[SocketControl] = (state & SS_5V)? SC_5V: SC_3V;
  629. delay(50);
  630. bcr = pcicfgr16(cb->pci, PciBCR);
  631. bcr &= ~0x40;
  632. pcicfgw16(cb->pci, PciBCR, bcr);
  633. delay(100);
  634. if (state & SS_PC16)
  635. cb->type = PC16;
  636. else
  637. cb->type = PC32;
  638. return 1;
  639. }
  640. static void
  641. powerdown(Cardbus *cb)
  642. {
  643. ushort bcr;
  644. if (cb->type == PC16) {
  645. wrreg(cb, Rpc, 0); /* turn off card power */
  646. wrreg(cb, Rwe, 0); /* no windows */
  647. cb->type = -1;
  648. return;
  649. }
  650. bcr = pcicfgr16(cb->pci, PciBCR);
  651. bcr |= 0x40;
  652. pcicfgw16(cb->pci, PciBCR, bcr);
  653. cb->regs[SocketControl] = 0;
  654. cb->type = -1;
  655. }
  656. static void
  657. configure(Cardbus *cb)
  658. {
  659. int i, r;
  660. ulong size, bar;
  661. Pcidev *pci;
  662. ulong membase, iobase, memlen, iolen, rombase, romlen;
  663. if(DEBUG)
  664. print("configuring slot %ld (%s)\n", cb - cbslots, states[cb->state]);
  665. if (cb->state == SlotConfigured)
  666. return;
  667. engine(cb, CardConfigured);
  668. delay(50); /* Emperically established */
  669. if (cb->type == PC16) {
  670. i82365configure(cb);
  671. return;
  672. }
  673. /* Scan the CardBus for new PCI devices */
  674. pciscan(pcicfgr8(cb->pci, PciSBN), &cb->pci->bridge);
  675. /*
  676. * size the devices on the bus, reserve a minimum for devices arriving later,
  677. * allow for ROM space, allocate space, and set the cardbus mapping registers
  678. */
  679. pcibussize(cb->pci->bridge, &memlen, &iolen); /* TO DO: need initial alignments */
  680. romlen = 0;
  681. for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
  682. size = pcibarsize(pci, PciEBAR0);
  683. if(size > 0){
  684. pci->rom.bar = -1;
  685. pci->rom.size = size;
  686. romlen += size;
  687. }
  688. }
  689. if(iolen < 512)
  690. iolen = 512;
  691. iobase = ioreserve(~0, iolen, 0, "cardbus");
  692. pcicfgw32(cb->pci, PciCBIBR0, iobase);
  693. pcicfgw32(cb->pci, PciCBILR0, iobase + iolen-1);
  694. pcicfgw32(cb->pci, PciCBIBR1, 0);
  695. pcicfgw32(cb->pci, PciCBILR1, 0);
  696. rombase = memlen;
  697. memlen += romlen;
  698. if(memlen < 1*1024*1024)
  699. memlen = 1*1024*1024;
  700. membase = upaalloc(memlen, 4*1024*1024); /* TO DO: better alignment */
  701. pcicfgw32(cb->pci, PciCBMBR0, membase);
  702. pcicfgw32(cb->pci, PciCBMLR0, membase + memlen-1);
  703. pcicfgw32(cb->pci, PciCBMBR1, 0);
  704. pcicfgw32(cb->pci, PciCBMLR1, 0);
  705. // pcibussize(cb->pci->bridge, &membase, &iobase); /* now assign them */
  706. rombase += membase;
  707. for(pci = cb->pci->bridge; pci != nil; pci = pci->list){
  708. r = pcicfgr16(pci, PciPCR);
  709. r &= ~(PciPCR_IO|PciPCR_MEM);
  710. pcicfgw16(pci, PciPCR, r);
  711. /*
  712. * Treat the found device as an ordinary PCI card.
  713. * It seems that the CIS is not always present in
  714. * CardBus cards.
  715. * XXX, need to support multifunction cards
  716. */
  717. for(i = 0; i < Nbars; i++) {
  718. if(pci->mem[i].size == 0)
  719. continue;
  720. bar = pci->mem[i].bar;
  721. if(bar & 1)
  722. bar += iobase;
  723. else
  724. bar += membase;
  725. pci->mem[i].bar = bar;
  726. pcicfgw32(pci, PciBAR0 + 4*i, bar);
  727. if((bar & 1) == 0){
  728. print("%T mem[%d] %8.8lux %d\n", pci->tbdf, i, bar, pci->mem[i].size);
  729. if(bar & 0x80){ /* TO DO: enable prefetch */
  730. ;
  731. }
  732. }
  733. }
  734. if((size = pcibarsize(pci, PciEBAR0)) > 0) { /* TO DO: can this be done by pci.c? */
  735. pci->rom.bar = rombase;
  736. pci->rom.size = size;
  737. rombase += size;
  738. pcicfgw32(pci, PciEBAR0, pci->rom.bar);
  739. }
  740. /* Set the basic PCI registers for the device */
  741. pci->pcr = pcicfgr16(pci, PciPCR);
  742. pci->pcr |= PciPCR_IO|PciPCR_MEM|PciPCR_Master;
  743. pci->cls = 8;
  744. pci->ltr = 64;
  745. pcicfgw16(pci, PciPCR, pci->pcr);
  746. pcicfgw8(pci, PciCLS, pci->cls);
  747. pcicfgw8(pci, PciLTR, pci->ltr);
  748. if (pcicfgr8(pci, PciINTP)) {
  749. pci->intl = pcicfgr8(cb->pci, PciINTL);
  750. pcicfgw8(pci, PciINTL, pci->intl);
  751. /* Route interrupts to INTA#/B# */
  752. pcicfgw16(cb->pci, PciBCR,
  753. pcicfgr16(cb->pci, PciBCR) & ~(1 << 7));
  754. }
  755. }
  756. }
  757. static void
  758. unconfigure(Cardbus *cb)
  759. {
  760. Pcidev *pci;
  761. int i, ioindex, memindex, r;
  762. if (cb->type == PC16) {
  763. print("#Y%d: Don't know how to unconfigure a PC16 card\n",
  764. (int)(cb - cbslots));
  765. memset(&cb->linfo, 0, sizeof(Pcminfo));
  766. return;
  767. }
  768. pci = cb->pci->bridge;
  769. if (pci == nil)
  770. return; /* Not configured */
  771. cb->pci->bridge = nil;
  772. memindex = ioindex = 0;
  773. while (pci) {
  774. Pcidev *_pci;
  775. for (i = 0; i != Nbars; i++) {
  776. if (pci->mem[i].size == 0)
  777. continue;
  778. if (pci->mem[i].bar & 1) {
  779. iofree(pci->mem[i].bar & ~1);
  780. pcicfgw16(cb->pci, PciCBIBR0 + ioindex * 8,
  781. (ushort)-1);
  782. pcicfgw16(cb->pci, PciCBILR0 + ioindex * 8, 0);
  783. ioindex++;
  784. continue;
  785. }
  786. upafree(pci->mem[i].bar & ~0xF, pci->mem[i].size);
  787. pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
  788. pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
  789. r = pcicfgr16(cb->pci, PciBCR);
  790. r &= ~(1 << (8 + memindex));
  791. pcicfgw16(cb->pci, PciBCR, r);
  792. memindex++;
  793. }
  794. if (pci->rom.bar && memindex < 2) {
  795. upafree(pci->rom.bar & ~0xF, pci->rom.size);
  796. pcicfgw32(cb->pci, PciCBMBR0 + memindex * 8, (ulong)-1);
  797. pcicfgw32(cb->pci, PciCBMLR0 + memindex * 8, 0);
  798. memindex++;
  799. }
  800. _pci = pci->list;
  801. free(_pci);
  802. pci = _pci;
  803. }
  804. }
  805. static void
  806. i82365configure(Cardbus *cb)
  807. {
  808. int this;
  809. Cisdat cis;
  810. PCMmap *m;
  811. uchar type, link;
  812. /*
  813. * Read all tuples in attribute space.
  814. */
  815. m = isamap(cb, 0, 0, 1);
  816. if(m == 0)
  817. return;
  818. cis.cisbase = KADDR(m->isa);
  819. cis.cispos = 0;
  820. cis.cisskip = 2;
  821. cis.cislen = m->len;
  822. /* loop through all the tuples */
  823. for(;;){
  824. this = cis.cispos;
  825. if(readc(&cis, &type) != 1)
  826. break;
  827. if(type == 0xFF)
  828. break;
  829. if(readc(&cis, &link) != 1)
  830. break;
  831. switch(type){
  832. default:
  833. break;
  834. case 0x15:
  835. tvers1(cb, &cis, type);
  836. break;
  837. case 0x1A:
  838. tcfig(cb, &cis, type);
  839. break;
  840. case 0x1B:
  841. tentry(cb, &cis, type);
  842. break;
  843. }
  844. if(link == 0xFF)
  845. break;
  846. cis.cispos = this + (2+link);
  847. }
  848. isaunmap(m);
  849. }
  850. /*
  851. * look for a card whose version contains 'idstr'
  852. */
  853. static int
  854. pccard_pcmspecial(char *idstr, ISAConf *isa)
  855. {
  856. int i, irq;
  857. PCMconftab *ct, *et;
  858. Pcminfo *pi;
  859. Cardbus *cb;
  860. uchar x, we, *p;
  861. cb = nil;
  862. for (i = 0; i != nslots; i++) {
  863. cb = &cbslots[i];
  864. lock(cb);
  865. if (cb->state == SlotConfigured &&
  866. cb->type == PC16 &&
  867. !cb->special &&
  868. strstr(cb->linfo.verstr, idstr))
  869. break;
  870. unlock(cb);
  871. }
  872. if (i == nslots) {
  873. if(0 && DEBUG)
  874. print("#Y: %s not found\n", idstr);
  875. return -1;
  876. }
  877. pi = &cb->linfo;
  878. /*
  879. * configure the PCMslot for IO. We assume very heavily that we can read
  880. * configuration info from the CIS. If not, we won't set up correctly.
  881. */
  882. irq = isa->irq;
  883. if(irq == 2)
  884. irq = 9;
  885. et = &pi->ctab[pi->nctab];
  886. ct = nil;
  887. for(i = 0; i < isa->nopt; i++){
  888. int index;
  889. char *cp;
  890. if(strncmp(isa->opt[i], "index=", 6))
  891. continue;
  892. index = strtol(&isa->opt[i][6], &cp, 0);
  893. if(cp == &isa->opt[i][6] || index >= pi->nctab) {
  894. unlock(cb);
  895. print("#Y%d: Cannot find index %d in conf table\n",
  896. (int)(cb - cbslots), index);
  897. return -1;
  898. }
  899. ct = &pi->ctab[index];
  900. }
  901. if(ct == nil){
  902. PCMconftab *t;
  903. /* assume default is right */
  904. if(pi->defctab)
  905. ct = pi->defctab;
  906. else
  907. ct = pi->ctab;
  908. /* try for best match */
  909. if(ct->nio == 0
  910. || ct->io[0].start != isa->port || ((1<<irq) & ct->irqs) == 0){
  911. for(t = pi->ctab; t < et; t++)
  912. if(t->nio
  913. && t->io[0].start == isa->port
  914. && ((1<<irq) & t->irqs)){
  915. ct = t;
  916. break;
  917. }
  918. }
  919. if(ct->nio == 0 || ((1<<irq) & ct->irqs) == 0){
  920. for(t = pi->ctab; t < et; t++)
  921. if(t->nio && ((1<<irq) & t->irqs)){
  922. ct = t;
  923. break;
  924. }
  925. }
  926. if(ct->nio == 0){
  927. for(t = pi->ctab; t < et; t++)
  928. if(t->nio){
  929. ct = t;
  930. break;
  931. }
  932. }
  933. }
  934. if(ct == et || ct->nio == 0) {
  935. unlock(cb);
  936. print("#Y%d: No configuration?\n", (int)(cb - cbslots));
  937. return -1;
  938. }
  939. if(isa->port == 0 && ct->io[0].start == 0) {
  940. unlock(cb);
  941. print("#Y%d: No part or start address\n", (int)(cb - cbslots));
  942. return -1;
  943. }
  944. cb->special = 1; /* taken */
  945. /* route interrupts */
  946. isa->irq = irq;
  947. wrreg(cb, Rigc, irq | Fnotreset | Fiocard);
  948. /* set power and enable device */
  949. x = vcode(ct->vpp1);
  950. wrreg(cb, Rpc, x|Fautopower|Foutena|Fcardena);
  951. /* 16-bit data path */
  952. if(ct->bit16)
  953. x = Ftiming|Fiocs16|Fwidth16;
  954. else
  955. x = Ftiming;
  956. if(ct->nio == 2 && ct->io[1].start)
  957. x |= x<<4;
  958. wrreg(cb, Rio, x);
  959. /*
  960. * enable io port map 0
  961. * the 'top' register value includes the last valid address
  962. */
  963. if(isa->port == 0)
  964. isa->port = ct->io[0].start;
  965. we = rdreg(cb, Rwe);
  966. wrreg(cb, Riobtm0lo, isa->port);
  967. wrreg(cb, Riobtm0hi, isa->port>>8);
  968. i = isa->port+ct->io[0].len-1;
  969. wrreg(cb, Riotop0lo, i);
  970. wrreg(cb, Riotop0hi, i>>8);
  971. we |= 1<<6;
  972. if(ct->nio == 2 && ct->io[1].start){
  973. wrreg(cb, Riobtm1lo, ct->io[1].start);
  974. wrreg(cb, Riobtm1hi, ct->io[1].start>>8);
  975. i = ct->io[1].start+ct->io[1].len-1;
  976. wrreg(cb, Riotop1lo, i);
  977. wrreg(cb, Riotop1hi, i>>8);
  978. we |= 1<<7;
  979. }
  980. wrreg(cb, Rwe, we);
  981. /* only touch Rconfig if it is present */
  982. if(pi->conf_present & (1<<Rconfig)){
  983. PCMmap *m;
  984. /* Reset adapter */
  985. m = isamap(cb, pi->conf_addr + Rconfig, 1, 1);
  986. p = KADDR(m->isa + pi->conf_addr + Rconfig - m->ca);
  987. /* set configuration and interrupt type */
  988. x = ct->index;
  989. if(ct->irqtype & 0x20)
  990. x |= Clevel;
  991. *p = x;
  992. delay(5);
  993. isaunmap(m);
  994. }
  995. pi->port = isa->port;
  996. pi->irq = isa->irq;
  997. unlock(cb);
  998. print("#Y%ld: %s irq %d, port %lX\n", cb - cbslots, pi->verstr, isa->irq, isa->port);
  999. return (int)(cb - cbslots);
  1000. }
  1001. static void
  1002. pccard_pcmspecialclose(int slotno)
  1003. {
  1004. Cardbus *cb = &cbslots[slotno];
  1005. wrreg(cb, Rwe, 0); /* no windows */
  1006. cb->special = 0;
  1007. }
  1008. static Chan*
  1009. pccardattach(char *spec)
  1010. {
  1011. if (!managerstarted) {
  1012. managerstarted = 1;
  1013. kproc("cardbus", processevents, nil);
  1014. }
  1015. return devattach('Y', spec);
  1016. }
  1017. enum
  1018. {
  1019. Qdir,
  1020. Qctl,
  1021. Nents = 1,
  1022. };
  1023. #define SLOTNO(c) ((ulong)((c->qid.path>>8)&0xff))
  1024. #define TYPE(c) ((ulong)(c->qid.path&0xff))
  1025. #define QID(s,t) (((s)<<8)|(t))
  1026. static int
  1027. pccardgen(Chan *c, char*, Dirtab *, int , int i, Dir *dp)
  1028. {
  1029. int slotno;
  1030. Qid qid;
  1031. long len;
  1032. int entry;
  1033. if(i == DEVDOTDOT){
  1034. mkqid(&qid, Qdir, 0, QTDIR);
  1035. devdir(c, qid, "#Y", 0, eve, 0555, dp);
  1036. return 1;
  1037. }
  1038. len = 0;
  1039. if(i >= Nents * nslots) return -1;
  1040. slotno = i / Nents;
  1041. entry = i % Nents;
  1042. if (entry == 0) {
  1043. qid.path = QID(slotno, Qctl);
  1044. snprint(up->genbuf, sizeof up->genbuf, "cb%dctl", slotno);
  1045. }
  1046. else {
  1047. /* Entries for memory regions. I'll implement them when
  1048. needed. (pb) */
  1049. }
  1050. qid.vers = 0;
  1051. qid.type = QTFILE;
  1052. devdir(c, qid, up->genbuf, len, eve, 0660, dp);
  1053. return 1;
  1054. }
  1055. static Walkqid*
  1056. pccardwalk(Chan *c, Chan *nc, char **name, int nname)
  1057. {
  1058. return devwalk(c, nc, name, nname, 0, 0, pccardgen);
  1059. }
  1060. static int
  1061. pccardstat(Chan *c, uchar *db, int n)
  1062. {
  1063. return devstat(c, db, n, 0, 0, pccardgen);
  1064. }
  1065. static void
  1066. increfp(Cardbus *cb)
  1067. {
  1068. lock(&cb->refslock);
  1069. cb->refs++;
  1070. unlock(&cb->refslock);
  1071. }
  1072. static void
  1073. decrefp(Cardbus *cb)
  1074. {
  1075. lock(&cb->refslock);
  1076. cb->refs--;
  1077. unlock(&cb->refslock);
  1078. }
  1079. static Chan*
  1080. pccardopen(Chan *c, int omode)
  1081. {
  1082. if (c->qid.type & QTDIR){
  1083. if(omode != OREAD)
  1084. error(Eperm);
  1085. } else
  1086. increfp(&cbslots[SLOTNO(c)]);
  1087. c->mode = openmode(omode);
  1088. c->flag |= COPEN;
  1089. c->offset = 0;
  1090. return c;
  1091. }
  1092. static void
  1093. pccardclose(Chan *c)
  1094. {
  1095. if(c->flag & COPEN)
  1096. if((c->qid.type & QTDIR) == 0)
  1097. decrefp(&cbslots[SLOTNO(c)]);
  1098. }
  1099. static long
  1100. pccardread(Chan *c, void *a, long n, vlong offset)
  1101. {
  1102. Cardbus *cb;
  1103. char *buf, *p, *e;
  1104. int i;
  1105. switch(TYPE(c)){
  1106. case Qdir:
  1107. return devdirread(c, a, n, 0, 0, pccardgen);
  1108. case Qctl:
  1109. buf = p = malloc(READSTR);
  1110. buf[0] = 0;
  1111. e = p + READSTR;
  1112. cb = &cbslots[SLOTNO(c)];
  1113. lock(cb);
  1114. p = seprint(p, e, "slot %ld: %s; ", cb - cbslots, states[cb->state]);
  1115. switch (cb->type) {
  1116. case -1:
  1117. seprint(p, e, "\n");
  1118. break;
  1119. case PC32:
  1120. if (cb->pci->bridge) {
  1121. Pcidev *pci = cb->pci->bridge;
  1122. int i;
  1123. while (pci) {
  1124. p = seprint(p, e, "%.4uX %.4uX; irq %d\n",
  1125. pci->vid, pci->did, pci->intl);
  1126. for (i = 0; i != Nbars; i++)
  1127. if (pci->mem[i].size)
  1128. p = seprint(p, e,
  1129. "\tmem[%d] %.8ulX (%.8uX)\n",
  1130. i, pci->mem[i].bar,
  1131. pci->mem[i].size);
  1132. if (pci->rom.size)
  1133. p = seprint(p, e, "\tROM %.8ulX (%.8uX)\n",
  1134. pci->rom.bar, pci->rom.size);
  1135. pci = pci->list;
  1136. }
  1137. }
  1138. break;
  1139. case PC16:
  1140. if (cb->state == SlotConfigured) {
  1141. Pcminfo *pi = &cb->linfo;
  1142. p = seprint(p, e, "%s port %X; irq %d;\n",
  1143. pi->verstr, pi->port,
  1144. pi->irq);
  1145. for (i = 0; i != pi->nctab; i++) {
  1146. PCMconftab *ct;
  1147. int j;
  1148. ct = &pi->ctab[i];
  1149. p = seprint(p, e,
  1150. "\tconfiguration[%d] irqs %.4uX; vpp %d, %d; %s\n",
  1151. i, ct->irqs, ct->vpp1, ct->vpp2,
  1152. (ct == pi->defctab)? "(default);": "");
  1153. for (j = 0; j != ct->nio; j++)
  1154. if (ct->io[j].len > 0)
  1155. p = seprint(p, e, "\t\tio[%d] %.8ulX %uld\n",
  1156. j, ct->io[j].start, ct->io[j].len);
  1157. }
  1158. }
  1159. break;
  1160. }
  1161. unlock(cb);
  1162. n = readstr(offset, a, n, buf);
  1163. free(buf);
  1164. return n;
  1165. }
  1166. return 0;
  1167. }
  1168. static long
  1169. pccardwrite(Chan *c, void *v, long n, vlong)
  1170. {
  1171. Rune r;
  1172. ulong n0;
  1173. char *device;
  1174. Cmdbuf *cbf;
  1175. Cmdtab *ct;
  1176. Cardbus *cb;
  1177. n0 = n;
  1178. switch(TYPE(c)){
  1179. case Qctl:
  1180. cb = &cbslots[SLOTNO(c)];
  1181. cbf = parsecmd(v, n);
  1182. if(waserror()){
  1183. free(cbf);
  1184. nexterror();
  1185. }
  1186. ct = lookupcmd(cbf, pccardctlmsg, nelem(pccardctlmsg));
  1187. switch(ct->index){
  1188. case CMdown:
  1189. device = cbf->f[1];
  1190. device += chartorune(&r, device);
  1191. if ((n = devno(r, 1)) >= 0 && devtab[n]->config)
  1192. devtab[n]->config(0, device, nil);
  1193. qengine(cb, CardEjected);
  1194. break;
  1195. case CMpower:
  1196. if ((cb->regs[SocketState] & SS_CCD) == 0)
  1197. qengine(cb, CardDetected);
  1198. break;
  1199. }
  1200. poperror();
  1201. free(cbf);
  1202. break;
  1203. }
  1204. return n0 - n;
  1205. }
  1206. Dev pccarddevtab = {
  1207. 'Y',
  1208. "cardbus",
  1209. devreset,
  1210. devinit,
  1211. devshutdown,
  1212. pccardattach,
  1213. pccardwalk,
  1214. pccardstat,
  1215. pccardopen,
  1216. devcreate,
  1217. pccardclose,
  1218. pccardread,
  1219. devbread,
  1220. pccardwrite,
  1221. devbwrite,
  1222. devremove,
  1223. devwstat,
  1224. };
  1225. static PCMmap *
  1226. isamap(Cardbus *cb, ulong offset, int len, int attr)
  1227. {
  1228. uchar we, bit;
  1229. PCMmap *m, *nm;
  1230. Pcminfo *pi;
  1231. int i;
  1232. ulong e;
  1233. pi = &cb->linfo;
  1234. /* convert offset to granularity */
  1235. if(len <= 0)
  1236. len = 1;
  1237. e = ROUND(offset+len, Mgran);
  1238. offset &= Mmask;
  1239. len = e - offset;
  1240. /* look for a map that covers the right area */
  1241. we = rdreg(cb, Rwe);
  1242. bit = 1;
  1243. nm = 0;
  1244. for(m = pi->mmap; m < &pi->mmap[nelem(pi->mmap)]; m++){
  1245. if((we & bit))
  1246. if(m->attr == attr)
  1247. if(offset >= m->ca && e <= m->cea){
  1248. m->ref++;
  1249. return m;
  1250. }
  1251. bit <<= 1;
  1252. if(nm == 0 && m->ref == 0)
  1253. nm = m;
  1254. }
  1255. m = nm;
  1256. if(m == 0)
  1257. return 0;
  1258. /* if isa space isn't big enough, free it and get more */
  1259. if(m->len < len){
  1260. if(m->isa){
  1261. umbfree(m->isa, m->len);
  1262. m->len = 0;
  1263. }
  1264. m->isa = PADDR(umbmalloc(0, len, Mgran));
  1265. if(m->isa == 0){
  1266. print("isamap: out of isa space\n");
  1267. return 0;
  1268. }
  1269. m->len = len;
  1270. }
  1271. /* set up new map */
  1272. m->ca = offset;
  1273. m->cea = m->ca + m->len;
  1274. m->attr = attr;
  1275. i = m - pi->mmap;
  1276. bit = 1<<i;
  1277. wrreg(cb, Rwe, we & ~bit); /* disable map before changing it */
  1278. wrreg(cb, MAP(i, Mbtmlo), m->isa>>Mshift);
  1279. wrreg(cb, MAP(i, Mbtmhi), (m->isa>>(Mshift+8)) | F16bit);
  1280. wrreg(cb, MAP(i, Mtoplo), (m->isa+m->len-1)>>Mshift);
  1281. wrreg(cb, MAP(i, Mtophi), ((m->isa+m->len-1)>>(Mshift+8)));
  1282. offset -= m->isa;
  1283. offset &= (1<<25)-1;
  1284. offset >>= Mshift;
  1285. wrreg(cb, MAP(i, Mofflo), offset);
  1286. wrreg(cb, MAP(i, Moffhi), (offset>>8) | (attr ? Fregactive : 0));
  1287. wrreg(cb, Rwe, we | bit); /* enable map */
  1288. m->ref = 1;
  1289. return m;
  1290. }
  1291. static void
  1292. isaunmap(PCMmap* m)
  1293. {
  1294. m->ref--;
  1295. }
  1296. /*
  1297. * reading and writing card registers
  1298. */
  1299. static uchar
  1300. rdreg(Cardbus *cb, int index)
  1301. {
  1302. outb(cb->lindex, cb->lbase + index);
  1303. return inb(cb->ldata);
  1304. }
  1305. static void
  1306. wrreg(Cardbus *cb, int index, uchar val)
  1307. {
  1308. outb(cb->lindex, cb->lbase + index);
  1309. outb(cb->ldata, val);
  1310. }
  1311. static int
  1312. readc(Cisdat *cis, uchar *x)
  1313. {
  1314. if(cis->cispos >= cis->cislen)
  1315. return 0;
  1316. *x = cis->cisbase[cis->cisskip*cis->cispos];
  1317. cis->cispos++;
  1318. return 1;
  1319. }
  1320. static ulong
  1321. getlong(Cisdat *cis, int size)
  1322. {
  1323. uchar c;
  1324. int i;
  1325. ulong x;
  1326. x = 0;
  1327. for(i = 0; i < size; i++){
  1328. if(readc(cis, &c) != 1)
  1329. break;
  1330. x |= c<<(i*8);
  1331. }
  1332. return x;
  1333. }
  1334. static void
  1335. tcfig(Cardbus *cb, Cisdat *cis, int )
  1336. {
  1337. uchar size, rasize, rmsize;
  1338. uchar last;
  1339. Pcminfo *pi;
  1340. if(readc(cis, &size) != 1)
  1341. return;
  1342. rasize = (size&0x3) + 1;
  1343. rmsize = ((size>>2)&0xf) + 1;
  1344. if(readc(cis, &last) != 1)
  1345. return;
  1346. pi = &cb->linfo;
  1347. pi->conf_addr = getlong(cis, rasize);
  1348. pi->conf_present = getlong(cis, rmsize);
  1349. }
  1350. static void
  1351. tvers1(Cardbus *cb, Cisdat *cis, int )
  1352. {
  1353. uchar c, major, minor, last;
  1354. int i;
  1355. Pcminfo *pi;
  1356. pi = &cb->linfo;
  1357. if(readc(cis, &major) != 1)
  1358. return;
  1359. if(readc(cis, &minor) != 1)
  1360. return;
  1361. last = 0;
  1362. for(i = 0; i < sizeof(pi->verstr) - 1; i++){
  1363. if(readc(cis, &c) != 1)
  1364. return;
  1365. if(c == 0)
  1366. c = ';';
  1367. if(c == '\n')
  1368. c = ';';
  1369. if(c == 0xff)
  1370. break;
  1371. if(c == ';' && last == ';')
  1372. continue;
  1373. pi->verstr[i] = c;
  1374. last = c;
  1375. }
  1376. pi->verstr[i] = 0;
  1377. }
  1378. static ulong
  1379. microvolt(Cisdat *cis)
  1380. {
  1381. uchar c;
  1382. ulong microvolts;
  1383. ulong exp;
  1384. if(readc(cis, &c) != 1)
  1385. return 0;
  1386. exp = exponent[c&0x7];
  1387. microvolts = vmant[(c>>3)&0xf]*exp;
  1388. while(c & 0x80){
  1389. if(readc(cis, &c) != 1)
  1390. return 0;
  1391. switch(c){
  1392. case 0x7d:
  1393. break; /* high impedence when sleeping */
  1394. case 0x7e:
  1395. case 0x7f:
  1396. microvolts = 0; /* no connection */
  1397. break;
  1398. default:
  1399. exp /= 10;
  1400. microvolts += exp*(c&0x7f);
  1401. }
  1402. }
  1403. return microvolts;
  1404. }
  1405. static ulong
  1406. nanoamps(Cisdat *cis)
  1407. {
  1408. uchar c;
  1409. ulong nanoamps;
  1410. if(readc(cis, &c) != 1)
  1411. return 0;
  1412. nanoamps = exponent[c&0x7]*vmant[(c>>3)&0xf];
  1413. while(c & 0x80){
  1414. if(readc(cis, &c) != 1)
  1415. return 0;
  1416. if(c == 0x7d || c == 0x7e || c == 0x7f)
  1417. nanoamps = 0;
  1418. }
  1419. return nanoamps;
  1420. }
  1421. /*
  1422. * only nominal voltage (feature 1) is important for config,
  1423. * other features must read card to stay in sync.
  1424. */
  1425. static ulong
  1426. power(Cisdat *cis)
  1427. {
  1428. uchar feature;
  1429. ulong mv;
  1430. mv = 0;
  1431. if(readc(cis, &feature) != 1)
  1432. return 0;
  1433. if(feature & 1)
  1434. mv = microvolt(cis);
  1435. if(feature & 2)
  1436. microvolt(cis);
  1437. if(feature & 4)
  1438. microvolt(cis);
  1439. if(feature & 8)
  1440. nanoamps(cis);
  1441. if(feature & 0x10)
  1442. nanoamps(cis);
  1443. if(feature & 0x20)
  1444. nanoamps(cis);
  1445. if(feature & 0x40)
  1446. nanoamps(cis);
  1447. return mv/1000000;
  1448. }
  1449. static ulong
  1450. ttiming(Cisdat *cis, int scale)
  1451. {
  1452. uchar unscaled;
  1453. ulong nanosecs;
  1454. if(readc(cis, &unscaled) != 1)
  1455. return 0;
  1456. nanosecs = (mantissa[(unscaled>>3)&0xf]*exponent[unscaled&7])/10;
  1457. nanosecs = nanosecs * exponent[scale];
  1458. return nanosecs;
  1459. }
  1460. static void
  1461. timing(Cisdat *cis, PCMconftab *ct)
  1462. {
  1463. uchar c, i;
  1464. if(readc(cis, &c) != 1)
  1465. return;
  1466. i = c&0x3;
  1467. if(i != 3)
  1468. ct->maxwait = ttiming(cis, i); /* max wait */
  1469. i = (c>>2)&0x7;
  1470. if(i != 7)
  1471. ct->readywait = ttiming(cis, i); /* max ready/busy wait */
  1472. i = (c>>5)&0x7;
  1473. if(i != 7)
  1474. ct->otherwait = ttiming(cis, i); /* reserved wait */
  1475. }
  1476. static void
  1477. iospaces(Cisdat *cis, PCMconftab *ct)
  1478. {
  1479. uchar c;
  1480. int i, nio;
  1481. ct->nio = 0;
  1482. if(readc(cis, &c) != 1)
  1483. return;
  1484. ct->bit16 = ((c>>5)&3) >= 2;
  1485. if(!(c & 0x80)){
  1486. ct->io[0].start = 0;
  1487. ct->io[0].len = 1<<(c&0x1f);
  1488. ct->nio = 1;
  1489. return;
  1490. }
  1491. if(readc(cis, &c) != 1)
  1492. return;
  1493. /*
  1494. * For each of the range descriptions read the
  1495. * start address and the length (value is length-1).
  1496. */
  1497. nio = (c&0xf)+1;
  1498. for(i = 0; i < nio; i++){
  1499. ct->io[i].start = getlong(cis, (c>>4)&0x3);
  1500. ct->io[i].len = getlong(cis, (c>>6)&0x3)+1;
  1501. }
  1502. ct->nio = nio;
  1503. }
  1504. static void
  1505. irq(Cisdat *cis, PCMconftab *ct)
  1506. {
  1507. uchar c;
  1508. if(readc(cis, &c) != 1)
  1509. return;
  1510. ct->irqtype = c & 0xe0;
  1511. if(c & 0x10)
  1512. ct->irqs = getlong(cis, 2);
  1513. else
  1514. ct->irqs = 1<<(c&0xf);
  1515. ct->irqs &= 0xDEB8; /* levels available to card */
  1516. }
  1517. static void
  1518. memspace(Cisdat *cis, int asize, int lsize, int host)
  1519. {
  1520. ulong haddress, address, len;
  1521. len = getlong(cis, lsize)*256;
  1522. address = getlong(cis, asize)*256;
  1523. USED(len, address);
  1524. if(host){
  1525. haddress = getlong(cis, asize)*256;
  1526. USED(haddress);
  1527. }
  1528. }
  1529. static void
  1530. tentry(Cardbus *cb, Cisdat *cis, int )
  1531. {
  1532. uchar c, i, feature;
  1533. PCMconftab *ct;
  1534. Pcminfo *pi;
  1535. pi = &cb->linfo;
  1536. if(pi->nctab >= nelem(pi->ctab))
  1537. return;
  1538. if(readc(cis, &c) != 1)
  1539. return;
  1540. ct = &pi->ctab[pi->nctab++];
  1541. /* copy from last default config */
  1542. if(pi->defctab)
  1543. *ct = *pi->defctab;
  1544. ct->index = c & 0x3f;
  1545. /* is this the new default? */
  1546. if(c & 0x40)
  1547. pi->defctab = ct;
  1548. /* memory wait specified? */
  1549. if(c & 0x80){
  1550. if(readc(cis, &i) != 1)
  1551. return;
  1552. if(i&0x80)
  1553. ct->memwait = 1;
  1554. }
  1555. if(readc(cis, &feature) != 1)
  1556. return;
  1557. switch(feature&0x3){
  1558. case 1:
  1559. ct->vpp1 = ct->vpp2 = power(cis);
  1560. break;
  1561. case 2:
  1562. power(cis);
  1563. ct->vpp1 = ct->vpp2 = power(cis);
  1564. break;
  1565. case 3:
  1566. power(cis);
  1567. ct->vpp1 = power(cis);
  1568. ct->vpp2 = power(cis);
  1569. break;
  1570. default:
  1571. break;
  1572. }
  1573. if(feature&0x4)
  1574. timing(cis, ct);
  1575. if(feature&0x8)
  1576. iospaces(cis, ct);
  1577. if(feature&0x10)
  1578. irq(cis, ct);
  1579. switch((feature>>5)&0x3){
  1580. case 1:
  1581. memspace(cis, 0, 2, 0);
  1582. break;
  1583. case 2:
  1584. memspace(cis, 2, 2, 0);
  1585. break;
  1586. case 3:
  1587. if(readc(cis, &c) != 1)
  1588. return;
  1589. for(i = 0; i <= (c&0x7); i++)
  1590. memspace(cis, (c>>5)&0x3, (c>>3)&0x3, c&0x80);
  1591. break;
  1592. }
  1593. }
  1594. static void
  1595. i82365probe(Cardbus *cb, int lindex, int ldata)
  1596. {
  1597. uchar c, id;
  1598. int dev = 0; /* According to the Ricoh spec 00->3F _and_ 80->BF seem
  1599. to be the same socket A (ditto for B). */
  1600. outb(lindex, Rid + (dev<<7));
  1601. id = inb(ldata);
  1602. if((id & 0xf0) != 0x80)
  1603. return; /* not a memory & I/O card */
  1604. if((id & 0x0f) == 0x00)
  1605. return; /* no revision number, not possible */
  1606. cb->lindex = lindex;
  1607. cb->ldata = ldata;
  1608. cb->ltype = Ti82365;
  1609. cb->lbase = (int)(cb - cbslots) * 0x40;
  1610. switch(id){
  1611. case 0x82:
  1612. case 0x83:
  1613. case 0x84:
  1614. /* could be a cirrus */
  1615. outb(cb->lindex, Rchipinfo + (dev<<7));
  1616. outb(cb->ldata, 0);
  1617. c = inb(cb->ldata);
  1618. if((c & 0xc0) != 0xc0)
  1619. break;
  1620. c = inb(cb->ldata);
  1621. if((c & 0xc0) != 0x00)
  1622. break;
  1623. if(c & 0x20){
  1624. cb->ltype = Tpd6720;
  1625. } else {
  1626. cb->ltype = Tpd6710;
  1627. }
  1628. /* low power mode */
  1629. outb(cb->lindex, Rmisc2 + (dev<<7));
  1630. c = inb(cb->ldata);
  1631. outb(cb->ldata, c & ~Flowpow);
  1632. break;
  1633. break;
  1634. }
  1635. /* if it's not a Cirrus, it could be a Vadem... */
  1636. if(cb->ltype == Ti82365){
  1637. /* unlock the Vadem extended regs */
  1638. outb(cb->lindex, 0x0E + (dev<<7));
  1639. outb(cb->lindex, 0x37 + (dev<<7));
  1640. /* make the id register show the Vadem id */
  1641. outb(cb->lindex, 0x3A + (dev<<7));
  1642. c = inb(cb->ldata);
  1643. outb(cb->ldata, c|0xC0);
  1644. outb(cb->lindex, Rid + (dev<<7));
  1645. c = inb(cb->ldata);
  1646. if(c & 0x08)
  1647. cb->ltype = Tvg46x;
  1648. /* go back to Intel compatible id */
  1649. outb(cb->lindex, 0x3A + (dev<<7));
  1650. c = inb(cb->ldata);
  1651. outb(cb->ldata, c & ~0xC0);
  1652. }
  1653. }
  1654. static int
  1655. vcode(int volt)
  1656. {
  1657. switch(volt){
  1658. case 5:
  1659. return 1;
  1660. case 12:
  1661. return 2;
  1662. default:
  1663. return 0;
  1664. }
  1665. }