ether8139.c 20 KB

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  1. /*
  2. * Realtek 8139 (but not the 8129).
  3. * Error recovery for the various over/under -flow conditions
  4. * may need work.
  5. */
  6. #include "u.h"
  7. #include "../port/lib.h"
  8. #include "mem.h"
  9. #include "dat.h"
  10. #include "fns.h"
  11. #include "io.h"
  12. #include "../port/error.h"
  13. #include "../port/netif.h"
  14. #include "etherif.h"
  15. enum { /* registers */
  16. Idr0 = 0x0000, /* MAC address */
  17. Mar0 = 0x0008, /* Multicast address */
  18. Tsd0 = 0x0010, /* Transmit Status Descriptor0 */
  19. Tsad0 = 0x0020, /* Transmit Start Address Descriptor0 */
  20. Rbstart = 0x0030, /* Receive Buffer Start Address */
  21. Erbcr = 0x0034, /* Early Receive Byte Count */
  22. Ersr = 0x0036, /* Early Receive Status */
  23. Cr = 0x0037, /* Command Register */
  24. Capr = 0x0038, /* Current Address of Packet Read */
  25. Cbr = 0x003A, /* Current Buffer Address */
  26. Imr = 0x003C, /* Interrupt Mask */
  27. Isr = 0x003E, /* Interrupt Status */
  28. Tcr = 0x0040, /* Transmit Configuration */
  29. Rcr = 0x0044, /* Receive Configuration */
  30. Tctr = 0x0048, /* Timer Count */
  31. Mpc = 0x004C, /* Missed Packet Counter */
  32. Cr9346 = 0x0050, /* 9346 Command Register */
  33. Config0 = 0x0051, /* Configuration Register 0 */
  34. Config1 = 0x0052, /* Configuration Register 1 */
  35. TimerInt = 0x0054, /* Timer Interrupt */
  36. Msr = 0x0058, /* Media Status */
  37. Config3 = 0x0059, /* Configuration Register 3 */
  38. Config4 = 0x005A, /* Configuration Register 4 */
  39. Mulint = 0x005C, /* Multiple Interrupt Select */
  40. RerID = 0x005E, /* PCI Revision ID */
  41. Tsad = 0x0060, /* Transmit Status of all Descriptors */
  42. Bmcr = 0x0062, /* Basic Mode Control */
  43. Bmsr = 0x0064, /* Basic Mode Status */
  44. Anar = 0x0066, /* Auto-Negotiation Advertisment */
  45. Anlpar = 0x0068, /* Auto-Negotiation Link Partner */
  46. Aner = 0x006A, /* Auto-Negotiation Expansion */
  47. Dis = 0x006C, /* Disconnect Counter */
  48. Fcsc = 0x006E, /* False Carrier Sense Counter */
  49. Nwaytr = 0x0070, /* N-way Test */
  50. Rec = 0x0072, /* RX_ER Counter */
  51. Cscr = 0x0074, /* CS Configuration */
  52. Phy1parm = 0x0078, /* PHY Parameter 1 */
  53. Twparm = 0x007C, /* Twister Parameter */
  54. Phy2parm = 0x0080, /* PHY Parameter 2 */
  55. };
  56. enum { /* Cr */
  57. Bufe = 0x01, /* Rx Buffer Empty */
  58. Te = 0x04, /* Transmitter Enable */
  59. Re = 0x08, /* Receiver Enable */
  60. Rst = 0x10, /* Software Reset */
  61. };
  62. enum { /* Imr/Isr */
  63. Rok = 0x0001, /* Receive OK */
  64. Rer = 0x0002, /* Receive Error */
  65. Tok = 0x0004, /* Transmit OK */
  66. Ter = 0x0008, /* Transmit Error */
  67. Rxovw = 0x0010, /* Receive Buffer Overflow */
  68. PunLc = 0x0020, /* Packet Underrun or Link Change */
  69. Fovw = 0x0040, /* Receive FIFO Overflow */
  70. Clc = 0x2000, /* Cable Length Change */
  71. Timerbit = 0x4000, /* Timer */
  72. Serr = 0x8000, /* System Error */
  73. };
  74. enum { /* Tcr */
  75. Clrabt = 0x00000001, /* Clear Abort */
  76. TxrrSHIFT = 4, /* Transmit Retry Count */
  77. TxrrMASK = 0x000000F0,
  78. MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
  79. MtxdmaMASK = 0x00000700,
  80. Mtxdma2048 = 0x00000700,
  81. Acrc = 0x00010000, /* Append CRC (not) */
  82. LbkSHIFT = 17, /* Loopback Test */
  83. LbkMASK = 0x00060000,
  84. Rtl8139ArevG = 0x00800000, /* RTL8139A Rev. G ID */
  85. IfgSHIFT = 24, /* Interframe Gap */
  86. IfgMASK = 0x03000000,
  87. HwveridSHIFT = 26, /* Hardware Version ID */
  88. HwveridMASK = 0x7C000000,
  89. };
  90. enum { /* Rcr */
  91. Aap = 0x00000001, /* Accept All Packets */
  92. Apm = 0x00000002, /* Accept Physical Match */
  93. Am = 0x00000004, /* Accept Multicast */
  94. Ab = 0x00000008, /* Accept Broadcast */
  95. Ar = 0x00000010, /* Accept Runt */
  96. Aer = 0x00000020, /* Accept Error */
  97. Sel9356 = 0x00000040, /* 9356 EEPROM used */
  98. Wrap = 0x00000080, /* Rx Buffer Wrap Control */
  99. MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
  100. MrxdmaMASK = 0x00000700,
  101. Mrxdmaunlimited = 0x00000700,
  102. RblenSHIFT = 11, /* Receive Buffer Length */
  103. RblenMASK = 0x00001800,
  104. Rblen8K = 0x00000000, /* 8KB+16 */
  105. Rblen16K = 0x00000800, /* 16KB+16 */
  106. Rblen32K = 0x00001000, /* 32KB+16 */
  107. Rblen64K = 0x00001800, /* 64KB+16 */
  108. RxfthSHIFT = 13, /* Receive Buffer Length */
  109. RxfthMASK = 0x0000E000,
  110. Rxfth256 = 0x00008000,
  111. Rxfthnone = 0x0000E000,
  112. Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
  113. MulERINT = 0x00020000, /* Multiple Early Interrupt Select */
  114. ErxthSHIFT = 24, /* Early Rx Threshold */
  115. ErxthMASK = 0x0F000000,
  116. Erxthnone = 0x00000000,
  117. };
  118. enum { /* Received Packet Status */
  119. Rcok = 0x0001, /* Receive Completed OK */
  120. Fae = 0x0002, /* Frame Alignment Error */
  121. Crc = 0x0004, /* CRC Error */
  122. Long = 0x0008, /* Long Packet */
  123. Runt = 0x0010, /* Runt Packet Received */
  124. Ise = 0x0020, /* Invalid Symbol Error */
  125. Bar = 0x2000, /* Broadcast Address Received */
  126. Pam = 0x4000, /* Physical Address Matched */
  127. Mar = 0x8000, /* Multicast Address Received */
  128. };
  129. enum { /* Media Status Register */
  130. Rxpf = 0x01, /* Pause Flag */
  131. Txpf = 0x02, /* Pause Flag */
  132. Linkb = 0x04, /* Inverse of Link Status */
  133. Speed10 = 0x08, /* 10Mbps */
  134. Auxstatus = 0x10, /* Aux. Power Present Status */
  135. Rxfce = 0x40, /* Receive Flow Control Enable */
  136. Txfce = 0x80, /* Transmit Flow Control Enable */
  137. };
  138. typedef struct Td Td;
  139. struct Td { /* Soft Transmit Descriptor */
  140. int tsd;
  141. int tsad;
  142. uchar* data;
  143. Block* bp;
  144. };
  145. enum { /* Tsd0 */
  146. SizeSHIFT = 0, /* Descriptor Size */
  147. SizeMASK = 0x00001FFF,
  148. Own = 0x00002000,
  149. Tun = 0x00004000, /* Transmit FIFO Underrun */
  150. Tcok = 0x00008000, /* Transmit COmpleted OK */
  151. EtxthSHIFT = 16, /* Early Tx Threshold */
  152. EtxthMASK = 0x001F0000,
  153. NccSHIFT = 24, /* Number of Collisions Count */
  154. NccMASK = 0x0F000000,
  155. Cdh = 0x10000000, /* CD Heartbeat */
  156. Owc = 0x20000000, /* Out of Window Collision */
  157. Tabt = 0x40000000, /* Transmit Abort */
  158. Crs = 0x80000000, /* Carrier Sense Lost */
  159. };
  160. enum {
  161. Rblen = Rblen64K, /* Receive Buffer Length */
  162. Ntd = 4, /* Number of Transmit Descriptors */
  163. Tdbsz = ROUNDUP(sizeof(Etherpkt), 4),
  164. };
  165. typedef struct Ctlr Ctlr;
  166. typedef struct Ctlr {
  167. int port;
  168. Pcidev* pcidev;
  169. Ctlr* next;
  170. int active;
  171. int id;
  172. QLock alock; /* attach */
  173. Lock ilock; /* init */
  174. void* alloc; /* base of per-Ctlr allocated data */
  175. int pcie; /* flag: pci-express device? */
  176. uvlong mchash; /* multicast hash */
  177. int rcr; /* receive configuration register */
  178. uchar* rbstart; /* receive buffer */
  179. int rblen; /* receive buffer length */
  180. int ierrs; /* receive errors */
  181. Lock tlock; /* transmit */
  182. Td td[Ntd];
  183. int ntd; /* descriptors active */
  184. int tdh; /* host index into td */
  185. int tdi; /* interface index into td */
  186. int etxth; /* early transmit threshold */
  187. int taligned; /* packet required no alignment */
  188. int tunaligned; /* packet required alignment */
  189. int dis; /* disconnect counter */
  190. int fcsc; /* false carrier sense counter */
  191. int rec; /* RX_ER counter */
  192. uint mcast;
  193. } Ctlr;
  194. static Ctlr* ctlrhead;
  195. static Ctlr* ctlrtail;
  196. #define csr8r(c, r) (inb((c)->port+(r)))
  197. #define csr16r(c, r) (ins((c)->port+(r)))
  198. #define csr32r(c, r) (inl((c)->port+(r)))
  199. #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
  200. #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
  201. #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
  202. static void
  203. rtl8139promiscuous(void* arg, int on)
  204. {
  205. Ether *edev;
  206. Ctlr * ctlr;
  207. edev = arg;
  208. ctlr = edev->ctlr;
  209. ilock(&ctlr->ilock);
  210. if(on)
  211. ctlr->rcr |= Aap;
  212. else
  213. ctlr->rcr &= ~Aap;
  214. csr32w(ctlr, Rcr, ctlr->rcr);
  215. iunlock(&ctlr->ilock);
  216. }
  217. enum {
  218. /* everyone else uses 0x04c11db7, but they both produce the same crc */
  219. Etherpolybe = 0x04c11db6,
  220. Bytemask = (1<<8) - 1,
  221. };
  222. static ulong
  223. ethercrcbe(uchar *addr, long len)
  224. {
  225. int i, j;
  226. ulong c, crc, carry;
  227. crc = ~0UL;
  228. for (i = 0; i < len; i++) {
  229. c = addr[i];
  230. for (j = 0; j < 8; j++) {
  231. carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
  232. crc <<= 1;
  233. c >>= 1;
  234. if (carry)
  235. crc = (crc ^ Etherpolybe) | carry;
  236. }
  237. }
  238. return crc;
  239. }
  240. static ulong
  241. swabl(ulong l)
  242. {
  243. return l>>24 | (l>>8) & (Bytemask<<8) |
  244. (l<<8) & (Bytemask<<16) | l<<24;
  245. }
  246. static void
  247. rtl8139multicast(void* ether, uchar *eaddr, int add)
  248. {
  249. Ether *edev;
  250. Ctlr *ctlr;
  251. if (!add)
  252. return; /* ok to keep receiving on old mcast addrs */
  253. edev = ether;
  254. ctlr = edev->ctlr;
  255. ilock(&ctlr->ilock);
  256. ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
  257. ctlr->rcr |= Am;
  258. csr32w(ctlr, Rcr, ctlr->rcr);
  259. /* pci-e variants reverse the order of the hash byte registers */
  260. if (0 && ctlr->pcie) {
  261. csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
  262. csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
  263. } else {
  264. csr32w(ctlr, Mar0, ctlr->mchash);
  265. csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
  266. }
  267. iunlock(&ctlr->ilock);
  268. }
  269. static long
  270. rtl8139ifstat(Ether* edev, void* a, long n, ulong offset)
  271. {
  272. int l;
  273. char *p;
  274. Ctlr *ctlr;
  275. ctlr = edev->ctlr;
  276. p = malloc(READSTR);
  277. l = snprint(p, READSTR, "rcr %#8.8ux\n", ctlr->rcr);
  278. l += snprint(p+l, READSTR-l, "multicast %ud\n", ctlr->mcast);
  279. l += snprint(p+l, READSTR-l, "ierrs %d\n", ctlr->ierrs);
  280. l += snprint(p+l, READSTR-l, "etxth %d\n", ctlr->etxth);
  281. l += snprint(p+l, READSTR-l, "taligned %d\n", ctlr->taligned);
  282. l += snprint(p+l, READSTR-l, "tunaligned %d\n", ctlr->tunaligned);
  283. ctlr->dis += csr16r(ctlr, Dis);
  284. l += snprint(p+l, READSTR-l, "dis %d\n", ctlr->dis);
  285. ctlr->fcsc += csr16r(ctlr, Fcsc);
  286. l += snprint(p+l, READSTR-l, "fcscnt %d\n", ctlr->fcsc);
  287. ctlr->rec += csr16r(ctlr, Rec);
  288. l += snprint(p+l, READSTR-l, "rec %d\n", ctlr->rec);
  289. l += snprint(p+l, READSTR-l, "Tcr %#8.8lux\n", csr32r(ctlr, Tcr));
  290. l += snprint(p+l, READSTR-l, "Config0 %#2.2ux\n", csr8r(ctlr, Config0));
  291. l += snprint(p+l, READSTR-l, "Config1 %#2.2ux\n", csr8r(ctlr, Config1));
  292. l += snprint(p+l, READSTR-l, "Msr %#2.2ux\n", csr8r(ctlr, Msr));
  293. l += snprint(p+l, READSTR-l, "Config3 %#2.2ux\n", csr8r(ctlr, Config3));
  294. l += snprint(p+l, READSTR-l, "Config4 %#2.2ux\n", csr8r(ctlr, Config4));
  295. l += snprint(p+l, READSTR-l, "Bmcr %#4.4ux\n", csr16r(ctlr, Bmcr));
  296. l += snprint(p+l, READSTR-l, "Bmsr %#4.4ux\n", csr16r(ctlr, Bmsr));
  297. l += snprint(p+l, READSTR-l, "Anar %#4.4ux\n", csr16r(ctlr, Anar));
  298. l += snprint(p+l, READSTR-l, "Anlpar %#4.4ux\n", csr16r(ctlr, Anlpar));
  299. l += snprint(p+l, READSTR-l, "Aner %#4.4ux\n", csr16r(ctlr, Aner));
  300. l += snprint(p+l, READSTR-l, "Nwaytr %#4.4ux\n", csr16r(ctlr, Nwaytr));
  301. snprint(p+l, READSTR-l, "Cscr %#4.4ux\n", csr16r(ctlr, Cscr));
  302. n = readstr(offset, a, n, p);
  303. free(p);
  304. return n;
  305. }
  306. static int
  307. rtl8139reset(Ctlr* ctlr)
  308. {
  309. int timeo;
  310. /*
  311. * Soft reset the controller.
  312. */
  313. csr8w(ctlr, Cr, Rst);
  314. for(timeo = 0; timeo < 1000; timeo++){
  315. if(!(csr8r(ctlr, Cr) & Rst))
  316. return 0;
  317. delay(1);
  318. }
  319. return -1;
  320. }
  321. static void
  322. rtl8139halt(Ctlr* ctlr)
  323. {
  324. int i;
  325. csr8w(ctlr, Cr, 0);
  326. csr16w(ctlr, Imr, 0);
  327. csr16w(ctlr, Isr, ~0);
  328. for(i = 0; i < Ntd; i++){
  329. if(ctlr->td[i].bp == nil)
  330. continue;
  331. freeb(ctlr->td[i].bp);
  332. ctlr->td[i].bp = nil;
  333. }
  334. }
  335. static void
  336. rtl8139init(Ether* edev)
  337. {
  338. int i;
  339. ulong r;
  340. Ctlr *ctlr;
  341. uchar *alloc;
  342. ctlr = edev->ctlr;
  343. ilock(&ctlr->ilock);
  344. rtl8139halt(ctlr);
  345. /*
  346. * MAC Address.
  347. */
  348. r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
  349. csr32w(ctlr, Idr0, r);
  350. r = (edev->ea[5]<<8)|edev->ea[4];
  351. csr32w(ctlr, Idr0+4, r);
  352. /*
  353. * Receiver
  354. */
  355. alloc = (uchar*)ROUNDUP((ulong)ctlr->alloc, 32);
  356. ctlr->rbstart = alloc;
  357. alloc += ctlr->rblen+16;
  358. memset(ctlr->rbstart, 0, ctlr->rblen+16);
  359. csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
  360. ctlr->rcr = Rxfth256|Rblen|Mrxdmaunlimited|Ab|Am|Apm;
  361. /*
  362. * Transmitter.
  363. */
  364. for(i = 0; i < Ntd; i++){
  365. ctlr->td[i].tsd = Tsd0+i*4;
  366. ctlr->td[i].tsad = Tsad0+i*4;
  367. ctlr->td[i].data = alloc;
  368. alloc += Tdbsz;
  369. ctlr->td[i].bp = nil;
  370. }
  371. ctlr->ntd = ctlr->tdh = ctlr->tdi = 0;
  372. ctlr->etxth = 128/32;
  373. /*
  374. * Interrupts.
  375. */
  376. csr32w(ctlr, TimerInt, 0);
  377. csr16w(ctlr, Imr, Serr|Timerbit|Fovw|PunLc|Rxovw|Ter|Tok|Rer|Rok);
  378. csr32w(ctlr, Mpc, 0);
  379. /*
  380. * Enable receiver/transmitter.
  381. * Need to enable before writing the Rcr or it won't take.
  382. */
  383. csr8w(ctlr, Cr, Te|Re);
  384. csr32w(ctlr, Tcr, Mtxdma2048);
  385. csr32w(ctlr, Rcr, ctlr->rcr);
  386. csr32w(ctlr, Mar0, 0);
  387. csr32w(ctlr, Mar0+4, 0);
  388. ctlr->mchash = 0;
  389. iunlock(&ctlr->ilock);
  390. }
  391. static void
  392. rtl8139attach(Ether* edev)
  393. {
  394. Ctlr *ctlr;
  395. ctlr = edev->ctlr;
  396. qlock(&ctlr->alock);
  397. if(ctlr->alloc == nil){
  398. ctlr->rblen = 1<<((Rblen>>RblenSHIFT)+13);
  399. ctlr->alloc = mallocz(ctlr->rblen+16 + Ntd*Tdbsz + 32, 0);
  400. rtl8139init(edev);
  401. }
  402. qunlock(&ctlr->alock);
  403. }
  404. static void
  405. rtl8139txstart(Ether* edev)
  406. {
  407. Td *td;
  408. int size;
  409. Block *bp;
  410. Ctlr *ctlr;
  411. ctlr = edev->ctlr;
  412. while(ctlr->ntd < Ntd){
  413. bp = qget(edev->oq);
  414. if(bp == nil)
  415. break;
  416. size = BLEN(bp);
  417. td = &ctlr->td[ctlr->tdh];
  418. if(((int)bp->rp) & 0x03){
  419. memmove(td->data, bp->rp, size);
  420. freeb(bp);
  421. csr32w(ctlr, td->tsad, PCIWADDR(td->data));
  422. ctlr->tunaligned++;
  423. }
  424. else{
  425. td->bp = bp;
  426. csr32w(ctlr, td->tsad, PCIWADDR(bp->rp));
  427. ctlr->taligned++;
  428. }
  429. csr32w(ctlr, td->tsd, (ctlr->etxth<<EtxthSHIFT)|size);
  430. ctlr->ntd++;
  431. ctlr->tdh = NEXT(ctlr->tdh, Ntd);
  432. }
  433. }
  434. static void
  435. rtl8139transmit(Ether* edev)
  436. {
  437. Ctlr *ctlr;
  438. ctlr = edev->ctlr;
  439. ilock(&ctlr->tlock);
  440. rtl8139txstart(edev);
  441. iunlock(&ctlr->tlock);
  442. }
  443. static void
  444. rtl8139receive(Ether* edev)
  445. {
  446. Block *bp;
  447. Ctlr *ctlr;
  448. ushort capr;
  449. uchar cr, *p;
  450. int l, length, status;
  451. ctlr = edev->ctlr;
  452. /*
  453. * Capr is where the host is reading from,
  454. * Cbr is where the NIC is currently writing.
  455. */
  456. capr = (csr16r(ctlr, Capr)+16) % ctlr->rblen;
  457. while(!(csr8r(ctlr, Cr) & Bufe)){
  458. p = ctlr->rbstart+capr;
  459. /*
  460. * Apparently the packet length may be 0xFFF0 if
  461. * the NIC is still copying the packet into memory.
  462. */
  463. length = (*(p+3)<<8)|*(p+2);
  464. if(length == 0xFFF0)
  465. break;
  466. status = (*(p+1)<<8)|*p;
  467. if(!(status & Rcok)){
  468. if(status & (Ise|Fae))
  469. edev->frames++;
  470. if(status & Crc)
  471. edev->crcs++;
  472. if(status & (Runt|Long))
  473. edev->buffs++;
  474. /*
  475. * Reset the receiver.
  476. * Also may have to restore the multicast list
  477. * here too if it ever gets used.
  478. */
  479. cr = csr8r(ctlr, Cr);
  480. csr8w(ctlr, Cr, cr & ~Re);
  481. csr32w(ctlr, Rbstart, PCIWADDR(ctlr->rbstart));
  482. csr8w(ctlr, Cr, cr);
  483. csr32w(ctlr, Rcr, ctlr->rcr);
  484. continue;
  485. }
  486. /*
  487. * Receive Completed OK.
  488. * Very simplistic; there are ways this could be done
  489. * without copying, but the juice probably isn't worth
  490. * the squeeze.
  491. * The packet length includes a 4 byte CRC on the end.
  492. */
  493. capr = (capr+4) % ctlr->rblen;
  494. p = ctlr->rbstart+capr;
  495. capr = (capr+length) % ctlr->rblen;
  496. if(status & Mar)
  497. ctlr->mcast++;
  498. if((bp = iallocb(length)) != nil){
  499. if(p+length >= ctlr->rbstart+ctlr->rblen){
  500. l = ctlr->rbstart+ctlr->rblen - p;
  501. memmove(bp->wp, p, l);
  502. bp->wp += l;
  503. length -= l;
  504. p = ctlr->rbstart;
  505. }
  506. if(length > 0){
  507. memmove(bp->wp, p, length);
  508. bp->wp += length;
  509. }
  510. bp->wp -= 4;
  511. etheriq(edev, bp, 1);
  512. }
  513. capr = ROUNDUP(capr, 4);
  514. csr16w(ctlr, Capr, capr-16);
  515. }
  516. }
  517. static void
  518. rtl8139interrupt(Ureg*, void* arg)
  519. {
  520. Td *td;
  521. Ctlr *ctlr;
  522. Ether *edev;
  523. int isr, msr, tsd;
  524. edev = arg;
  525. ctlr = edev->ctlr;
  526. while((isr = csr16r(ctlr, Isr)) != 0){
  527. csr16w(ctlr, Isr, isr);
  528. if(isr & (Fovw|PunLc|Rxovw|Rer|Rok)){
  529. rtl8139receive(edev);
  530. if(!(isr & Rok))
  531. ctlr->ierrs++;
  532. isr &= ~(Fovw|Rxovw|Rer|Rok);
  533. }
  534. if(isr & (Ter|Tok)){
  535. ilock(&ctlr->tlock);
  536. while(ctlr->ntd){
  537. td = &ctlr->td[ctlr->tdi];
  538. tsd = csr32r(ctlr, td->tsd);
  539. if(!(tsd & (Tabt|Tun|Tcok)))
  540. break;
  541. if(!(tsd & Tcok)){
  542. if(tsd & Tun){
  543. if(ctlr->etxth < ETHERMAXTU/32)
  544. ctlr->etxth++;
  545. }
  546. edev->oerrs++;
  547. }
  548. if(td->bp != nil){
  549. freeb(td->bp);
  550. td->bp = nil;
  551. }
  552. ctlr->ntd--;
  553. ctlr->tdi = NEXT(ctlr->tdi, Ntd);
  554. }
  555. rtl8139txstart(edev);
  556. iunlock(&ctlr->tlock);
  557. isr &= ~(Ter|Tok);
  558. }
  559. if(isr & PunLc){
  560. /*
  561. * Maybe the link changed - do we care very much?
  562. */
  563. msr = csr8r(ctlr, Msr);
  564. if(!(msr & Linkb)){
  565. if(!(msr & Speed10) && edev->mbps != 100){
  566. edev->mbps = 100;
  567. qsetlimit(edev->oq, 256*1024);
  568. }
  569. else if((msr & Speed10) && edev->mbps != 10){
  570. edev->mbps = 10;
  571. qsetlimit(edev->oq, 65*1024);
  572. }
  573. }
  574. isr &= ~(Clc|PunLc);
  575. }
  576. /*
  577. * Only Serr|Timerbit should be left by now.
  578. * Should anything be done to tidy up? TimerInt isn't
  579. * used so that can be cleared. A PCI bus error is indicated
  580. * by Serr, that's pretty serious; is there anyhing to do
  581. * other than try to reinitialise the chip?
  582. */
  583. if((isr & (Serr|Timerbit)) != 0){
  584. iprint("rtl8139interrupt: imr %#4.4ux isr %#4.4ux\n",
  585. csr16r(ctlr, Imr), isr);
  586. if(isr & Timerbit)
  587. csr32w(ctlr, TimerInt, 0);
  588. if(isr & Serr)
  589. rtl8139init(edev);
  590. }
  591. }
  592. }
  593. static Ctlr*
  594. rtl8139match(Ether* edev, int id)
  595. {
  596. Pcidev *p;
  597. Ctlr *ctlr;
  598. int i, port;
  599. /*
  600. * Any adapter matches if no edev->port is supplied,
  601. * otherwise the ports must match.
  602. */
  603. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  604. if(ctlr->active)
  605. continue;
  606. p = ctlr->pcidev;
  607. if(((p->did<<16)|p->vid) != id)
  608. continue;
  609. port = p->mem[0].bar & ~0x01;
  610. if(edev->port != 0 && edev->port != port)
  611. continue;
  612. if(ioalloc(port, p->mem[0].size, 0, "rtl8139") < 0){
  613. print("rtl8139: port %#ux in use\n", port);
  614. continue;
  615. }
  616. if(pcigetpms(p) > 0){
  617. pcisetpms(p, 0);
  618. for(i = 0; i < 6; i++)
  619. pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
  620. pcicfgw8(p, PciINTL, p->intl);
  621. pcicfgw8(p, PciLTR, p->ltr);
  622. pcicfgw8(p, PciCLS, p->cls);
  623. pcicfgw16(p, PciPCR, p->pcr);
  624. }
  625. ctlr->port = port;
  626. if(rtl8139reset(ctlr)) {
  627. iofree(port);
  628. continue;
  629. }
  630. pcisetbme(p);
  631. ctlr->active = 1;
  632. return ctlr;
  633. }
  634. return nil;
  635. }
  636. static struct {
  637. char* name;
  638. int id;
  639. } rtl8139pci[] = {
  640. { "rtl8139", (0x8139<<16)|0x10EC, }, /* generic */
  641. { "smc1211", (0x1211<<16)|0x1113, }, /* SMC EZ-Card */
  642. { "dfe-538tx", (0x1300<<16)|0x1186, }, /* D-Link DFE-538TX */
  643. { "dfe-560txd", (0x1340<<16)|0x1186, }, /* D-Link DFE-560TXD */
  644. { nil },
  645. };
  646. static int
  647. rtl8139pnp(Ether* edev)
  648. {
  649. int i, id;
  650. Pcidev *p;
  651. Ctlr *ctlr;
  652. uchar ea[Eaddrlen];
  653. /*
  654. * Make a list of all ethernet controllers
  655. * if not already done.
  656. */
  657. if(ctlrhead == nil){
  658. p = nil;
  659. while(p = pcimatch(p, 0, 0)){
  660. if(p->ccrb != 0x02 || p->ccru != 0)
  661. continue;
  662. ctlr = malloc(sizeof(Ctlr));
  663. ctlr->pcidev = p;
  664. ctlr->id = (p->did<<16)|p->vid;
  665. if(ctlrhead != nil)
  666. ctlrtail->next = ctlr;
  667. else
  668. ctlrhead = ctlr;
  669. ctlrtail = ctlr;
  670. }
  671. }
  672. /*
  673. * Is it an RTL8139 under a different name?
  674. * Normally a search is made through all the found controllers
  675. * for one which matches any of the known vid+did pairs.
  676. * If a vid+did pair is specified a search is made for that
  677. * specific controller only.
  678. */
  679. id = 0;
  680. for(i = 0; i < edev->nopt; i++){
  681. if(cistrncmp(edev->opt[i], "id=", 3) == 0)
  682. id = strtol(&edev->opt[i][3], nil, 0);
  683. }
  684. ctlr = nil;
  685. if(id != 0)
  686. ctlr = rtl8139match(edev, id);
  687. else for(i = 0; rtl8139pci[i].name; i++){
  688. if((ctlr = rtl8139match(edev, rtl8139pci[i].id)) != nil)
  689. break;
  690. }
  691. if(ctlr == nil)
  692. return -1;
  693. edev->ctlr = ctlr;
  694. edev->port = ctlr->port;
  695. edev->irq = ctlr->pcidev->intl;
  696. edev->tbdf = ctlr->pcidev->tbdf;
  697. /*
  698. * Check if the adapter's station address is to be overridden.
  699. * If not, read it from the device and set in edev->ea.
  700. */
  701. memset(ea, 0, Eaddrlen);
  702. if(memcmp(ea, edev->ea, Eaddrlen) == 0){
  703. i = csr32r(ctlr, Idr0);
  704. edev->ea[0] = i;
  705. edev->ea[1] = i>>8;
  706. edev->ea[2] = i>>16;
  707. edev->ea[3] = i>>24;
  708. i = csr32r(ctlr, Idr0+4);
  709. edev->ea[4] = i;
  710. edev->ea[5] = i>>8;
  711. }
  712. edev->attach = rtl8139attach;
  713. edev->transmit = rtl8139transmit;
  714. edev->interrupt = rtl8139interrupt;
  715. edev->ifstat = rtl8139ifstat;
  716. edev->arg = edev;
  717. edev->promiscuous = rtl8139promiscuous;
  718. edev->multicast = rtl8139multicast;
  719. // edev->shutdown = rtl8139shutdown;
  720. /*
  721. * This should be much more dynamic but will do for now.
  722. */
  723. if((csr8r(ctlr, Msr) & (Speed10|Linkb)) == 0)
  724. edev->mbps = 100;
  725. return 0;
  726. }
  727. void
  728. ether8139link(void)
  729. {
  730. addethercard("rtl8139", rtl8139pnp);
  731. }