ether8169.c 26 KB

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  1. /*
  2. * Realtek RTL8110S/8169S.
  3. * Mostly there. There are some magic register values used
  4. * which are not described in any datasheet or driver but seem
  5. * to be necessary.
  6. * No tuning has been done. Only tested on an RTL8110S, there
  7. * are slight differences between the chips in the series so some
  8. * tweaks may be needed.
  9. */
  10. #include "u.h"
  11. #include "../port/lib.h"
  12. #include "mem.h"
  13. #include "dat.h"
  14. #include "fns.h"
  15. #include "io.h"
  16. #include "../port/error.h"
  17. #include "../port/netif.h"
  18. #include "etherif.h"
  19. #include "ethermii.h"
  20. enum { /* registers */
  21. Idr0 = 0x00, /* MAC address */
  22. Mar0 = 0x08, /* Multicast address */
  23. Dtccr = 0x10, /* Dump Tally Counter Command */
  24. Tnpds = 0x20, /* Transmit Normal Priority Descriptors */
  25. Thpds = 0x28, /* Transmit High Priority Descriptors */
  26. Flash = 0x30, /* Flash Memory Read/Write */
  27. Erbcr = 0x34, /* Early Receive Byte Count */
  28. Ersr = 0x36, /* Early Receive Status */
  29. Cr = 0x37, /* Command Register */
  30. Tppoll = 0x38, /* Transmit Priority Polling */
  31. Imr = 0x3C, /* Interrupt Mask */
  32. Isr = 0x3E, /* Interrupt Status */
  33. Tcr = 0x40, /* Transmit Configuration */
  34. Rcr = 0x44, /* Receive Configuration */
  35. Tctr = 0x48, /* Timer Count */
  36. Mpc = 0x4C, /* Missed Packet Counter */
  37. Cr9346 = 0x50, /* 9346 Command Register */
  38. Config0 = 0x51, /* Configuration Register 0 */
  39. Config1 = 0x52, /* Configuration Register 1 */
  40. Config2 = 0x53, /* Configuration Register 2 */
  41. Config3 = 0x54, /* Configuration Register 3 */
  42. Config4 = 0x55, /* Configuration Register 4 */
  43. Config5 = 0x56, /* Configuration Register 5 */
  44. Timerint = 0x58, /* Timer Interrupt */
  45. Mulint = 0x5C, /* Multiple Interrupt Select */
  46. Phyar = 0x60, /* PHY Access */
  47. Tbicsr0 = 0x64, /* TBI Control and Status */
  48. Tbianar = 0x68, /* TBI Auto-Negotiation Advertisment */
  49. Tbilpar = 0x6A, /* TBI Auto-Negotiation Link Partner */
  50. Phystatus = 0x6C, /* PHY Status */
  51. Rms = 0xDA, /* Receive Packet Maximum Size */
  52. Cplusc = 0xE0, /* C+ Command */
  53. Rdsar = 0xE4, /* Receive Descriptor Start Address */
  54. Mtps = 0xEC, /* Max. Transmit Packet Size */
  55. };
  56. enum { /* Dtccr */
  57. Cmd = 0x00000008, /* Command */
  58. };
  59. enum { /* Cr */
  60. Te = 0x04, /* Transmitter Enable */
  61. Re = 0x08, /* Receiver Enable */
  62. Rst = 0x10, /* Software Reset */
  63. };
  64. enum { /* Tppoll */
  65. Fswint = 0x01, /* Forced Software Interrupt */
  66. Npq = 0x40, /* Normal Priority Queue polling */
  67. Hpq = 0x80, /* High Priority Queue polling */
  68. };
  69. enum { /* Imr/Isr */
  70. Rok = 0x0001, /* Receive OK */
  71. Rer = 0x0002, /* Receive Error */
  72. Tok = 0x0004, /* Transmit OK */
  73. Ter = 0x0008, /* Transmit Error */
  74. Rdu = 0x0010, /* Receive Descriptor Unavailable */
  75. Punlc = 0x0020, /* Packet Underrun or Link Change */
  76. Fovw = 0x0040, /* Receive FIFO Overflow */
  77. Tdu = 0x0080, /* Transmit Descriptor Unavailable */
  78. Swint = 0x0100, /* Software Interrupt */
  79. Timeout = 0x4000, /* Timer */
  80. Serr = 0x8000, /* System Error */
  81. };
  82. enum { /* Tcr */
  83. MtxdmaSHIFT = 8, /* Max. DMA Burst Size */
  84. MtxdmaMASK = 0x00000700,
  85. Mtxdmaunlimited = 0x00000700,
  86. Acrc = 0x00010000, /* Append CRC (not) */
  87. Lbk0 = 0x00020000, /* Loopback Test 0 */
  88. Lbk1 = 0x00040000, /* Loopback Test 1 */
  89. Ifg2 = 0x00080000, /* Interframe Gap 2 */
  90. HwveridSHIFT = 23, /* Hardware Version ID */
  91. HwveridMASK = 0x7C800000,
  92. Macv01 = 0x00000000, /* RTL8169 */
  93. Macv02 = 0x00800000, /* RTL8169S/8110S */
  94. Macv03 = 0x04000000, /* RTL8169S/8110S */
  95. Macv04 = 0x10000000, /* RTL8169SB/8110SB */
  96. Macv05 = 0x18000000, /* RTL8169SC/8110SC */
  97. Macv11 = 0x30000000, /* RTL8168B/8111B */
  98. Macv12 = 0x38000000, /* RTL8169B/8111B */
  99. Macv13 = 0x34000000, /* RTL8101E */
  100. Macv14 = 0x30800000, /* RTL8100E */
  101. Macv15 = 0x38800000, /* RTL8100E */
  102. Ifg0 = 0x01000000, /* Interframe Gap 0 */
  103. Ifg1 = 0x02000000, /* Interframe Gap 1 */
  104. };
  105. enum { /* Rcr */
  106. Aap = 0x00000001, /* Accept All Packets */
  107. Apm = 0x00000002, /* Accept Physical Match */
  108. Am = 0x00000004, /* Accept Multicast */
  109. Ab = 0x00000008, /* Accept Broadcast */
  110. Ar = 0x00000010, /* Accept Runt */
  111. Aer = 0x00000020, /* Accept Error */
  112. Sel9356 = 0x00000040, /* 9356 EEPROM used */
  113. MrxdmaSHIFT = 8, /* Max. DMA Burst Size */
  114. MrxdmaMASK = 0x00000700,
  115. Mrxdmaunlimited = 0x00000700,
  116. RxfthSHIFT = 13, /* Receive Buffer Length */
  117. RxfthMASK = 0x0000E000,
  118. Rxfth256 = 0x00008000,
  119. Rxfthnone = 0x0000E000,
  120. Rer8 = 0x00010000, /* Accept Error Packets > 8 bytes */
  121. MulERINT = 0x01000000, /* Multiple Early Interrupt Select */
  122. };
  123. enum { /* Cr9346 */
  124. Eedo = 0x01, /* */
  125. Eedi = 0x02, /* */
  126. Eesk = 0x04, /* */
  127. Eecs = 0x08, /* */
  128. Eem0 = 0x40, /* Operating Mode */
  129. Eem1 = 0x80,
  130. };
  131. enum { /* Phyar */
  132. DataMASK = 0x0000FFFF, /* 16-bit GMII/MII Register Data */
  133. DataSHIFT = 0,
  134. RegaddrMASK = 0x001F0000, /* 5-bit GMII/MII Register Address */
  135. RegaddrSHIFT = 16,
  136. Flag = 0x80000000, /* */
  137. };
  138. enum { /* Phystatus */
  139. Fd = 0x01, /* Full Duplex */
  140. Linksts = 0x02, /* Link Status */
  141. Speed10 = 0x04, /* */
  142. Speed100 = 0x08, /* */
  143. Speed1000 = 0x10, /* */
  144. Rxflow = 0x20, /* */
  145. Txflow = 0x40, /* */
  146. Entbi = 0x80, /* */
  147. };
  148. enum { /* Cplusc */
  149. Mulrw = 0x0008, /* PCI Multiple R/W Enable */
  150. Dac = 0x0010, /* PCI Dual Address Cycle Enable */
  151. Rxchksum = 0x0020, /* Receive Checksum Offload Enable */
  152. Rxvlan = 0x0040, /* Receive VLAN De-tagging Enable */
  153. Endian = 0x0200, /* Endian Mode */
  154. };
  155. typedef struct D D; /* Transmit/Receive Descriptor */
  156. struct D {
  157. u32int control;
  158. u32int vlan;
  159. u32int addrlo;
  160. u32int addrhi;
  161. };
  162. enum { /* Transmit Descriptor control */
  163. TxflMASK = 0x0000FFFF, /* Transmit Frame Length */
  164. TxflSHIFT = 0,
  165. Tcps = 0x00010000, /* TCP Checksum Offload */
  166. Udpcs = 0x00020000, /* UDP Checksum Offload */
  167. Ipcs = 0x00040000, /* IP Checksum Offload */
  168. Lgsen = 0x08000000, /* Large Send */
  169. };
  170. enum { /* Receive Descriptor control */
  171. RxflMASK = 0x00003FFF, /* Receive Frame Length */
  172. RxflSHIFT = 0,
  173. Tcpf = 0x00004000, /* TCP Checksum Failure */
  174. Udpf = 0x00008000, /* UDP Checksum Failure */
  175. Ipf = 0x00010000, /* IP Checksum Failure */
  176. Pid0 = 0x00020000, /* Protocol ID0 */
  177. Pid1 = 0x00040000, /* Protocol ID1 */
  178. Crce = 0x00080000, /* CRC Error */
  179. Runt = 0x00100000, /* Runt Packet */
  180. Res = 0x00200000, /* Receive Error Summary */
  181. Rwt = 0x00400000, /* Receive Watchdog Timer Expired */
  182. Fovf = 0x00800000, /* FIFO Overflow */
  183. Bovf = 0x01000000, /* Buffer Overflow */
  184. Bar = 0x02000000, /* Broadcast Address Received */
  185. Pam = 0x04000000, /* Physical Address Matched */
  186. Mar = 0x08000000, /* Multicast Address Received */
  187. };
  188. enum { /* General Descriptor control */
  189. Ls = 0x10000000, /* Last Segment Descriptor */
  190. Fs = 0x20000000, /* First Segment Descriptor */
  191. Eor = 0x40000000, /* End of Descriptor Ring */
  192. Own = 0x80000000, /* Ownership */
  193. };
  194. /*
  195. */
  196. enum { /* Ring sizes (<= 1024) */
  197. Ntd = 32, /* Transmit Ring */
  198. Nrd = 128, /* Receive Ring */
  199. Mps = ROUNDUP(ETHERMAXTU+4, 128),
  200. };
  201. typedef struct Dtcc Dtcc;
  202. struct Dtcc {
  203. u64int txok;
  204. u64int rxok;
  205. u64int txer;
  206. u32int rxer;
  207. u16int misspkt;
  208. u16int fae;
  209. u32int tx1col;
  210. u32int txmcol;
  211. u64int rxokph;
  212. u64int rxokbrd;
  213. u32int rxokmu;
  214. u16int txabt;
  215. u16int txundrn;
  216. };
  217. enum { /* Variants */
  218. Rtl8100e = (0x8136<<16)|0x10EC, /* RTL810[01]E: pci -e */
  219. Rtl8169c = (0x0116<<16)|0x16EC, /* RTL8169C+ (USR997902) */
  220. Rtl8169sc = (0x8167<<16)|0x10EC, /* RTL8169SC */
  221. Rtl8168b = (0x8168<<16)|0x10EC, /* RTL8168B: pci-e */
  222. Rtl8169 = (0x8169<<16)|0x10EC, /* RTL8169 */
  223. };
  224. typedef struct Ctlr Ctlr;
  225. typedef struct Ctlr {
  226. int port;
  227. Pcidev* pcidev;
  228. Ctlr* next;
  229. int active;
  230. QLock alock; /* attach */
  231. Lock ilock; /* init */
  232. int init; /* */
  233. int pciv; /* */
  234. int macv; /* MAC version */
  235. int phyv; /* PHY version */
  236. int pcie; /* flag: pci-express device? */
  237. uvlong mchash; /* multicast hash */
  238. Mii* mii;
  239. Lock tlock; /* transmit */
  240. D* td; /* descriptor ring */
  241. Block** tb; /* transmit buffers */
  242. int ntd;
  243. int tdh; /* head - producer index (host) */
  244. int tdt; /* tail - consumer index (NIC) */
  245. int ntdfree;
  246. int ntq;
  247. int mtps; /* Max. Transmit Packet Size */
  248. Lock rlock; /* receive */
  249. D* rd; /* descriptor ring */
  250. Block** rb; /* receive buffers */
  251. int nrd;
  252. int rdh; /* head - producer index (NIC) */
  253. int rdt; /* tail - consumer index (host) */
  254. int nrdfree;
  255. int tcr; /* transmit configuration register */
  256. int rcr; /* receive configuration register */
  257. int imr;
  258. QLock slock; /* statistics */
  259. Dtcc* dtcc;
  260. uint txdu;
  261. uint tcpf;
  262. uint udpf;
  263. uint ipf;
  264. uint fovf;
  265. uint ierrs;
  266. uint rer;
  267. uint rdu;
  268. uint punlc;
  269. uint fovw;
  270. uint mcast;
  271. } Ctlr;
  272. static Ctlr* rtl8169ctlrhead;
  273. static Ctlr* rtl8169ctlrtail;
  274. #define csr8r(c, r) (inb((c)->port+(r)))
  275. #define csr16r(c, r) (ins((c)->port+(r)))
  276. #define csr32r(c, r) (inl((c)->port+(r)))
  277. #define csr8w(c, r, b) (outb((c)->port+(r), (u8int)(b)))
  278. #define csr16w(c, r, w) (outs((c)->port+(r), (u16int)(w)))
  279. #define csr32w(c, r, l) (outl((c)->port+(r), (u32int)(l)))
  280. static int
  281. rtl8169miimir(Mii* mii, int pa, int ra)
  282. {
  283. uint r;
  284. int timeo;
  285. Ctlr *ctlr;
  286. if(pa != 1)
  287. return -1;
  288. ctlr = mii->ctlr;
  289. r = (ra<<16) & RegaddrMASK;
  290. csr32w(ctlr, Phyar, r);
  291. delay(1);
  292. for(timeo = 0; timeo < 2000; timeo++){
  293. if((r = csr32r(ctlr, Phyar)) & Flag)
  294. break;
  295. microdelay(100);
  296. }
  297. if(!(r & Flag))
  298. return -1;
  299. return (r & DataMASK)>>DataSHIFT;
  300. }
  301. static int
  302. rtl8169miimiw(Mii* mii, int pa, int ra, int data)
  303. {
  304. uint r;
  305. int timeo;
  306. Ctlr *ctlr;
  307. if(pa != 1)
  308. return -1;
  309. ctlr = mii->ctlr;
  310. r = Flag|((ra<<16) & RegaddrMASK)|((data<<DataSHIFT) & DataMASK);
  311. csr32w(ctlr, Phyar, r);
  312. delay(1);
  313. for(timeo = 0; timeo < 2000; timeo++){
  314. if(!((r = csr32r(ctlr, Phyar)) & Flag))
  315. break;
  316. microdelay(100);
  317. }
  318. if(r & Flag)
  319. return -1;
  320. return 0;
  321. }
  322. static int
  323. rtl8169mii(Ctlr* ctlr)
  324. {
  325. MiiPhy *phy;
  326. /*
  327. * Link management.
  328. */
  329. if((ctlr->mii = malloc(sizeof(Mii))) == nil)
  330. return -1;
  331. ctlr->mii->mir = rtl8169miimir;
  332. ctlr->mii->miw = rtl8169miimiw;
  333. ctlr->mii->ctlr = ctlr;
  334. /*
  335. * Get rev number out of Phyidr2 so can config properly.
  336. * There's probably more special stuff for Macv0[234] needed here.
  337. */
  338. ctlr->phyv = rtl8169miimir(ctlr->mii, 1, Phyidr2) & 0x0F;
  339. if(ctlr->macv == Macv02){
  340. csr8w(ctlr, 0x82, 1); /* magic */
  341. rtl8169miimiw(ctlr->mii, 1, 0x0B, 0x0000); /* magic */
  342. }
  343. if(mii(ctlr->mii, (1<<1)) == 0 || (phy = ctlr->mii->curphy) == nil){
  344. free(ctlr->mii);
  345. ctlr->mii = nil;
  346. return -1;
  347. }
  348. print("oui %#ux phyno %d, macv = %#8.8ux phyv = %#4.4ux\n",
  349. phy->oui, phy->phyno, ctlr->macv, ctlr->phyv);
  350. miiane(ctlr->mii, ~0, ~0, ~0);
  351. return 0;
  352. }
  353. static void
  354. rtl8169promiscuous(void* arg, int on)
  355. {
  356. Ether *edev;
  357. Ctlr * ctlr;
  358. edev = arg;
  359. ctlr = edev->ctlr;
  360. ilock(&ctlr->ilock);
  361. if(on)
  362. ctlr->rcr |= Aap;
  363. else
  364. ctlr->rcr &= ~Aap;
  365. csr32w(ctlr, Rcr, ctlr->rcr);
  366. iunlock(&ctlr->ilock);
  367. }
  368. enum {
  369. /* everyone else uses 0x04c11db7, but they both produce the same crc */
  370. Etherpolybe = 0x04c11db6,
  371. Bytemask = (1<<8) - 1,
  372. };
  373. static ulong
  374. ethercrcbe(uchar *addr, long len)
  375. {
  376. int i, j;
  377. ulong c, crc, carry;
  378. crc = ~0UL;
  379. for (i = 0; i < len; i++) {
  380. c = addr[i];
  381. for (j = 0; j < 8; j++) {
  382. carry = ((crc & (1UL << 31))? 1: 0) ^ (c & 1);
  383. crc <<= 1;
  384. c >>= 1;
  385. if (carry)
  386. crc = (crc ^ Etherpolybe) | carry;
  387. }
  388. }
  389. return crc;
  390. }
  391. static ulong
  392. swabl(ulong l)
  393. {
  394. return l>>24 | (l>>8) & (Bytemask<<8) |
  395. (l<<8) & (Bytemask<<16) | l<<24;
  396. }
  397. static void
  398. rtl8169multicast(void* ether, uchar *eaddr, int add)
  399. {
  400. Ether *edev;
  401. Ctlr *ctlr;
  402. if (!add)
  403. return; /* ok to keep receiving on old mcast addrs */
  404. edev = ether;
  405. ctlr = edev->ctlr;
  406. ilock(&ctlr->ilock);
  407. ctlr->mchash |= 1ULL << (ethercrcbe(eaddr, Eaddrlen) >> 26);
  408. ctlr->rcr |= Am;
  409. csr32w(ctlr, Rcr, ctlr->rcr);
  410. /* pci-e variants reverse the order of the hash byte registers */
  411. if (ctlr->pcie) {
  412. csr32w(ctlr, Mar0, swabl(ctlr->mchash>>32));
  413. csr32w(ctlr, Mar0+4, swabl(ctlr->mchash));
  414. } else {
  415. csr32w(ctlr, Mar0, ctlr->mchash);
  416. csr32w(ctlr, Mar0+4, ctlr->mchash>>32);
  417. }
  418. iunlock(&ctlr->ilock);
  419. }
  420. static long
  421. rtl8169ifstat(Ether* edev, void* a, long n, ulong offset)
  422. {
  423. char *p;
  424. Ctlr *ctlr;
  425. Dtcc *dtcc;
  426. int i, l, r, timeo;
  427. ctlr = edev->ctlr;
  428. qlock(&ctlr->slock);
  429. p = nil;
  430. if(waserror()){
  431. qunlock(&ctlr->slock);
  432. free(p);
  433. nexterror();
  434. }
  435. csr32w(ctlr, Dtccr+4, 0);
  436. csr32w(ctlr, Dtccr, PCIWADDR(ctlr->dtcc)|Cmd);
  437. for(timeo = 0; timeo < 1000; timeo++){
  438. if(!(csr32r(ctlr, Dtccr) & Cmd))
  439. break;
  440. delay(1);
  441. }
  442. if(csr32r(ctlr, Dtccr) & Cmd)
  443. error(Eio);
  444. dtcc = ctlr->dtcc;
  445. edev->oerrs = dtcc->txer;
  446. edev->crcs = dtcc->rxer;
  447. edev->frames = dtcc->fae;
  448. edev->buffs = dtcc->misspkt;
  449. edev->overflows = ctlr->txdu+ctlr->rdu;
  450. if(n == 0){
  451. qunlock(&ctlr->slock);
  452. poperror();
  453. return 0;
  454. }
  455. if((p = malloc(READSTR)) == nil)
  456. error(Enomem);
  457. l = snprint(p, READSTR, "TxOk: %llud\n", dtcc->txok);
  458. l += snprint(p+l, READSTR-l, "RxOk: %llud\n", dtcc->rxok);
  459. l += snprint(p+l, READSTR-l, "TxEr: %llud\n", dtcc->txer);
  460. l += snprint(p+l, READSTR-l, "RxEr: %ud\n", dtcc->rxer);
  461. l += snprint(p+l, READSTR-l, "MissPkt: %ud\n", dtcc->misspkt);
  462. l += snprint(p+l, READSTR-l, "FAE: %ud\n", dtcc->fae);
  463. l += snprint(p+l, READSTR-l, "Tx1Col: %ud\n", dtcc->tx1col);
  464. l += snprint(p+l, READSTR-l, "TxMCol: %ud\n", dtcc->txmcol);
  465. l += snprint(p+l, READSTR-l, "RxOkPh: %llud\n", dtcc->rxokph);
  466. l += snprint(p+l, READSTR-l, "RxOkBrd: %llud\n", dtcc->rxokbrd);
  467. l += snprint(p+l, READSTR-l, "RxOkMu: %ud\n", dtcc->rxokmu);
  468. l += snprint(p+l, READSTR-l, "TxAbt: %ud\n", dtcc->txabt);
  469. l += snprint(p+l, READSTR-l, "TxUndrn: %ud\n", dtcc->txundrn);
  470. l += snprint(p+l, READSTR-l, "txdu: %ud\n", ctlr->txdu);
  471. l += snprint(p+l, READSTR-l, "tcpf: %ud\n", ctlr->tcpf);
  472. l += snprint(p+l, READSTR-l, "udpf: %ud\n", ctlr->udpf);
  473. l += snprint(p+l, READSTR-l, "ipf: %ud\n", ctlr->ipf);
  474. l += snprint(p+l, READSTR-l, "fovf: %ud\n", ctlr->fovf);
  475. l += snprint(p+l, READSTR-l, "ierrs: %ud\n", ctlr->ierrs);
  476. l += snprint(p+l, READSTR-l, "rer: %ud\n", ctlr->rer);
  477. l += snprint(p+l, READSTR-l, "rdu: %ud\n", ctlr->rdu);
  478. l += snprint(p+l, READSTR-l, "punlc: %ud\n", ctlr->punlc);
  479. l += snprint(p+l, READSTR-l, "fovw: %ud\n", ctlr->fovw);
  480. l += snprint(p+l, READSTR-l, "tcr: %#8.8ux\n", ctlr->tcr);
  481. l += snprint(p+l, READSTR-l, "rcr: %#8.8ux\n", ctlr->rcr);
  482. l += snprint(p+l, READSTR-l, "multicast: %ud\n", ctlr->mcast);
  483. if(ctlr->mii != nil && ctlr->mii->curphy != nil){
  484. l += snprint(p+l, READSTR, "phy: ");
  485. for(i = 0; i < NMiiPhyr; i++){
  486. if(i && ((i & 0x07) == 0))
  487. l += snprint(p+l, READSTR-l, "\n ");
  488. r = miimir(ctlr->mii, i);
  489. l += snprint(p+l, READSTR-l, " %4.4ux", r);
  490. }
  491. snprint(p+l, READSTR-l, "\n");
  492. }
  493. n = readstr(offset, a, n, p);
  494. qunlock(&ctlr->slock);
  495. poperror();
  496. free(p);
  497. return n;
  498. }
  499. static void
  500. rtl8169halt(Ctlr* ctlr)
  501. {
  502. csr8w(ctlr, Cr, 0);
  503. csr16w(ctlr, Imr, 0);
  504. csr16w(ctlr, Isr, ~0);
  505. }
  506. static int
  507. rtl8169reset(Ctlr* ctlr)
  508. {
  509. u32int r;
  510. int timeo;
  511. /*
  512. * Soft reset the controller.
  513. */
  514. csr8w(ctlr, Cr, Rst);
  515. for(r = timeo = 0; timeo < 1000; timeo++){
  516. r = csr8r(ctlr, Cr);
  517. if(!(r & Rst))
  518. break;
  519. delay(1);
  520. }
  521. rtl8169halt(ctlr);
  522. if(r & Rst)
  523. return -1;
  524. return 0;
  525. }
  526. static void
  527. rtl8169replenish(Ctlr* ctlr)
  528. {
  529. D *d;
  530. int rdt;
  531. Block *bp;
  532. rdt = ctlr->rdt;
  533. while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
  534. d = &ctlr->rd[rdt];
  535. if(ctlr->rb[rdt] == nil){
  536. /*
  537. * Simple allocation for now.
  538. * This better be aligned on 8.
  539. */
  540. bp = iallocb(Mps);
  541. if(bp == nil){
  542. iprint("no available buffers\n");
  543. break;
  544. }
  545. ctlr->rb[rdt] = bp;
  546. d->addrlo = PCIWADDR(bp->rp);
  547. d->addrhi = 0;
  548. }
  549. coherence();
  550. d->control |= Own|Mps;
  551. rdt = NEXT(rdt, ctlr->nrd);
  552. ctlr->nrdfree++;
  553. }
  554. ctlr->rdt = rdt;
  555. }
  556. static int
  557. rtl8169init(Ether* edev)
  558. {
  559. int i;
  560. u32int r;
  561. Block *bp;
  562. Ctlr *ctlr;
  563. u8int cplusc;
  564. ctlr = edev->ctlr;
  565. ilock(&ctlr->ilock);
  566. rtl8169halt(ctlr);
  567. /*
  568. * MAC Address.
  569. * Must put chip into config register write enable mode.
  570. */
  571. csr8w(ctlr, Cr9346, Eem1|Eem0);
  572. r = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
  573. csr32w(ctlr, Idr0, r);
  574. r = (edev->ea[5]<<8)|edev->ea[4];
  575. csr32w(ctlr, Idr0+4, r);
  576. /*
  577. * Transmitter.
  578. */
  579. memset(ctlr->td, 0, sizeof(D)*ctlr->ntd);
  580. ctlr->tdh = ctlr->tdt = 0;
  581. ctlr->td[ctlr->ntd-1].control = Eor;
  582. /*
  583. * Receiver.
  584. * Need to do something here about the multicast filter.
  585. */
  586. memset(ctlr->rd, 0, sizeof(D)*ctlr->nrd);
  587. ctlr->nrdfree = ctlr->rdh = ctlr->rdt = 0;
  588. ctlr->rd[ctlr->nrd-1].control = Eor;
  589. for(i = 0; i < ctlr->nrd; i++){
  590. if((bp = ctlr->rb[i]) != nil){
  591. ctlr->rb[i] = nil;
  592. freeb(bp);
  593. }
  594. }
  595. rtl8169replenish(ctlr);
  596. ctlr->rcr = Rxfthnone|Mrxdmaunlimited|Ab|Am|Apm;
  597. /*
  598. * Mtps is in units of 128 except for the RTL8169
  599. * where is is 32. If using jumbo frames should be
  600. * set to 0x3F.
  601. * Setting Mulrw in Cplusc disables the Tx/Rx DMA burst
  602. * settings in Tcr/Rcr; the (1<<14) is magic.
  603. */
  604. ctlr->mtps = HOWMANY(Mps, 128);
  605. cplusc = csr16r(ctlr, Cplusc) & ~(1<<14);
  606. cplusc |= /*Rxchksum|*/Mulrw;
  607. switch(ctlr->macv){
  608. default:
  609. return -1;
  610. case Macv01:
  611. ctlr->mtps = HOWMANY(Mps, 32);
  612. break;
  613. case Macv02:
  614. case Macv03:
  615. cplusc |= (1<<14); /* magic */
  616. break;
  617. case Macv05:
  618. /*
  619. * This is interpreted from clearly bogus code
  620. * in the manufacturer-supplied driver, it could
  621. * be wrong. Untested.
  622. */
  623. r = csr8r(ctlr, Config2) & 0x07;
  624. if(r == 0x01) /* 66MHz PCI */
  625. csr32w(ctlr, 0x7C, 0x0007FFFF); /* magic */
  626. else
  627. csr32w(ctlr, 0x7C, 0x0007FF00); /* magic */
  628. pciclrmwi(ctlr->pcidev);
  629. break;
  630. case Macv13:
  631. /*
  632. * This is interpreted from clearly bogus code
  633. * in the manufacturer-supplied driver, it could
  634. * be wrong. Untested.
  635. */
  636. pcicfgw8(ctlr->pcidev, 0x68, 0x00); /* magic */
  637. pcicfgw8(ctlr->pcidev, 0x69, 0x08); /* magic */
  638. break;
  639. case Macv04:
  640. case Macv11:
  641. case Macv12:
  642. case Macv14:
  643. case Macv15:
  644. break;
  645. }
  646. /*
  647. * Enable receiver/transmitter.
  648. * Need to do this first or some of the settings below
  649. * won't take.
  650. */
  651. switch(ctlr->pciv){
  652. default:
  653. csr8w(ctlr, Cr, Te|Re);
  654. csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
  655. csr32w(ctlr, Rcr, ctlr->rcr);
  656. csr32w(ctlr, Mar0, 0);
  657. csr32w(ctlr, Mar0+4, 0);
  658. ctlr->mchash = 0;
  659. case Rtl8169sc:
  660. case Rtl8168b:
  661. break;
  662. }
  663. /*
  664. * Interrupts.
  665. * Disable Tdu|Tok for now, the transmit routine will tidy.
  666. * Tdu means the NIC ran out of descriptors to send, so it
  667. * doesn't really need to ever be on.
  668. */
  669. csr32w(ctlr, Timerint, 0);
  670. ctlr->imr = Serr|Timeout|Fovw|Punlc|Rdu|Ter|Rer|Rok;
  671. csr16w(ctlr, Imr, ctlr->imr);
  672. /*
  673. * Clear missed-packet counter;
  674. * initial early transmit threshold value;
  675. * set the descriptor ring base addresses;
  676. * set the maximum receive packet size;
  677. * no early-receive interrupts.
  678. */
  679. csr32w(ctlr, Mpc, 0);
  680. csr8w(ctlr, Mtps, ctlr->mtps);
  681. csr32w(ctlr, Tnpds+4, 0);
  682. csr32w(ctlr, Tnpds, PCIWADDR(ctlr->td));
  683. csr32w(ctlr, Rdsar+4, 0);
  684. csr32w(ctlr, Rdsar, PCIWADDR(ctlr->rd));
  685. csr16w(ctlr, Rms, Mps);
  686. r = csr16r(ctlr, Mulint) & 0xF000;
  687. csr16w(ctlr, Mulint, r);
  688. csr16w(ctlr, Cplusc, cplusc);
  689. /*
  690. * Set configuration.
  691. */
  692. switch(ctlr->pciv){
  693. default:
  694. break;
  695. case Rtl8169sc:
  696. csr16w(ctlr, 0xE2, 0); /* magic */
  697. csr8w(ctlr, Cr, Te|Re);
  698. csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
  699. csr32w(ctlr, Rcr, ctlr->rcr);
  700. break;
  701. case Rtl8168b:
  702. case Rtl8169c:
  703. csr16w(ctlr, 0xE2, 0); /* magic */
  704. csr16w(ctlr, Cplusc, 0x2000); /* magic */
  705. csr8w(ctlr, Cr, Te|Re);
  706. csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
  707. csr32w(ctlr, Rcr, ctlr->rcr);
  708. csr16w(ctlr, Rms, 0x0800);
  709. csr8w(ctlr, Mtps, 0x3F);
  710. break;
  711. }
  712. ctlr->tcr = csr32r(ctlr, Tcr);
  713. csr8w(ctlr, Cr9346, 0);
  714. iunlock(&ctlr->ilock);
  715. // rtl8169mii(ctlr);
  716. return 0;
  717. }
  718. static void
  719. rtl8169attach(Ether* edev)
  720. {
  721. int timeo;
  722. Ctlr *ctlr;
  723. ctlr = edev->ctlr;
  724. qlock(&ctlr->alock);
  725. if(ctlr->init == 0){
  726. /*
  727. * Handle allocation/init errors here.
  728. */
  729. ctlr->td = mallocalign(sizeof(D)*Ntd, 256, 0, 0);
  730. ctlr->tb = malloc(Ntd*sizeof(Block*));
  731. ctlr->ntd = Ntd;
  732. ctlr->rd = mallocalign(sizeof(D)*Nrd, 256, 0, 0);
  733. ctlr->rb = malloc(Nrd*sizeof(Block*));
  734. ctlr->nrd = Nrd;
  735. ctlr->dtcc = mallocalign(sizeof(Dtcc), 64, 0, 0);
  736. rtl8169init(edev);
  737. ctlr->init = 1;
  738. }
  739. qunlock(&ctlr->alock);
  740. /*
  741. * Wait for link to be ready.
  742. */
  743. for(timeo = 0; timeo < 35; timeo++){
  744. if(miistatus(ctlr->mii) == 0)
  745. break;
  746. delay(100); /* print fewer miistatus messages */
  747. }
  748. }
  749. static void
  750. rtl8169link(Ether* edev)
  751. {
  752. uint r;
  753. int limit;
  754. Ctlr *ctlr;
  755. ctlr = edev->ctlr;
  756. /*
  757. * Maybe the link changed - do we care very much?
  758. * Could stall transmits if no link, maybe?
  759. */
  760. if(!((r = csr8r(ctlr, Phystatus)) & Linksts)){
  761. edev->link = 0;
  762. return;
  763. }
  764. edev->link = 1;
  765. limit = 256*1024;
  766. if(r & Speed10){
  767. edev->mbps = 10;
  768. limit = 65*1024;
  769. } else if(r & Speed100)
  770. edev->mbps = 100;
  771. else if(r & Speed1000)
  772. edev->mbps = 1000;
  773. if(edev->oq != nil)
  774. qsetlimit(edev->oq, limit);
  775. }
  776. static void
  777. rtl8169transmit(Ether* edev)
  778. {
  779. D *d;
  780. Block *bp;
  781. Ctlr *ctlr;
  782. int control, x;
  783. ctlr = edev->ctlr;
  784. ilock(&ctlr->tlock);
  785. for(x = ctlr->tdh; ctlr->ntq > 0; x = NEXT(x, ctlr->ntd)){
  786. d = &ctlr->td[x];
  787. if((control = d->control) & Own)
  788. break;
  789. /*
  790. * Check errors and log here.
  791. */
  792. USED(control);
  793. /*
  794. * Free it up.
  795. * Need to clean the descriptor here? Not really.
  796. * Simple freeb for now (no chain and freeblist).
  797. * Use ntq count for now.
  798. */
  799. freeb(ctlr->tb[x]);
  800. ctlr->tb[x] = nil;
  801. d->control &= Eor;
  802. ctlr->ntq--;
  803. }
  804. ctlr->tdh = x;
  805. x = ctlr->tdt;
  806. while(ctlr->ntq < (ctlr->ntd-1)){
  807. if((bp = qget(edev->oq)) == nil)
  808. break;
  809. d = &ctlr->td[x];
  810. d->addrlo = PCIWADDR(bp->rp);
  811. d->addrhi = 0;
  812. ctlr->tb[x] = bp;
  813. coherence();
  814. d->control |= Own|Fs|Ls|((BLEN(bp)<<TxflSHIFT) & TxflMASK);
  815. x = NEXT(x, ctlr->ntd);
  816. ctlr->ntq++;
  817. }
  818. if(x != ctlr->tdt){
  819. ctlr->tdt = x;
  820. csr8w(ctlr, Tppoll, Npq);
  821. }
  822. else if(ctlr->ntq >= (ctlr->ntd-1))
  823. ctlr->txdu++;
  824. iunlock(&ctlr->tlock);
  825. }
  826. static void
  827. rtl8169receive(Ether* edev)
  828. {
  829. D *d;
  830. int rdh;
  831. Block *bp;
  832. Ctlr *ctlr;
  833. u32int control;
  834. ctlr = edev->ctlr;
  835. rdh = ctlr->rdh;
  836. for(;;){
  837. d = &ctlr->rd[rdh];
  838. if(d->control & Own)
  839. break;
  840. control = d->control;
  841. if((control & (Fs|Ls|Res)) == (Fs|Ls)){
  842. bp = ctlr->rb[rdh];
  843. ctlr->rb[rdh] = nil;
  844. bp->wp = bp->rp + ((control & RxflMASK)>>RxflSHIFT)-4;
  845. bp->next = nil;
  846. if(control & Fovf)
  847. ctlr->fovf++;
  848. if(control & Mar)
  849. ctlr->mcast++;
  850. switch(control & (Pid1|Pid0)){
  851. default:
  852. break;
  853. case Pid0:
  854. if(control & Tcpf){
  855. ctlr->tcpf++;
  856. break;
  857. }
  858. bp->flag |= Btcpck;
  859. break;
  860. case Pid1:
  861. if(control & Udpf){
  862. ctlr->udpf++;
  863. break;
  864. }
  865. bp->flag |= Budpck;
  866. break;
  867. case Pid1|Pid0:
  868. if(control & Ipf){
  869. ctlr->ipf++;
  870. break;
  871. }
  872. bp->flag |= Bipck;
  873. break;
  874. }
  875. etheriq(edev, bp, 1);
  876. }
  877. else{
  878. /*
  879. * Error stuff here.
  880. print("control %#8.8ux\n", control);
  881. */
  882. }
  883. d->control &= Eor;
  884. ctlr->nrdfree--;
  885. rdh = NEXT(rdh, ctlr->nrd);
  886. if(ctlr->nrdfree < ctlr->nrd/2)
  887. rtl8169replenish(ctlr);
  888. }
  889. ctlr->rdh = rdh;
  890. }
  891. static void
  892. rtl8169interrupt(Ureg*, void* arg)
  893. {
  894. Ctlr *ctlr;
  895. Ether *edev;
  896. u32int isr;
  897. edev = arg;
  898. ctlr = edev->ctlr;
  899. while((isr = csr16r(ctlr, Isr)) != 0 && isr != 0xFFFF){
  900. csr16w(ctlr, Isr, isr);
  901. if((isr & ctlr->imr) == 0)
  902. break;
  903. if(isr & (Fovw|Punlc|Rdu|Rer|Rok)){
  904. rtl8169receive(edev);
  905. if(!(isr & (Punlc|Rok)))
  906. ctlr->ierrs++;
  907. if(isr & Rer)
  908. ctlr->rer++;
  909. if(isr & Rdu)
  910. ctlr->rdu++;
  911. if(isr & Punlc)
  912. ctlr->punlc++;
  913. if(isr & Fovw)
  914. ctlr->fovw++;
  915. isr &= ~(Fovw|Rdu|Rer|Rok);
  916. }
  917. if(isr & (Tdu|Ter|Tok)){
  918. rtl8169transmit(edev);
  919. isr &= ~(Tdu|Ter|Tok);
  920. }
  921. if(isr & Punlc){
  922. rtl8169link(edev);
  923. isr &= ~Punlc;
  924. }
  925. /*
  926. * Some of the reserved bits get set sometimes...
  927. */
  928. if(isr & (Serr|Timeout|Tdu|Fovw|Punlc|Rdu|Ter|Tok|Rer|Rok))
  929. panic("rtl8169interrupt: imr %#4.4ux isr %#4.4ux\n",
  930. csr16r(ctlr, Imr), isr);
  931. }
  932. }
  933. static void
  934. rtl8169pci(void)
  935. {
  936. Pcidev *p;
  937. Ctlr *ctlr;
  938. int i, port, pcie;
  939. p = nil;
  940. while(p = pcimatch(p, 0, 0)){
  941. if(p->ccrb != 0x02 || p->ccru != 0)
  942. continue;
  943. pcie = 0;
  944. switch(i = ((p->did<<16)|p->vid)){
  945. default:
  946. continue;
  947. case Rtl8100e: /* RTL810[01]E ? */
  948. case Rtl8168b: /* RTL8168B */
  949. pcie = 1;
  950. break;
  951. case Rtl8169c: /* RTL8169C */
  952. case Rtl8169sc: /* RTL8169SC */
  953. case Rtl8169: /* RTL8169 */
  954. break;
  955. case (0xC107<<16)|0x1259: /* Corega CG-LAPCIGT */
  956. i = Rtl8169;
  957. break;
  958. }
  959. port = p->mem[0].bar & ~0x01;
  960. if(ioalloc(port, p->mem[0].size, 0, "rtl8169") < 0){
  961. print("rtl8169: port %#ux in use\n", port);
  962. continue;
  963. }
  964. ctlr = malloc(sizeof(Ctlr));
  965. ctlr->port = port;
  966. ctlr->pcidev = p;
  967. ctlr->pciv = i;
  968. ctlr->pcie = pcie;
  969. if(pcigetpms(p) > 0){
  970. pcisetpms(p, 0);
  971. for(i = 0; i < 6; i++)
  972. pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
  973. pcicfgw8(p, PciINTL, p->intl);
  974. pcicfgw8(p, PciLTR, p->ltr);
  975. pcicfgw8(p, PciCLS, p->cls);
  976. pcicfgw16(p, PciPCR, p->pcr);
  977. }
  978. if(rtl8169reset(ctlr)){
  979. iofree(port);
  980. free(ctlr);
  981. continue;
  982. }
  983. /*
  984. * Extract the chip hardware version,
  985. * needed to configure each properly.
  986. */
  987. ctlr->macv = csr32r(ctlr, Tcr) & HwveridMASK;
  988. rtl8169mii(ctlr);
  989. pcisetbme(p);
  990. if(rtl8169ctlrhead != nil)
  991. rtl8169ctlrtail->next = ctlr;
  992. else
  993. rtl8169ctlrhead = ctlr;
  994. rtl8169ctlrtail = ctlr;
  995. }
  996. }
  997. static int
  998. rtl8169pnp(Ether* edev)
  999. {
  1000. u32int r;
  1001. Ctlr *ctlr;
  1002. uchar ea[Eaddrlen];
  1003. if(rtl8169ctlrhead == nil)
  1004. rtl8169pci();
  1005. /*
  1006. * Any adapter matches if no edev->port is supplied,
  1007. * otherwise the ports must match.
  1008. */
  1009. for(ctlr = rtl8169ctlrhead; ctlr != nil; ctlr = ctlr->next){
  1010. if(ctlr->active)
  1011. continue;
  1012. if(edev->port == 0 || edev->port == ctlr->port){
  1013. ctlr->active = 1;
  1014. break;
  1015. }
  1016. }
  1017. if(ctlr == nil)
  1018. return -1;
  1019. edev->ctlr = ctlr;
  1020. edev->port = ctlr->port;
  1021. edev->irq = ctlr->pcidev->intl;
  1022. edev->tbdf = ctlr->pcidev->tbdf;
  1023. edev->mbps = 100;
  1024. /*
  1025. * Check if the adapter's station address is to be overridden.
  1026. * If not, read it from the device and set in edev->ea.
  1027. */
  1028. memset(ea, 0, Eaddrlen);
  1029. if(memcmp(ea, edev->ea, Eaddrlen) == 0){
  1030. r = csr32r(ctlr, Idr0);
  1031. edev->ea[0] = r;
  1032. edev->ea[1] = r>>8;
  1033. edev->ea[2] = r>>16;
  1034. edev->ea[3] = r>>24;
  1035. r = csr32r(ctlr, Idr0+4);
  1036. edev->ea[4] = r;
  1037. edev->ea[5] = r>>8;
  1038. }
  1039. edev->attach = rtl8169attach;
  1040. edev->transmit = rtl8169transmit;
  1041. edev->interrupt = rtl8169interrupt;
  1042. edev->ifstat = rtl8169ifstat;
  1043. edev->arg = edev;
  1044. edev->promiscuous = rtl8169promiscuous;
  1045. edev->multicast = rtl8169multicast;
  1046. // edev->shutdown = rtl8169shutdown;
  1047. rtl8169link(edev);
  1048. return 0;
  1049. }
  1050. void
  1051. ether8169link(void)
  1052. {
  1053. addethercard("rtl8169", rtl8169pnp);
  1054. }