ether83815.c 26 KB

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  1. /*
  2. * National Semiconductor DP83815
  3. *
  4. * Supports only internal PHY and has been tested on:
  5. * Netgear FA311TX (using Netgear DS108 10/100 hub)
  6. * To do:
  7. * check Ethernet address;
  8. * test autonegotiation on 10 Mbit, and 100 Mbit full duplex;
  9. * external PHY via MII (should be common code for MII);
  10. * thresholds;
  11. * ring sizing;
  12. * physical link changes/disconnect;
  13. * push initialisation back to attach.
  14. *
  15. * C H Forsyth, forsyth@vitanuova.com, 18th June 2001.
  16. */
  17. #include "u.h"
  18. #include "../port/lib.h"
  19. #include "mem.h"
  20. #include "dat.h"
  21. #include "fns.h"
  22. #include "io.h"
  23. #include "../port/error.h"
  24. #include "../port/netif.h"
  25. #include "etherif.h"
  26. #define DEBUG (0)
  27. #define debug if(DEBUG)print
  28. enum {
  29. Nrde = 64,
  30. Ntde = 64,
  31. };
  32. #define Rbsz ROUNDUP(sizeof(Etherpkt)+4, 4)
  33. typedef struct Des {
  34. ulong next;
  35. int cmdsts;
  36. ulong addr;
  37. Block* bp;
  38. } Des;
  39. enum { /* cmdsts */
  40. Own = 1<<31, /* set by data producer to hand to consumer */
  41. More = 1<<30, /* more of packet in next descriptor */
  42. Intr = 1<<29, /* interrupt when device is done with it */
  43. Supcrc = 1<<28, /* suppress crc on transmit */
  44. Inccrc = 1<<28, /* crc included on receive (always) */
  45. Ok = 1<<27, /* packet ok */
  46. Size = 0xFFF, /* packet size in bytes */
  47. /* transmit */
  48. Txa = 1<<26, /* transmission aborted */
  49. Tfu = 1<<25, /* transmit fifo underrun */
  50. Crs = 1<<24, /* carrier sense lost */
  51. Td = 1<<23, /* transmission deferred */
  52. Ed = 1<<22, /* excessive deferral */
  53. Owc = 1<<21, /* out of window collision */
  54. Ec = 1<<20, /* excessive collisions */
  55. /* 19-16 collision count */
  56. /* receive */
  57. Rxa = 1<<26, /* receive aborted (same as Rxo) */
  58. Rxo = 1<<25, /* receive overrun */
  59. Dest = 3<<23, /* destination class */
  60. Drej= 0<<23, /* packet was rejected */
  61. Duni= 1<<23, /* unicast */
  62. Dmulti= 2<<23, /* multicast */
  63. Dbroad= 3<<23, /* broadcast */
  64. Long = 1<<22, /* too long packet received */
  65. Runt = 1<<21, /* packet less than 64 bytes */
  66. Ise = 1<<20, /* invalid symbol */
  67. Crce = 1<<19, /* invalid crc */
  68. Fae = 1<<18, /* frame alignment error */
  69. Lbp = 1<<17, /* loopback packet */
  70. Col = 1<<16, /* collision during receive */
  71. };
  72. enum { /* PCI vendor & device IDs */
  73. Nat83815 = (0x0020<<16)|0x100B,
  74. SiS = 0x1039,
  75. SiS900 = (0x0900<<16)|SiS,
  76. SiS7016 = (0x7016<<16)|SiS,
  77. SiS630bridge = 0x0008,
  78. /* SiS 900 PCI revision codes */
  79. SiSrev630s = 0x81,
  80. SiSrev630e = 0x82,
  81. SiSrev630ea1 = 0x83,
  82. SiSeenodeaddr = 8, /* short addr of SiS eeprom mac addr */
  83. SiS630eenodeaddr = 9, /* likewise for the 630 */
  84. Nseenodeaddr = 6, /* " for NS eeprom */
  85. };
  86. typedef struct Ctlr Ctlr;
  87. typedef struct Ctlr {
  88. int port;
  89. Pcidev* pcidev;
  90. Ctlr* next;
  91. int active;
  92. int id; /* (pcidev->did<<16)|pcidev->vid */
  93. ushort srom[0xB+1];
  94. uchar sromea[Eaddrlen]; /* MAC address */
  95. uchar fd; /* option or auto negotiation */
  96. int mbps;
  97. Lock lock;
  98. Des* rdr; /* receive descriptor ring */
  99. int nrdr; /* size of rdr */
  100. int rdrx; /* index into rdr */
  101. Lock tlock;
  102. Des* tdr; /* transmit descriptor ring */
  103. int ntdr; /* size of tdr */
  104. int tdrh; /* host index into tdr */
  105. int tdri; /* interface index into tdr */
  106. int ntq; /* descriptors active */
  107. int ntqmax;
  108. ulong rxa; /* receive statistics */
  109. ulong rxo;
  110. ulong rlong;
  111. ulong runt;
  112. ulong ise;
  113. ulong crce;
  114. ulong fae;
  115. ulong lbp;
  116. ulong col;
  117. ulong rxsovr;
  118. ulong rxorn;
  119. ulong txa; /* transmit statistics */
  120. ulong tfu;
  121. ulong crs;
  122. ulong td;
  123. ulong ed;
  124. ulong owc;
  125. ulong ec;
  126. ulong txurn;
  127. ulong dperr; /* system errors */
  128. ulong rmabt;
  129. ulong rtabt;
  130. ulong sserr;
  131. ulong rxsover;
  132. } Ctlr;
  133. static Ctlr* ctlrhead;
  134. static Ctlr* ctlrtail;
  135. enum {
  136. /* registers (could memory map) */
  137. Rcr= 0x00, /* command register */
  138. Rst= 1<<8,
  139. Rxr= 1<<5, /* receiver reset */
  140. Txr= 1<<4, /* transmitter reset */
  141. Rxd= 1<<3, /* receiver disable */
  142. Rxe= 1<<2, /* receiver enable */
  143. Txd= 1<<1, /* transmitter disable */
  144. Txe= 1<<0, /* transmitter enable */
  145. Rcfg= 0x04, /* configuration */
  146. Lnksts= 1<<31, /* link good */
  147. Speed100= 1<<30, /* 100 Mb/s link */
  148. Fdup= 1<<29, /* full duplex */
  149. Pol= 1<<28, /* polarity reversal (10baseT) */
  150. Aneg_dn= 1<<27, /* autonegotiation done */
  151. Pint_acen= 1<<17, /* PHY interrupt auto clear enable */
  152. Pause_adv= 1<<16, /* advertise pause during auto neg */
  153. Paneg_ena= 1<<13, /* auto negotiation enable */
  154. Paneg_all= 7<<13, /* auto negotiation enable 10/100 half & full */
  155. Ext_phy= 1<<12, /* enable MII for external PHY */
  156. Phy_rst= 1<<10, /* reset internal PHY */
  157. Phy_dis= 1<<9, /* disable internal PHY (eg, low power) */
  158. Req_alg= 1<<7, /* PCI bus request: set means less aggressive */
  159. Sb= 1<<6, /* single slot back-off not random */
  160. Pow= 1<<5, /* out of window timer selection */
  161. Exd= 1<<4, /* disable excessive deferral timer */
  162. Pesel= 1<<3, /* parity error algorithm selection */
  163. Brom_dis= 1<<2, /* disable boot rom interface */
  164. Bem= 1<<0, /* big-endian mode */
  165. Rmear= 0x08, /* eeprom access */
  166. Mdc= 1<<6, /* MII mangement check */
  167. Mddir= 1<<5, /* MII management direction */
  168. Mdio= 1<<4, /* MII mangement data */
  169. Eesel= 1<<3, /* EEPROM chip select */
  170. Eeclk= 1<<2, /* EEPROM clock */
  171. Eedo= 1<<1, /* EEPROM data out (from chip) */
  172. Eedi= 1<<0, /* EEPROM data in (to chip) */
  173. Rptscr= 0x0C, /* pci test control */
  174. Risr= 0x10, /* interrupt status */
  175. Txrcmp= 1<<25, /* transmit reset complete */
  176. Rxrcmp= 1<<24, /* receiver reset complete */
  177. Dperr= 1<<23, /* detected parity error */
  178. Sserr= 1<<22, /* signalled system error */
  179. Rmabt= 1<<21, /* received master abort */
  180. Rtabt= 1<<20, /* received target abort */
  181. Rxsovr= 1<<16, /* RX status FIFO overrun */
  182. Hiberr= 1<<15, /* high bits error set (OR of 25-16) */
  183. Phy= 1<<14, /* PHY interrupt */
  184. Pme= 1<<13, /* power management event (wake online) */
  185. Swi= 1<<12, /* software interrupt */
  186. Mib= 1<<11, /* MIB service */
  187. Txurn= 1<<10, /* TX underrun */
  188. Txidle= 1<<9, /* TX idle */
  189. Txerr= 1<<8, /* TX packet error */
  190. Txdesc= 1<<7, /* TX descriptor (with Intr bit done) */
  191. Txok= 1<<6, /* TX ok */
  192. Rxorn= 1<<5, /* RX overrun */
  193. Rxidle= 1<<4, /* RX idle */
  194. Rxearly= 1<<3, /* RX early threshold */
  195. Rxerr= 1<<2, /* RX packet error */
  196. Rxdesc= 1<<1, /* RX descriptor (with Intr bit done) */
  197. Rxok= 1<<0, /* RX ok */
  198. Rimr= 0x14, /* interrupt mask */
  199. Rier= 0x18, /* interrupt enable */
  200. Ie= 1<<0, /* interrupt enable */
  201. Rtxdp= 0x20, /* transmit descriptor pointer */
  202. Rtxcfg= 0x24, /* transmit configuration */
  203. Csi= 1<<31, /* carrier sense ignore (needed for full duplex) */
  204. Hbi= 1<<30, /* heartbeat ignore (needed for full duplex) */
  205. Atp= 1<<28, /* automatic padding of runt packets */
  206. Mxdma= 7<<20, /* maximum dma transfer field */
  207. Mxdma32= 4<<20, /* 4x32-bit words (32 bytes) */
  208. Mxdma64= 5<<20, /* 8x32-bit words (64 bytes) */
  209. Flth= 0x3F<<8,/* Tx fill threshold, units of 32 bytes (must be > Mxdma) */
  210. Drth= 0x3F<<0,/* Tx drain threshold (units of 32 bytes) */
  211. Flth128= 4<<8, /* fill at 128 bytes */
  212. Drth512= 16<<0, /* drain at 512 bytes */
  213. Rrxdp= 0x30, /* receive descriptor pointer */
  214. Rrxcfg= 0x34, /* receive configuration */
  215. Atx= 1<<28, /* accept transmit packets (needed for full duplex) */
  216. Rdrth= 0x1F<<1,/* Rx drain threshold (units of 32 bytes) */
  217. Rdrth64= 2<<1, /* drain at 64 bytes */
  218. Rccsr= 0x3C, /* CLKRUN control/status */
  219. Pmests= 1<<15, /* PME status */
  220. Rwcsr= 0x40, /* wake on lan control/status */
  221. Rpcr= 0x44, /* pause control/status */
  222. Rrfcr= 0x48, /* receive filter/match control */
  223. Rfen= 1<<31, /* receive filter enable */
  224. Aab= 1<<30, /* accept all broadcast */
  225. Aam= 1<<29, /* accept all multicast */
  226. Aau= 1<<28, /* accept all unicast */
  227. Apm= 1<<27, /* accept on perfect match */
  228. Apat= 0xF<<23,/* accept on pattern match */
  229. Aarp= 1<<22, /* accept ARP */
  230. Mhen= 1<<21, /* multicast hash enable */
  231. Uhen= 1<<20, /* unicast hash enable */
  232. Ulm= 1<<19, /* U/L bit mask */
  233. /* bits 0-9 are rfaddr */
  234. Rrfdr= 0x4C, /* receive filter/match data */
  235. Rbrar= 0x50, /* boot rom address */
  236. Rbrdr= 0x54, /* boot rom data */
  237. Rsrr= 0x58, /* silicon revision */
  238. Rmibc= 0x5C, /* MIB control */
  239. /* 60-78 MIB data */
  240. /* PHY registers */
  241. Rbmcr= 0x80, /* basic mode configuration */
  242. Reset= 1<<15,
  243. Sel100= 1<<13, /* select 100Mb/sec if no auto neg */
  244. Anena= 1<<12, /* auto negotiation enable */
  245. Anrestart= 1<<9, /* restart auto negotiation */
  246. Selfdx= 1<<8, /* select full duplex if no auto neg */
  247. Rbmsr= 0x84, /* basic mode status */
  248. Ancomp= 1<<5, /* autonegotiation complete */
  249. Rphyidr1= 0x88,
  250. Rphyidr2= 0x8C,
  251. Ranar= 0x90, /* autonegotiation advertisement */
  252. Ranlpar= 0x94, /* autonegotiation link partner ability */
  253. Raner= 0x98, /* autonegotiation expansion */
  254. Rannptr= 0x9C, /* autonegotiation next page TX */
  255. Rphysts= 0xC0, /* PHY status */
  256. Rmicr= 0xC4, /* MII control */
  257. Inten= 1<<1, /* PHY interrupt enable */
  258. Rmisr= 0xC8, /* MII status */
  259. Rfcscr= 0xD0, /* false carrier sense counter */
  260. Rrecr= 0xD4, /* receive error counter */
  261. Rpcsr= 0xD8, /* 100Mb config/status */
  262. Rphycr= 0xE4, /* PHY control */
  263. Rtbscr= 0xE8, /* 10BaseT status/control */
  264. };
  265. /*
  266. * eeprom addresses
  267. * 7 to 9 (16 bit words): mac address, shifted and reversed
  268. */
  269. #define csr32r(c, r) (inl((c)->port+(r)))
  270. #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
  271. #define csr16r(c, r) (ins((c)->port+(r)))
  272. #define csr16w(c, r, l) (outs((c)->port+(r), (ulong)(l)))
  273. static void
  274. dumpcregs(Ctlr *ctlr)
  275. {
  276. int i;
  277. for(i=0; i<=0x5C; i+=4)
  278. print("%2.2ux %8.8lux\n", i, csr32r(ctlr, i));
  279. }
  280. static void
  281. promiscuous(void* arg, int on)
  282. {
  283. Ctlr *ctlr;
  284. ulong w;
  285. ctlr = ((Ether*)arg)->ctlr;
  286. ilock(&ctlr->lock);
  287. w = csr32r(ctlr, Rrfcr);
  288. if(on != ((w&Aau)!=0)){
  289. csr32w(ctlr, Rrfcr, w & ~Rfen);
  290. csr32w(ctlr, Rrfcr, Rfen | (w ^ Aau));
  291. }
  292. iunlock(&ctlr->lock);
  293. }
  294. static void
  295. attach(Ether* ether)
  296. {
  297. Ctlr *ctlr;
  298. ctlr = ether->ctlr;
  299. ilock(&ctlr->lock);
  300. if(0)
  301. dumpcregs(ctlr);
  302. csr32w(ctlr, Rcr, Rxe);
  303. iunlock(&ctlr->lock);
  304. }
  305. static long
  306. ifstat(Ether* ether, void* a, long n, ulong offset)
  307. {
  308. Ctlr *ctlr;
  309. char *buf, *p;
  310. int i, l, len;
  311. ctlr = ether->ctlr;
  312. ether->crcs = ctlr->crce;
  313. ether->frames = ctlr->runt+ctlr->ise+ctlr->rlong+ctlr->fae;
  314. ether->buffs = ctlr->rxorn+ctlr->tfu;
  315. ether->overflows = ctlr->rxsovr;
  316. if(n == 0)
  317. return 0;
  318. p = malloc(READSTR);
  319. l = snprint(p, READSTR, "Rxa: %lud\n", ctlr->rxa);
  320. l += snprint(p+l, READSTR-l, "Rxo: %lud\n", ctlr->rxo);
  321. l += snprint(p+l, READSTR-l, "Rlong: %lud\n", ctlr->rlong);
  322. l += snprint(p+l, READSTR-l, "Runt: %lud\n", ctlr->runt);
  323. l += snprint(p+l, READSTR-l, "Ise: %lud\n", ctlr->ise);
  324. l += snprint(p+l, READSTR-l, "Fae: %lud\n", ctlr->fae);
  325. l += snprint(p+l, READSTR-l, "Lbp: %lud\n", ctlr->lbp);
  326. l += snprint(p+l, READSTR-l, "Tfu: %lud\n", ctlr->tfu);
  327. l += snprint(p+l, READSTR-l, "Txa: %lud\n", ctlr->txa);
  328. l += snprint(p+l, READSTR-l, "CRC Error: %lud\n", ctlr->crce);
  329. l += snprint(p+l, READSTR-l, "Collision Seen: %lud\n", ctlr->col);
  330. l += snprint(p+l, READSTR-l, "Frame Too Long: %lud\n", ctlr->rlong);
  331. l += snprint(p+l, READSTR-l, "Runt Frame: %lud\n", ctlr->runt);
  332. l += snprint(p+l, READSTR-l, "Rx Underflow Error: %lud\n", ctlr->rxorn);
  333. l += snprint(p+l, READSTR-l, "Tx Underrun: %lud\n", ctlr->txurn);
  334. l += snprint(p+l, READSTR-l, "Excessive Collisions: %lud\n", ctlr->ec);
  335. l += snprint(p+l, READSTR-l, "Late Collision: %lud\n", ctlr->owc);
  336. l += snprint(p+l, READSTR-l, "Loss of Carrier: %lud\n", ctlr->crs);
  337. l += snprint(p+l, READSTR-l, "Parity: %lud\n", ctlr->dperr);
  338. l += snprint(p+l, READSTR-l, "Aborts: %lud\n", ctlr->rmabt+ctlr->rtabt);
  339. l += snprint(p+l, READSTR-l, "RX Status overrun: %lud\n", ctlr->rxsover);
  340. snprint(p+l, READSTR-l, "ntqmax: %d\n", ctlr->ntqmax);
  341. ctlr->ntqmax = 0;
  342. buf = a;
  343. len = readstr(offset, buf, n, p);
  344. if(offset > l)
  345. offset -= l;
  346. else
  347. offset = 0;
  348. buf += len;
  349. n -= len;
  350. l = snprint(p, READSTR, "srom:");
  351. for(i = 0; i < nelem(ctlr->srom); i++){
  352. if(i && ((i & 0x0F) == 0))
  353. l += snprint(p+l, READSTR-l, "\n ");
  354. l += snprint(p+l, READSTR-l, " %4.4uX", ctlr->srom[i]);
  355. }
  356. snprint(p+l, READSTR-l, "\n");
  357. len += readstr(offset, buf, n, p);
  358. free(p);
  359. return len;
  360. }
  361. static void
  362. txstart(Ether* ether)
  363. {
  364. Ctlr *ctlr;
  365. Block *bp;
  366. Des *des;
  367. int started;
  368. ctlr = ether->ctlr;
  369. started = 0;
  370. while(ctlr->ntq < ctlr->ntdr-1){
  371. bp = qget(ether->oq);
  372. if(bp == nil)
  373. break;
  374. des = &ctlr->tdr[ctlr->tdrh];
  375. des->bp = bp;
  376. des->addr = PADDR(bp->rp);
  377. ctlr->ntq++;
  378. coherence();
  379. des->cmdsts = Own | BLEN(bp);
  380. ctlr->tdrh = NEXT(ctlr->tdrh, ctlr->ntdr);
  381. started = 1;
  382. }
  383. if(started){
  384. coherence();
  385. csr32w(ctlr, Rcr, Txe); /* prompt */
  386. }
  387. if(ctlr->ntq > ctlr->ntqmax)
  388. ctlr->ntqmax = ctlr->ntq;
  389. }
  390. static void
  391. transmit(Ether* ether)
  392. {
  393. Ctlr *ctlr;
  394. ctlr = ether->ctlr;
  395. ilock(&ctlr->tlock);
  396. txstart(ether);
  397. iunlock(&ctlr->tlock);
  398. }
  399. static void
  400. txrxcfg(Ctlr *ctlr, int txdrth)
  401. {
  402. ulong rx, tx;
  403. rx = csr32r(ctlr, Rrxcfg);
  404. tx = csr32r(ctlr, Rtxcfg);
  405. if(ctlr->fd){
  406. rx |= Atx;
  407. tx |= Csi | Hbi;
  408. }else{
  409. rx &= ~Atx;
  410. tx &= ~(Csi | Hbi);
  411. }
  412. tx &= ~(Mxdma|Drth|Flth);
  413. tx |= Mxdma64 | Flth128 | txdrth;
  414. csr32w(ctlr, Rtxcfg, tx);
  415. rx &= ~(Mxdma|Rdrth);
  416. rx |= Mxdma64 | Rdrth64;
  417. csr32w(ctlr, Rrxcfg, rx);
  418. }
  419. static void
  420. interrupt(Ureg*, void* arg)
  421. {
  422. int len, status, cmdsts, n;
  423. Ctlr *ctlr;
  424. Ether *ether;
  425. Des *des;
  426. Block *bp;
  427. ether = arg;
  428. ctlr = ether->ctlr;
  429. while((status = csr32r(ctlr, Risr)) != 0){
  430. status &= ~(Pme|Mib);
  431. if(status & Hiberr){
  432. if(status & Rxsovr)
  433. ctlr->rxsover++;
  434. if(status & Sserr)
  435. ctlr->sserr++;
  436. if(status & Dperr)
  437. ctlr->dperr++;
  438. if(status & Rmabt)
  439. ctlr->rmabt++;
  440. if(status & Rtabt)
  441. ctlr->rtabt++;
  442. status &= ~(Hiberr|Txrcmp|Rxrcmp|Rxsovr|Dperr|Sserr|Rmabt|Rtabt);
  443. }
  444. /* update link state */
  445. if(status&Phy){
  446. status &= ~Phy;
  447. csr32r(ctlr, Rcfg);
  448. n = csr32r(ctlr, Rcfg);
  449. // iprint("83815 phy %x %x\n", n, n&Lnksts);
  450. ether->link = (n&Lnksts) != 0;
  451. }
  452. /*
  453. * Received packets.
  454. */
  455. if(status & (Rxdesc|Rxok|Rxerr|Rxearly|Rxorn)){
  456. des = &ctlr->rdr[ctlr->rdrx];
  457. while((cmdsts = des->cmdsts) & Own){
  458. if((cmdsts&Ok) == 0){
  459. if(cmdsts & Rxa)
  460. ctlr->rxa++;
  461. if(cmdsts & Rxo)
  462. ctlr->rxo++;
  463. if(cmdsts & Long)
  464. ctlr->rlong++;
  465. if(cmdsts & Runt)
  466. ctlr->runt++;
  467. if(cmdsts & Ise)
  468. ctlr->ise++;
  469. if(cmdsts & Crce)
  470. ctlr->crce++;
  471. if(cmdsts & Fae)
  472. ctlr->fae++;
  473. if(cmdsts & Lbp)
  474. ctlr->lbp++;
  475. if(cmdsts & Col)
  476. ctlr->col++;
  477. }
  478. else if(bp = iallocb(Rbsz)){
  479. len = (cmdsts&Size)-4;
  480. if(len <= 0){
  481. debug("ns83815: packet len %d <=0\n", len);
  482. freeb(des->bp);
  483. }else{
  484. des->bp->wp = des->bp->rp+len;
  485. etheriq(ether, des->bp, 1);
  486. }
  487. des->bp = bp;
  488. des->addr = PADDR(bp->rp);
  489. coherence();
  490. }else{
  491. debug("ns83815: interrupt: iallocb for input buffer failed\n");
  492. des->bp->next = 0;
  493. }
  494. des->cmdsts = Rbsz;
  495. coherence();
  496. ctlr->rdrx = NEXT(ctlr->rdrx, ctlr->nrdr);
  497. des = &ctlr->rdr[ctlr->rdrx];
  498. }
  499. status &= ~(Rxdesc|Rxok|Rxerr|Rxearly|Rxorn);
  500. }
  501. /*
  502. * Check the transmit side:
  503. * check for Transmit Underflow and Adjust
  504. * the threshold upwards;
  505. * free any transmitted buffers and try to
  506. * top-up the ring.
  507. */
  508. if(status & Txurn){
  509. ctlr->txurn++;
  510. ilock(&ctlr->lock);
  511. /* change threshold */
  512. iunlock(&ctlr->lock);
  513. status &= ~(Txurn);
  514. }
  515. ilock(&ctlr->tlock);
  516. while(ctlr->ntq){
  517. des = &ctlr->tdr[ctlr->tdri];
  518. cmdsts = des->cmdsts;
  519. if(cmdsts & Own)
  520. break;
  521. if((cmdsts & Ok) == 0){
  522. if(cmdsts & Txa)
  523. ctlr->txa++;
  524. if(cmdsts & Tfu)
  525. ctlr->tfu++;
  526. if(cmdsts & Td)
  527. ctlr->td++;
  528. if(cmdsts & Ed)
  529. ctlr->ed++;
  530. if(cmdsts & Owc)
  531. ctlr->owc++;
  532. if(cmdsts & Ec)
  533. ctlr->ec++;
  534. ether->oerrs++;
  535. }
  536. freeb(des->bp);
  537. des->bp = nil;
  538. des->cmdsts = 0;
  539. ctlr->ntq--;
  540. ctlr->tdri = NEXT(ctlr->tdri, ctlr->ntdr);
  541. }
  542. txstart(ether);
  543. iunlock(&ctlr->tlock);
  544. status &= ~(Txurn|Txidle|Txerr|Txdesc|Txok);
  545. /*
  546. * Anything left not catered for?
  547. */
  548. if(status)
  549. print("#l%d: status %8.8uX\n", ether->ctlrno, status);
  550. }
  551. }
  552. static void
  553. ctlrinit(Ether* ether)
  554. {
  555. Ctlr *ctlr;
  556. Des *des, *last;
  557. ctlr = ether->ctlr;
  558. /*
  559. * Allocate suitable aligned descriptors
  560. * for the transmit and receive rings;
  561. * initialise the receive ring;
  562. * initialise the transmit ring;
  563. * unmask interrupts and start the transmit side.
  564. */
  565. des = xspanalloc((ctlr->nrdr+ctlr->ntdr)*sizeof(Des), 32, 0);
  566. ctlr->tdr = des;
  567. ctlr->rdr = des+ctlr->ntdr;
  568. last = nil;
  569. for(des = ctlr->rdr; des < &ctlr->rdr[ctlr->nrdr]; des++){
  570. des->bp = iallocb(Rbsz);
  571. if(des->bp == nil)
  572. error(Enomem);
  573. des->cmdsts = Rbsz;
  574. des->addr = PADDR(des->bp->rp);
  575. if(last != nil)
  576. last->next = PADDR(des);
  577. last = des;
  578. }
  579. ctlr->rdr[ctlr->nrdr-1].next = PADDR(ctlr->rdr);
  580. ctlr->rdrx = 0;
  581. csr32w(ctlr, Rrxdp, PADDR(ctlr->rdr));
  582. last = nil;
  583. for(des = ctlr->tdr; des < &ctlr->tdr[ctlr->ntdr]; des++){
  584. des->cmdsts = 0;
  585. des->bp = nil;
  586. des->addr = ~0;
  587. if(last != nil)
  588. last->next = PADDR(des);
  589. last = des;
  590. }
  591. ctlr->tdr[ctlr->ntdr-1].next = PADDR(ctlr->tdr);
  592. ctlr->tdrh = 0;
  593. ctlr->tdri = 0;
  594. csr32w(ctlr, Rtxdp, PADDR(ctlr->tdr));
  595. txrxcfg(ctlr, Drth512);
  596. csr32w(ctlr, Rimr, Dperr|Sserr|Rmabt|Rtabt|Rxsovr|Hiberr|Txurn|Txerr|
  597. Txdesc|Txok|Rxorn|Rxerr|Rxdesc|Rxok); /* Phy|Pme|Mib */
  598. csr32w(ctlr, Rmicr, Inten); /* enable phy interrupts */
  599. csr32r(ctlr, Risr); /* clear status */
  600. csr32w(ctlr, Rier, Ie);
  601. }
  602. static void
  603. eeclk(Ctlr *ctlr, int clk)
  604. {
  605. csr32w(ctlr, Rmear, Eesel | clk);
  606. microdelay(2);
  607. }
  608. static void
  609. eeidle(Ctlr *ctlr)
  610. {
  611. int i;
  612. eeclk(ctlr, 0);
  613. eeclk(ctlr, Eeclk);
  614. for(i=0; i<25; i++){
  615. eeclk(ctlr, 0);
  616. eeclk(ctlr, Eeclk);
  617. }
  618. eeclk(ctlr, 0);
  619. csr32w(ctlr, Rmear, 0);
  620. microdelay(2);
  621. }
  622. static int
  623. eegetw(Ctlr *ctlr, int a)
  624. {
  625. int d, i, w, v;
  626. eeidle(ctlr);
  627. eeclk(ctlr, 0);
  628. eeclk(ctlr, Eeclk);
  629. d = 0x180 | a;
  630. for(i=0x400; i; i>>=1){
  631. v = (d & i) ? Eedi : 0;
  632. eeclk(ctlr, v);
  633. eeclk(ctlr, Eeclk|v);
  634. }
  635. eeclk(ctlr, 0);
  636. w = 0;
  637. for(i=0x8000; i; i >>= 1){
  638. eeclk(ctlr, Eeclk);
  639. if(csr32r(ctlr, Rmear) & Eedo)
  640. w |= i;
  641. microdelay(2);
  642. eeclk(ctlr, 0);
  643. }
  644. eeidle(ctlr);
  645. return w;
  646. }
  647. static void
  648. resetctlr(Ctlr *ctlr)
  649. {
  650. int i;
  651. csr32w(ctlr, Rcr, Rst);
  652. for(i=0;; i++){
  653. if(i > 100)
  654. panic("ns83815: soft reset did not complete");
  655. microdelay(250);
  656. if((csr32r(ctlr, Rcr) & Rst) == 0)
  657. break;
  658. delay(1);
  659. }
  660. }
  661. static void
  662. shutdown(Ether* ether)
  663. {
  664. Ctlr *ctlr = ether->ctlr;
  665. print("ether83815 shutting down\n");
  666. csr32w(ctlr, Rcr, Rxd|Txd); /* disable transceiver */
  667. resetctlr(ctlr);
  668. }
  669. static void
  670. softreset(Ctlr* ctlr, int resetphys)
  671. {
  672. int i, w;
  673. /*
  674. * Soft-reset the controller
  675. */
  676. resetctlr(ctlr);
  677. csr32w(ctlr, Rccsr, Pmests);
  678. csr32w(ctlr, Rccsr, 0);
  679. csr32w(ctlr, Rcfg, csr32r(ctlr, Rcfg) | Pint_acen);
  680. if(resetphys){
  681. /*
  682. * Soft-reset the PHY
  683. */
  684. csr32w(ctlr, Rbmcr, Reset);
  685. for(i=0;; i++){
  686. if(i > 100)
  687. panic("ns83815: PHY soft reset time out");
  688. if((csr32r(ctlr, Rbmcr) & Reset) == 0)
  689. break;
  690. delay(1);
  691. }
  692. }
  693. /*
  694. * Initialisation values, in sequence (see 4.4 Recommended Registers Configuration)
  695. */
  696. csr16w(ctlr, 0xCC, 0x0001); /* PGSEL */
  697. csr16w(ctlr, 0xE4, 0x189C); /* PMCCSR */
  698. csr16w(ctlr, 0xFC, 0x0000); /* TSTDAT */
  699. csr16w(ctlr, 0xF4, 0x5040); /* DSPCFG */
  700. csr16w(ctlr, 0xF8, 0x008C); /* SDCFG */
  701. /*
  702. * Auto negotiate
  703. */
  704. w = csr16r(ctlr, Rbmsr); /* clear latched bits */
  705. debug("anar: %4.4ux\n", csr16r(ctlr, Ranar));
  706. csr16w(ctlr, Rbmcr, Anena);
  707. if(csr16r(ctlr, Ranar) == 0 || (csr32r(ctlr, Rcfg) & Aneg_dn) == 0){
  708. csr16w(ctlr, Rbmcr, Anena|Anrestart);
  709. for(i=0;; i++){
  710. if(i > 3000){
  711. print("ns83815: auto neg timed out\n");
  712. break;
  713. }
  714. if((w = csr16r(ctlr, Rbmsr)) & Ancomp)
  715. break;
  716. delay(1);
  717. }
  718. debug("%d ms\n", i);
  719. w &= 0xFFFF;
  720. debug("bmsr: %4.4ux\n", w);
  721. }
  722. USED(w);
  723. debug("anar: %4.4ux\n", csr16r(ctlr, Ranar));
  724. debug("anlpar: %4.4ux\n", csr16r(ctlr, Ranlpar));
  725. debug("aner: %4.4ux\n", csr16r(ctlr, Raner));
  726. debug("physts: %4.4ux\n", csr16r(ctlr, Rphysts));
  727. debug("tbscr: %4.4ux\n", csr16r(ctlr, Rtbscr));
  728. }
  729. static int
  730. media(Ether* ether)
  731. {
  732. Ctlr* ctlr;
  733. ulong cfg;
  734. ctlr = ether->ctlr;
  735. cfg = csr32r(ctlr, Rcfg);
  736. ctlr->fd = (cfg & Fdup) != 0;
  737. ether->link = (cfg&Lnksts) != 0;
  738. return (cfg&(Lnksts|Speed100)) == Lnksts? 10: 100;
  739. }
  740. static char* mediatable[9] = {
  741. "10BASE-T", /* TP */
  742. "10BASE-2", /* BNC */
  743. "10BASE-5", /* AUI */
  744. "100BASE-TX",
  745. "10BASE-TFD",
  746. "100BASE-TXFD",
  747. "100BASE-T4",
  748. "100BASE-FX",
  749. "100BASE-FXFD",
  750. };
  751. static int
  752. is630(ulong id, Pcidev *p)
  753. {
  754. if(id == SiS900)
  755. switch (p->rid) {
  756. case SiSrev630s:
  757. case SiSrev630e:
  758. case SiSrev630ea1:
  759. return 1;
  760. }
  761. return 0;
  762. }
  763. enum {
  764. MagicReg = 0x48,
  765. MagicRegSz = 1,
  766. Magicrden = 0x40, /* read enable, apparently */
  767. Paddr= 0x70, /* address port */
  768. Pdata= 0x71, /* data port */
  769. };
  770. /* rcmos() originally from LANL's SiS 900 driver's rcmos() */
  771. static int
  772. sisrdcmos(Ctlr *ctlr)
  773. {
  774. int i;
  775. unsigned reg;
  776. ulong port;
  777. Pcidev *p;
  778. debug("ns83815: SiS 630 rev. %ux reading mac address from cmos\n", ctlr->pcidev->rid);
  779. p = pcimatch(nil, SiS, SiS630bridge);
  780. if(p == nil) {
  781. print("ns83815: no SiS 630 rev. %ux bridge for mac addr\n",
  782. ctlr->pcidev->rid);
  783. return 0;
  784. }
  785. port = p->mem[0].bar & ~0x01;
  786. debug("ns83815: SiS 630 rev. %ux reading mac addr from cmos via bridge at port 0x%lux\n", ctlr->pcidev->rid, port);
  787. reg = pcicfgr8(p, MagicReg);
  788. pcicfgw8(p, MagicReg, reg|Magicrden);
  789. for (i = 0; i < Eaddrlen; i++) {
  790. outb(port+Paddr, SiS630eenodeaddr + i);
  791. ctlr->sromea[i] = inb(port+Pdata);
  792. }
  793. pcicfgw8(p, MagicReg, reg & ~Magicrden);
  794. return 1;
  795. }
  796. /*
  797. * If this is a SiS 630E chipset with an embedded SiS 900 controller,
  798. * we have to read the MAC address from the APC CMOS RAM. - sez freebsd.
  799. * However, CMOS *is* NVRAM normally. See devrtc.c:440, memory.c:88.
  800. */
  801. static void
  802. sissrom(Ctlr *ctlr)
  803. {
  804. union {
  805. uchar eaddr[Eaddrlen];
  806. ushort alignment;
  807. } ee;
  808. int i, off = SiSeenodeaddr, cnt = sizeof ee.eaddr / sizeof(short);
  809. ushort *shp = (ushort *)ee.eaddr;
  810. if(!is630(ctlr->id, ctlr->pcidev) || !sisrdcmos(ctlr)) {
  811. for (i = 0; i < cnt; i++)
  812. *shp++ = eegetw(ctlr, off++);
  813. memmove(ctlr->sromea, ee.eaddr, sizeof ctlr->sromea);
  814. }
  815. }
  816. static void
  817. nssrom(Ctlr* ctlr)
  818. {
  819. int i, j;
  820. for(i = 0; i < nelem(ctlr->srom); i++)
  821. ctlr->srom[i] = eegetw(ctlr, i);
  822. /*
  823. * the MAC address is reversed, straddling word boundaries
  824. */
  825. j = Nseenodeaddr*16 + 15;
  826. for(i=0; i<48; i++){
  827. ctlr->sromea[i>>3] |= ((ctlr->srom[j>>4] >> (15-(j&0xF))) & 1) << (i&7);
  828. j++;
  829. }
  830. }
  831. static void
  832. srom(Ctlr* ctlr)
  833. {
  834. memset(ctlr->sromea, 0, sizeof(ctlr->sromea));
  835. switch (ctlr->id) {
  836. case SiS900:
  837. case SiS7016:
  838. sissrom(ctlr);
  839. break;
  840. case Nat83815:
  841. nssrom(ctlr);
  842. break;
  843. default:
  844. print("ns83815: srom: unknown id 0x%ux\n", ctlr->id);
  845. break;
  846. }
  847. }
  848. static void
  849. scanpci83815(void)
  850. {
  851. Ctlr *ctlr;
  852. Pcidev *p;
  853. ulong id;
  854. p = nil;
  855. while(p = pcimatch(p, 0, 0)){
  856. if(p->ccrb != Pcibcnet || p->ccru != 0)
  857. continue;
  858. id = (p->did<<16)|p->vid;
  859. switch(id){
  860. default:
  861. continue;
  862. case Nat83815:
  863. break;
  864. case SiS900:
  865. break;
  866. }
  867. /*
  868. * bar[0] is the I/O port register address and
  869. * bar[1] is the memory-mapped register address.
  870. */
  871. ctlr = malloc(sizeof(Ctlr));
  872. ctlr->port = p->mem[0].bar & ~0x01;
  873. ctlr->pcidev = p;
  874. ctlr->id = id;
  875. if(ioalloc(ctlr->port, p->mem[0].size, 0, "ns83815") < 0){
  876. print("ns83815: port 0x%uX in use\n", ctlr->port);
  877. free(ctlr);
  878. continue;
  879. }
  880. softreset(ctlr, 0);
  881. srom(ctlr);
  882. if(ctlrhead != nil)
  883. ctlrtail->next = ctlr;
  884. else
  885. ctlrhead = ctlr;
  886. ctlrtail = ctlr;
  887. }
  888. }
  889. /* multicast already on, don't need to do anything */
  890. static void
  891. multicast(void*, uchar*, int)
  892. {
  893. }
  894. static int
  895. reset(Ether* ether)
  896. {
  897. Ctlr *ctlr;
  898. int i, x;
  899. ulong ctladdr;
  900. uchar ea[Eaddrlen];
  901. static int scandone;
  902. if(scandone == 0){
  903. scanpci83815();
  904. scandone = 1;
  905. }
  906. /*
  907. * Any adapter matches if no ether->port is supplied,
  908. * otherwise the ports must match.
  909. */
  910. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  911. if(ctlr->active)
  912. continue;
  913. if(ether->port == 0 || ether->port == ctlr->port){
  914. ctlr->active = 1;
  915. break;
  916. }
  917. }
  918. if(ctlr == nil)
  919. return -1;
  920. ether->ctlr = ctlr;
  921. ether->port = ctlr->port;
  922. ether->irq = ctlr->pcidev->intl;
  923. ether->tbdf = ctlr->pcidev->tbdf;
  924. /*
  925. * Check if the adapter's station address is to be overridden.
  926. * If not, read it from the EEPROM and set in ether->ea prior to
  927. * loading the station address in the hardware.
  928. */
  929. memset(ea, 0, Eaddrlen);
  930. if(memcmp(ea, ether->ea, Eaddrlen) == 0)
  931. memmove(ether->ea, ctlr->sromea, Eaddrlen);
  932. for(i=0; i<Eaddrlen; i+=2){
  933. x = ether->ea[i] | (ether->ea[i+1]<<8);
  934. ctladdr = (ctlr->id == Nat83815? i: i<<15);
  935. csr32w(ctlr, Rrfcr, ctladdr);
  936. csr32w(ctlr, Rrfdr, x);
  937. }
  938. csr32w(ctlr, Rrfcr, Rfen|Apm|Aab|Aam);
  939. ether->mbps = media(ether);
  940. /*
  941. * Look for a medium override in case there's no autonegotiation
  942. * the autonegotiation fails.
  943. */
  944. for(i = 0; i < ether->nopt; i++){
  945. if(cistrcmp(ether->opt[i], "FD") == 0){
  946. ctlr->fd = 1;
  947. continue;
  948. }
  949. for(x = 0; x < nelem(mediatable); x++){
  950. debug("compare <%s> <%s>\n", mediatable[x],
  951. ether->opt[i]);
  952. if(cistrcmp(mediatable[x], ether->opt[i]) == 0){
  953. if(x != 4 && x >= 3)
  954. ether->mbps = 100;
  955. else
  956. ether->mbps = 10;
  957. switch(x){
  958. default:
  959. ctlr->fd = 0;
  960. break;
  961. case 0x04: /* 10BASE-TFD */
  962. case 0x05: /* 100BASE-TXFD */
  963. case 0x08: /* 100BASE-FXFD */
  964. ctlr->fd = 1;
  965. break;
  966. }
  967. break;
  968. }
  969. }
  970. }
  971. /*
  972. * Initialise descriptor rings, ethernet address.
  973. */
  974. ctlr->nrdr = Nrde;
  975. ctlr->ntdr = Ntde;
  976. pcisetbme(ctlr->pcidev);
  977. ctlrinit(ether);
  978. /*
  979. * Linkage to the generic ethernet driver.
  980. */
  981. ether->attach = attach;
  982. ether->transmit = transmit;
  983. ether->interrupt = interrupt;
  984. ether->ifstat = ifstat;
  985. ether->arg = ether;
  986. ether->promiscuous = promiscuous;
  987. ether->multicast = multicast;
  988. ether->shutdown = shutdown;
  989. return 0;
  990. }
  991. void
  992. ether83815link(void)
  993. {
  994. addethercard("83815", reset);
  995. }