etherm10g.c 28 KB

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  1. /*
  2. * myricom 10 Gb ethernet driver
  3. * © 2007 erik quanstrom, coraid
  4. *
  5. * the card is big endian.
  6. * we use uvlong rather than uintptr to hold addresses so that
  7. * we don't get "warning: stupid shift" on 32-bit architectures.
  8. */
  9. #include "u.h"
  10. #include "../port/lib.h"
  11. #include "mem.h"
  12. #include "dat.h"
  13. #include "fns.h"
  14. #include "io.h"
  15. #include "../port/error.h"
  16. #include "../port/netif.h"
  17. #include "../pc/etherif.h"
  18. #ifndef KiB
  19. #define KiB 1024u /* Kibi 0x0000000000000400 */
  20. #define MiB 1048576u /* Mebi 0x0000000000100000 */
  21. #endif /* KiB */
  22. #define dprint(...) if(debug) print(__VA_ARGS__)
  23. #define pcicapdbg(...)
  24. #define malign(n) mallocalign((n), 4*KiB, 0, 0)
  25. #include "etherm10g2k.i"
  26. #include "etherm10g4k.i"
  27. static int debug = 0;
  28. static char Etimeout[] = "timeout";
  29. enum {
  30. Epromsz = 256,
  31. Maxslots= 1024,
  32. Align = 4096,
  33. Maxmtu = 9000,
  34. Noconf = 0xffffffff,
  35. Fwoffset= 1*MiB,
  36. Cmdoff = 0xf80000, /* command port offset */
  37. Fwsubmt = 0xfc0000, /* firmware submission command port offset */
  38. Rdmaoff = 0xfc01c0, /* rdma command port offset */
  39. };
  40. enum {
  41. CZero,
  42. Creset,
  43. Cversion,
  44. CSintrqdma, /* issue these before Cetherup */
  45. CSbigsz, /* in bytes bigsize = 2^n */
  46. CSsmallsz,
  47. CGsendoff,
  48. CGsmallrxoff,
  49. CGbigrxoff,
  50. CGirqackoff,
  51. CGirqdeassoff,
  52. CGsendrgsz,
  53. CGrxrgsz,
  54. CSintrqsz, /* 2^n */
  55. Cetherup, /* above parameters + mtu/mac addr must be set first. */
  56. Cetherdn,
  57. CSmtu, /* below may be issued live */
  58. CGcoaloff, /* in µs */
  59. CSstatsrate, /* in µs */
  60. CSstatsdma,
  61. Cpromisc,
  62. Cnopromisc,
  63. CSmac,
  64. Cenablefc,
  65. Cdisablefc,
  66. Cdmatest, /* address in d[0-1], d[2]=length */
  67. Cenableallmc,
  68. Cdisableallmc,
  69. CSjoinmc,
  70. CSleavemc,
  71. Cleaveallmc,
  72. CSstatsdma2, /* adds (unused) multicast stats */
  73. };
  74. typedef union {
  75. uint i[2];
  76. uchar c[8];
  77. } Cmd;
  78. typedef ulong Slot;
  79. typedef struct {
  80. ushort cksum;
  81. ushort len;
  82. } Slotparts;
  83. enum {
  84. SFsmall = 1,
  85. SFfirst = 2,
  86. SFalign = 4,
  87. SFnotso = 16,
  88. };
  89. typedef struct {
  90. ulong high;
  91. ulong low;
  92. ushort hdroff;
  93. ushort len;
  94. uchar pad;
  95. uchar nrdma;
  96. uchar chkoff;
  97. uchar flags;
  98. } Send;
  99. typedef struct {
  100. QLock;
  101. Send *lanai; /* tx ring (cksum+len in lanai memory) */
  102. Send *host; /* tx ring (data in our memory) */
  103. Block **bring;
  104. // uchar *wcfifo; /* what the heck is a w/c fifo? */
  105. int size; /* of buffers in the z8's memory */
  106. ulong segsz;
  107. uint n; /* rxslots */
  108. uint m; /* mask; rxslots must be a power of two */
  109. uint i; /* number of segments (not frames) queued */
  110. uint cnt; /* number of segments sent by the card */
  111. ulong npkt;
  112. vlong nbytes;
  113. } Tx;
  114. typedef struct {
  115. Lock;
  116. Block *head;
  117. uint size; /* buffer size of each block */
  118. uint n; /* n free buffers */
  119. uint cnt;
  120. } Bpool;
  121. static Bpool smpool = { .size = 128, };
  122. static Bpool bgpool = { .size = Maxmtu, };
  123. typedef struct {
  124. Bpool *pool; /* free buffers */
  125. ulong *lanai; /* rx ring; we have no permanent host shadow */
  126. Block **host; /* called "info" in myricom driver */
  127. // uchar *wcfifo; /* cmd submission fifo */
  128. uint m;
  129. uint n; /* rxslots */
  130. uint i;
  131. uint cnt; /* number of buffers allocated (lifetime) */
  132. uint allocfail;
  133. } Rx;
  134. /* dma mapped. unix network byte order. */
  135. typedef struct {
  136. uchar txcnt[4];
  137. uchar linkstat[4];
  138. uchar dlink[4];
  139. uchar derror[4];
  140. uchar drunt[4];
  141. uchar doverrun[4];
  142. uchar dnosm[4];
  143. uchar dnobg[4];
  144. uchar nrdma[4];
  145. uchar txstopped;
  146. uchar down;
  147. uchar updated;
  148. uchar valid;
  149. } Stats;
  150. enum {
  151. Detached,
  152. Attached,
  153. Runed,
  154. };
  155. typedef struct {
  156. Slot *entry;
  157. uvlong busaddr;
  158. uint m;
  159. uint n;
  160. uint i;
  161. } Done;
  162. typedef struct Ctlr Ctlr;
  163. typedef struct Ctlr {
  164. QLock;
  165. int state;
  166. int kprocs;
  167. uvlong port;
  168. Pcidev* pcidev;
  169. Ctlr* next;
  170. int active;
  171. int id; /* do we need this? */
  172. uchar ra[Eaddrlen];
  173. int ramsz;
  174. uchar *ram;
  175. ulong *irqack;
  176. ulong *irqdeass;
  177. ulong *coal;
  178. char eprom[Epromsz];
  179. ulong serial; /* unit serial number */
  180. QLock cmdl;
  181. Cmd *cmd; /* address of command return */
  182. uvlong cprt; /* bus address of command */
  183. uvlong boot; /* boot address */
  184. Done done;
  185. Tx tx;
  186. Rx sm;
  187. Rx bg;
  188. Stats *stats;
  189. uvlong statsprt;
  190. Rendez rxrendez;
  191. Rendez txrendez;
  192. int msi;
  193. ulong linkstat;
  194. ulong nrdma;
  195. } Ctlr;
  196. static Ctlr *ctlrs;
  197. enum {
  198. PciCapPMG = 0x01, /* power management */
  199. PciCapAGP = 0x02,
  200. PciCapVPD = 0x03, /* vital product data */
  201. PciCapSID = 0x04, /* slot id */
  202. PciCapMSI = 0x05,
  203. PciCapCHS = 0x06, /* compact pci hot swap */
  204. PciCapPCIX = 0x07,
  205. PciCapHTC = 0x08, /* hypertransport irq conf */
  206. PciCapVND = 0x09, /* vendor specific information */
  207. PciCapHSW = 0x0C, /* hot swap */
  208. PciCapPCIe = 0x10,
  209. PciCapMSIX = 0x11,
  210. };
  211. enum {
  212. PcieAERC = 1,
  213. PcieVC,
  214. PcieSNC,
  215. PciePBC,
  216. };
  217. enum {
  218. AercCCR = 0x18, /* control register */
  219. };
  220. enum {
  221. PcieCTL = 8,
  222. PcieLCR = 12,
  223. PcieMRD = 0x7000, /* maximum read size */
  224. };
  225. static int
  226. pcicap(Pcidev *p, int cap)
  227. {
  228. int i, c, off;
  229. pcicapdbg("pcicap: %x:%d\n", p->vid, p->did);
  230. off = 0x34; /* 0x14 for cardbus */
  231. for(i = 48; i--; ){
  232. pcicapdbg("\t" "loop %x\n", off);
  233. off = pcicfgr8(p, off);
  234. pcicapdbg("\t" "pcicfgr8 %x\n", off);
  235. if(off < 0x40)
  236. break;
  237. off &= ~3;
  238. c = pcicfgr8(p, off);
  239. pcicapdbg("\t" "pcicfgr8 %x\n", c);
  240. if(c == 0xff)
  241. break;
  242. if(c == cap)
  243. return off;
  244. off++;
  245. }
  246. return 0;
  247. }
  248. /*
  249. * this function doesn't work because pcicgr32 doesn't have access
  250. * to the pcie extended configuration space.
  251. */
  252. static int
  253. pciecap(Pcidev *p, int cap)
  254. {
  255. uint off, i;
  256. off = 0x100;
  257. while(((i = pcicfgr32(p, off))&0xffff) != cap){
  258. off = i >> 20;
  259. print("pciecap offset = %ud\n", off);
  260. if(off < 0x100 || off >= 4*KiB - 1)
  261. return 0;
  262. }
  263. print("pciecap found = %ud\n", off);
  264. return off;
  265. }
  266. static int
  267. setpcie(Pcidev *p)
  268. {
  269. int off;
  270. /* set 4k writes */
  271. off = pcicap(p, PciCapPCIe);
  272. if(off < 64)
  273. return -1;
  274. off += PcieCTL;
  275. pcicfgw16(p, off, (pcicfgr16(p, off) & ~PcieMRD) | 5<<12);
  276. return 0;
  277. }
  278. static int
  279. whichfw(Pcidev *p)
  280. {
  281. char *s;
  282. int i, off, lanes, ecrc;
  283. ulong cap;
  284. /* check the number of configured lanes. */
  285. off = pcicap(p, PciCapPCIe);
  286. if(off < 64)
  287. return -1;
  288. off += PcieLCR;
  289. cap = pcicfgr16(p, off);
  290. lanes = (cap>>4) & 0x3f;
  291. /* check AERC register. we need it on. */
  292. off = pciecap(p, PcieAERC);
  293. print("%d offset\n", off);
  294. cap = 0;
  295. if(off != 0){
  296. off += AercCCR;
  297. cap = pcicfgr32(p, off);
  298. print("%lud cap\n", cap);
  299. }
  300. ecrc = (cap>>4) & 0xf;
  301. /* if we don't like the aerc, kick it here. */
  302. print("m10g %d lanes; ecrc=%d; ", lanes, ecrc);
  303. if(s = getconf("myriforce")){
  304. i = atoi(s);
  305. if(i != 4*KiB || i != 2*KiB)
  306. i = 2*KiB;
  307. print("fw=%d [forced]\n", i);
  308. return i;
  309. }
  310. if(lanes <= 4){
  311. print("fw = 4096 [lanes]\n");
  312. return 4*KiB;
  313. }
  314. if(ecrc & 10){
  315. print("fw = 4096 [ecrc set]\n");
  316. return 4*KiB;
  317. }
  318. print("fw = 4096 [default]\n");
  319. return 4*KiB;
  320. }
  321. static int
  322. parseeprom(Ctlr *c)
  323. {
  324. int i, j, k, l, bits;
  325. char *s;
  326. dprint("m10g eprom:\n");
  327. s = c->eprom;
  328. bits = 3;
  329. for(i = 0; s[i] && i < Epromsz; i++){
  330. l = strlen(s+i);
  331. dprint("\t%s\n", s+i);
  332. if(strncmp(s+i, "MAC=", 4) == 0 && l == 4+12+5){
  333. bits ^= 1;
  334. j = i + 4;
  335. for(k = 0; k < 6; k++)
  336. c->ra[k] = strtoul(s+j+3*k, 0, 16);
  337. }else if(strncmp(s+i, "SN=", 3) == 0){
  338. bits ^= 2;
  339. c->serial = atoi(s+i+3);
  340. }
  341. i += l;
  342. }
  343. if(bits)
  344. return -1;
  345. return 0;
  346. }
  347. static ushort
  348. pbit16(ushort i)
  349. {
  350. ushort j;
  351. uchar *p;
  352. p = (uchar*)&j;
  353. p[1] = i;
  354. p[0] = i>>8;
  355. return j;
  356. }
  357. static ushort
  358. gbit16(uchar i[2])
  359. {
  360. ushort j;
  361. j = i[1];
  362. j |= i[0]<<8;
  363. return j;
  364. }
  365. static ulong
  366. pbit32(ulong i)
  367. {
  368. ulong j;
  369. uchar *p;
  370. p = (uchar*)&j;
  371. p[3] = i;
  372. p[2] = i>>8;
  373. p[1] = i>>16;
  374. p[0] = i>>24;
  375. return j;
  376. }
  377. static ulong
  378. gbit32(uchar i[4])
  379. {
  380. ulong j;
  381. j = i[3];
  382. j |= i[2]<<8;
  383. j |= i[1]<<16;
  384. j |= i[0]<<24;
  385. return j;
  386. }
  387. static void
  388. prepcmd(ulong *cmd, int i)
  389. {
  390. while(i-- > 0)
  391. cmd[i] = pbit32(cmd[i]);
  392. }
  393. /*
  394. * the command looks like this (int 32bit integers)
  395. * cmd type
  396. * addr (low)
  397. * addr (high)
  398. * pad (used for dma testing)
  399. * response (high)
  400. * response (low)
  401. * 40 byte = 5 int pad.
  402. */
  403. ulong
  404. cmd(Ctlr *c, int type, uvlong data)
  405. {
  406. ulong buf[16], i;
  407. Cmd *cmd;
  408. qlock(&c->cmdl);
  409. cmd = c->cmd;
  410. cmd->i[1] = Noconf;
  411. memset(buf, 0, sizeof buf);
  412. buf[0] = type;
  413. buf[1] = data;
  414. buf[2] = data >> 32;
  415. buf[4] = c->cprt >> 32;
  416. buf[5] = c->cprt;
  417. prepcmd(buf, 6);
  418. coherence();
  419. memmove(c->ram + Cmdoff, buf, sizeof buf);
  420. if(waserror())
  421. nexterror();
  422. for(i = 0; i < 15; i++){
  423. if(cmd->i[1] != Noconf){
  424. poperror();
  425. i = gbit32(cmd->c);
  426. qunlock(&c->cmdl);
  427. if(cmd->i[1] != 0)
  428. dprint("[%lux]", i);
  429. return i;
  430. }
  431. tsleep(&up->sleep, return0, 0, 1);
  432. }
  433. qunlock(&c->cmdl);
  434. iprint("m10g: cmd timeout [%ux %ux] cmd=%d\n",
  435. cmd->i[0], cmd->i[1], type);
  436. error(Etimeout);
  437. return ~0; /* silence! */
  438. }
  439. ulong
  440. maccmd(Ctlr *c, int type, uchar *m)
  441. {
  442. ulong buf[16], i;
  443. Cmd *cmd;
  444. qlock(&c->cmdl);
  445. cmd = c->cmd;
  446. cmd->i[1] = Noconf;
  447. memset(buf, 0, sizeof buf);
  448. buf[0] = type;
  449. buf[1] = m[0]<<24 | m[1]<<16 | m[2]<<8 | m[3];
  450. buf[2] = m[4]<< 8 | m[5];
  451. buf[4] = c->cprt >> 32;
  452. buf[5] = c->cprt;
  453. prepcmd(buf, 6);
  454. coherence();
  455. memmove(c->ram + Cmdoff, buf, sizeof buf);
  456. if(waserror())
  457. nexterror();
  458. for(i = 0; i < 15; i++){
  459. if(cmd->i[1] != Noconf){
  460. poperror();
  461. i = gbit32(cmd->c);
  462. qunlock(&c->cmdl);
  463. if(cmd->i[1] != 0)
  464. dprint("[%lux]", i);
  465. return i;
  466. }
  467. tsleep(&up->sleep, return0, 0, 1);
  468. }
  469. qunlock(&c->cmdl);
  470. iprint("m10g: maccmd timeout [%ux %ux] cmd=%d\n",
  471. cmd->i[0], cmd->i[1], type);
  472. error(Etimeout);
  473. return ~0; /* silence! */
  474. }
  475. /* remove this garbage after testing */
  476. enum {
  477. DMAread = 0x10000,
  478. DMAwrite= 0x1,
  479. };
  480. ulong
  481. dmatestcmd(Ctlr *c, int type, uvlong addr, int len)
  482. {
  483. ulong buf[16], i;
  484. memset(buf, 0, sizeof buf);
  485. memset(c->cmd, Noconf, sizeof *c->cmd);
  486. buf[0] = Cdmatest;
  487. buf[1] = addr;
  488. buf[2] = addr >> 32;
  489. buf[3] = len * type;
  490. buf[4] = c->cprt >> 32;
  491. buf[5] = c->cprt;
  492. prepcmd(buf, 6);
  493. coherence();
  494. memmove(c->ram + Cmdoff, buf, sizeof buf);
  495. if(waserror())
  496. nexterror();
  497. for(i = 0; i < 15; i++){
  498. if(c->cmd->i[1] != Noconf){
  499. i = gbit32(c->cmd->c);
  500. if(i == 0)
  501. error(Eio);
  502. poperror();
  503. return i;
  504. }
  505. tsleep(&up->sleep, return0, 0, 5);
  506. }
  507. error(Etimeout);
  508. return ~0; /* silence! */
  509. }
  510. ulong
  511. rdmacmd(Ctlr *c, int on)
  512. {
  513. ulong buf[16], i;
  514. memset(buf, 0, sizeof buf);
  515. c->cmd->i[0] = 0;
  516. coherence();
  517. buf[0] = c->cprt >> 32;
  518. buf[1] = c->cprt;
  519. buf[2] = Noconf;
  520. buf[3] = c->cprt >> 32;
  521. buf[4] = c->cprt;
  522. buf[5] = on;
  523. prepcmd(buf, 6);
  524. memmove(c->ram + Rdmaoff, buf, sizeof buf);
  525. if(waserror())
  526. nexterror();
  527. for(i = 0; i < 20; i++){
  528. if(c->cmd->i[0] == Noconf){
  529. poperror();
  530. return gbit32(c->cmd->c);
  531. }
  532. tsleep(&up->sleep, return0, 0, 1);
  533. }
  534. error(Etimeout);
  535. iprint("m10g: rdmacmd timeout\n");
  536. return ~0; /* silence! */
  537. }
  538. static int
  539. loadfw(Ctlr *c, int *align)
  540. {
  541. ulong *f, *s, sz;
  542. int i;
  543. if((*align = whichfw(c->pcidev)) == 4*KiB){
  544. f = (ulong*)fw4k;
  545. sz = sizeof fw4k;
  546. }else{
  547. f = (ulong*)fw2k;
  548. sz = sizeof fw2k;
  549. }
  550. s = (ulong*)(c->ram + Fwoffset);
  551. for(i = 0; i < sz / 4; i++)
  552. s[i] = f[i];
  553. return sz & ~3;
  554. }
  555. static int
  556. bootfw(Ctlr *c)
  557. {
  558. int i, sz, align;
  559. ulong buf[16];
  560. Cmd* cmd;
  561. if((sz = loadfw(c, &align)) == 0)
  562. return 0;
  563. dprint("bootfw %d bytes ... ", sz);
  564. cmd = c->cmd;
  565. memset(buf, 0, sizeof buf);
  566. c->cmd->i[0] = 0;
  567. coherence();
  568. buf[0] = c->cprt >> 32; /* upper dma target address */
  569. buf[1] = c->cprt; /* lower */
  570. buf[2] = Noconf; /* writeback */
  571. buf[3] = Fwoffset + 8,
  572. buf[4] = sz - 8;
  573. buf[5] = 8;
  574. buf[6] = 0;
  575. prepcmd(buf, 7);
  576. coherence();
  577. memmove(c->ram + Fwsubmt, buf, sizeof buf);
  578. for(i = 0; i < 20; i++){
  579. if(cmd->i[0] == Noconf)
  580. break;
  581. delay(1);
  582. }
  583. dprint("[%lux %lux]", gbit32(cmd->c), gbit32(cmd->c+4));
  584. if(i == 20){
  585. print("m10g: cannot load fw\n");
  586. return -1;
  587. }
  588. dprint("\n");
  589. c->tx.segsz = align;
  590. return 0;
  591. }
  592. static int
  593. kickthebaby(Pcidev *p, Ctlr *c)
  594. {
  595. /* don't kick the baby! */
  596. ulong code;
  597. pcicfgw8(p, 0x10 + c->boot, 0x3);
  598. pcicfgw32(p, 0x18 + c->boot, 0xfffffff0);
  599. code = pcicfgr32(p, 0x14 + c->boot);
  600. dprint("reboot status = %lux\n", code);
  601. if(code != 0xfffffff0)
  602. return -1;
  603. return 0;
  604. }
  605. typedef struct {
  606. uchar len[4];
  607. uchar type[4];
  608. char version[128];
  609. uchar globals[4];
  610. uchar ramsz[4];
  611. uchar specs[4];
  612. uchar specssz[4];
  613. } Fwhdr;
  614. enum {
  615. Tmx = 0x4d582020,
  616. Tpcie = 0x70636965,
  617. Teth = 0x45544820,
  618. Tmcp0 = 0x4d435030,
  619. };
  620. static char *
  621. fwtype(ulong type)
  622. {
  623. switch(type){
  624. case Tmx:
  625. return "mx";
  626. case Tpcie:
  627. return "PCIe";
  628. case Teth:
  629. return "eth";
  630. case Tmcp0:
  631. return "mcp0";
  632. }
  633. return "*GOK*";
  634. }
  635. static int
  636. chkfw(Ctlr *c)
  637. {
  638. ulong off, type;
  639. Fwhdr *h;
  640. off = gbit32(c->ram+0x3c);
  641. dprint("firmware %lux\n", off);
  642. if((off&3) || off + sizeof *h > c->ramsz){
  643. print("!m10g: bad firmware %lux\n", off);
  644. return -1;
  645. }
  646. h = (Fwhdr*)(c->ram + off);
  647. type = gbit32(h->type);
  648. dprint("\t" "type %s\n", fwtype(type));
  649. dprint("\t" "vers %s\n", h->version);
  650. dprint("\t" "ramsz %lux\n", gbit32(h->ramsz));
  651. if(type != Teth){
  652. print("!m10g: bad card type %s\n", fwtype(type));
  653. return -1;
  654. }
  655. return bootfw(c) || rdmacmd(c, 0);
  656. }
  657. static int
  658. reset(Ether *e, Ctlr *c)
  659. {
  660. ulong i, sz;
  661. if(waserror()){
  662. print("m10g: reset error\n");
  663. nexterror();
  664. return -1;
  665. }
  666. chkfw(c);
  667. cmd(c, Creset, 0);
  668. cmd(c, CSintrqsz, c->done.n * sizeof *c->done.entry);
  669. cmd(c, CSintrqdma, c->done.busaddr);
  670. c->irqack = (ulong*)(c->ram + cmd(c, CGirqackoff, 0));
  671. /* required only if we're not doing msi? */
  672. c->irqdeass = (ulong*)(c->ram + cmd(c, CGirqdeassoff, 0));
  673. /* this is the driver default, why fiddle with this? */
  674. c->coal = (ulong*)(c->ram + cmd(c, CGcoaloff, 0));
  675. *c->coal = pbit32(25);
  676. dprint("dma stats:\n");
  677. rdmacmd(c, 1);
  678. sz = c->tx.segsz;
  679. i = dmatestcmd(c, DMAread, c->done.busaddr, sz);
  680. print("\t" "read: %lud MB/s\n", ((i>>16)*sz*2) / (i&0xffff));
  681. i = dmatestcmd(c, DMAwrite, c->done.busaddr, sz);
  682. print("\t" "write: %lud MB/s\n", ((i>>16)*sz*2) / (i&0xffff));
  683. i = dmatestcmd(c, DMAwrite|DMAread, c->done.busaddr, sz);
  684. print("\t" "r/w: %lud MB/s\n", ((i>>16)*sz*2*2) / (i&0xffff));
  685. memset(c->done.entry, 0, c->done.n * sizeof *c->done.entry);
  686. maccmd(c, CSmac, c->ra);
  687. // cmd(c, Cnopromisc, 0);
  688. cmd(c, Cenablefc, 0);
  689. e->maxmtu = Maxmtu;
  690. cmd(c, CSmtu, e->maxmtu);
  691. dprint("CSmtu %d...\n", e->maxmtu);
  692. poperror();
  693. return 0;
  694. }
  695. static void
  696. ctlrfree(Ctlr *c)
  697. {
  698. /* free up all the Block*s, too */
  699. free(c->tx.host);
  700. free(c->sm.host);
  701. free(c->bg.host);
  702. free(c->cmd);
  703. free(c->done.entry);
  704. free(c->stats);
  705. free(c);
  706. }
  707. static int
  708. setmem(Pcidev *p, Ctlr *c)
  709. {
  710. ulong i;
  711. uvlong raddr;
  712. Done *d;
  713. void *mem;
  714. c->tx.segsz = 2048;
  715. c->ramsz = 2*MiB - (2*48*KiB + 32*KiB) - 0x100;
  716. if(c->ramsz > p->mem[0].size)
  717. return -1;
  718. raddr = p->mem[0].bar & ~0x0F;
  719. mem = vmap(raddr, p->mem[0].size);
  720. if(mem == nil){
  721. print("m10g: can't map %8.8lux\n", p->mem[0].bar);
  722. return -1;
  723. }
  724. dprint("%llux <- vmap(mem[0].size = %ux)\n", raddr, p->mem[0].size);
  725. c->port = raddr;
  726. c->ram = mem;
  727. c->cmd = malign(sizeof *c->cmd);
  728. c->cprt = PCIWADDR(c->cmd);
  729. d = &c->done;
  730. d->n = Maxslots;
  731. d->m = d->n - 1;
  732. i = d->n * sizeof *d->entry;
  733. d->entry = malign(i);
  734. memset(d->entry, 0, i);
  735. d->busaddr = PCIWADDR(d->entry);
  736. c->stats = malign(sizeof *c->stats);
  737. memset(c->stats, 0, sizeof *c->stats);
  738. c->statsprt = PCIWADDR(c->stats);
  739. memmove(c->eprom, c->ram + c->ramsz - Epromsz, Epromsz-2);
  740. return setpcie(p) || parseeprom(c);
  741. }
  742. static Rx*
  743. whichrx(Ctlr *c, int sz)
  744. {
  745. if(sz <= smpool.size)
  746. return &c->sm;
  747. return &c->bg;
  748. }
  749. static Block*
  750. balloc(Rx* rx)
  751. {
  752. Block *b;
  753. ilock(rx->pool);
  754. if((b = rx->pool->head) != nil){
  755. rx->pool->head = b->next;
  756. b->next = nil;
  757. rx->pool->n--;
  758. }
  759. iunlock(rx->pool);
  760. return b;
  761. }
  762. static void
  763. smbfree(Block *b)
  764. {
  765. Bpool *p;
  766. b->rp = b->wp = (uchar*)PGROUND((uintptr)b->base);
  767. p = &smpool;
  768. ilock(p);
  769. b->next = p->head;
  770. p->head = b;
  771. p->n++;
  772. p->cnt++;
  773. iunlock(p);
  774. }
  775. static void
  776. bgbfree(Block *b)
  777. {
  778. Bpool *p;
  779. b->rp = b->wp = (uchar*)PGROUND((uintptr)b->base);
  780. p = &bgpool;
  781. ilock(p);
  782. b->next = p->head;
  783. p->head = b;
  784. p->n++;
  785. p->cnt++;
  786. iunlock(p);
  787. }
  788. static void
  789. replenish(Rx *rx)
  790. {
  791. ulong buf[16], i, idx, e;
  792. Bpool *p;
  793. Block *b;
  794. p = rx->pool;
  795. if(p->n < 8)
  796. return;
  797. memset(buf, 0, sizeof buf);
  798. e = (rx->i - rx->cnt) & ~7;
  799. e += rx->n;
  800. while(p->n >= 8 && e){
  801. idx = rx->cnt & rx->m;
  802. for(i = 0; i < 8; i++){
  803. b = balloc(rx);
  804. buf[i*2] = pbit32((uvlong)PCIWADDR(b->wp) >> 32);
  805. buf[i*2+1] = pbit32(PCIWADDR(b->wp));
  806. rx->host[idx+i] = b;
  807. assert(b);
  808. }
  809. memmove(rx->lanai + 2*idx, buf, sizeof buf);
  810. coherence();
  811. rx->cnt += 8;
  812. e -= 8;
  813. }
  814. if(e && p->n > 7+1)
  815. print("should panic? pool->n = %d\n", p->n);
  816. }
  817. /*
  818. * future:
  819. * if (c->mtrr >= 0) {
  820. * c->tx.wcfifo = c->ram+0x200000;
  821. * c->sm.wcfifo = c->ram+0x300000;
  822. * c->bg.wcfifo = c->ram+0x340000;
  823. * }
  824. */
  825. static int
  826. nextpow(int j)
  827. {
  828. int i;
  829. for(i = 0; j > (1 << i); i++)
  830. ;
  831. return 1 << i;
  832. }
  833. static void*
  834. emalign(int sz)
  835. {
  836. void *v;
  837. v = malign(sz);
  838. if(v == nil)
  839. error(Enomem);
  840. memset(v, 0, sz);
  841. return v;
  842. }
  843. static void
  844. open0(Ether *e, Ctlr *c)
  845. {
  846. Block *b;
  847. int i, sz, entries;
  848. entries = cmd(c, CGsendrgsz, 0) / sizeof *c->tx.lanai;
  849. c->tx.lanai = (Send*)(c->ram + cmd(c, CGsendoff, 0));
  850. c->tx.host = emalign(entries * sizeof *c->tx.host);
  851. c->tx.bring = emalign(entries * sizeof *c->tx.bring);
  852. c->tx.n = entries;
  853. c->tx.m = entries-1;
  854. entries = cmd(c, CGrxrgsz, 0)/8;
  855. c->sm.pool = &smpool;
  856. cmd(c, CSsmallsz, c->sm.pool->size);
  857. c->sm.lanai = (ulong*)(c->ram + cmd(c, CGsmallrxoff, 0));
  858. c->sm.n = entries;
  859. c->sm.m = entries-1;
  860. c->sm.host = emalign(entries * sizeof *c->sm.host);
  861. c->bg.pool = &bgpool;
  862. c->bg.pool->size = nextpow(2 + e->maxmtu); /* 2-byte alignment pad */
  863. cmd(c, CSbigsz, c->bg.pool->size);
  864. c->bg.lanai = (ulong*)(c->ram + cmd(c, CGbigrxoff, 0));
  865. c->bg.n = entries;
  866. c->bg.m = entries-1;
  867. c->bg.host = emalign(entries * sizeof *c->bg.host);
  868. sz = c->sm.pool->size + BY2PG;
  869. for(i = 0; i < c->sm.n; i++){
  870. if((b = allocb(sz)) == 0)
  871. break;
  872. b->free = smbfree;
  873. freeb(b);
  874. }
  875. sz = c->bg.pool->size + BY2PG;
  876. for(i = 0; i < c->bg.n; i++){
  877. if((b = allocb(sz)) == 0)
  878. break;
  879. b->free = bgbfree;
  880. freeb(b);
  881. }
  882. cmd(c, CSstatsdma, c->statsprt);
  883. c->linkstat = ~0;
  884. c->nrdma = 15;
  885. cmd(c, Cetherup, 0);
  886. }
  887. static Block*
  888. nextblock(Ctlr *c)
  889. {
  890. uint i;
  891. ushort l, k;
  892. Block *b;
  893. Done *d;
  894. Rx *rx;
  895. Slot *s;
  896. Slotparts *sp;
  897. d = &c->done;
  898. s = d->entry;
  899. i = d->i & d->m;
  900. sp = (Slotparts *)(s + i);
  901. l = sp->len;
  902. if(l == 0)
  903. return 0;
  904. k = sp->cksum;
  905. s[i] = 0;
  906. d->i++;
  907. l = gbit16((uchar*)&l);
  908. //dprint("nextb: i=%d l=%d\n", d->i, l);
  909. rx = whichrx(c, l);
  910. if(rx->i >= rx->cnt){
  911. iprint("m10g: overrun\n");
  912. return 0;
  913. }
  914. i = rx->i & rx->m;
  915. b = rx->host[i];
  916. rx->host[i] = 0;
  917. if(b == 0){
  918. iprint("m10g: error rx to no block. memory is hosed.\n");
  919. return 0;
  920. }
  921. rx->i++;
  922. b->flag |= Bipck|Btcpck|Budpck;
  923. b->checksum = k;
  924. b->rp += 2;
  925. b->wp += 2+l;
  926. b->lim = b->wp; /* lie like a dog. */
  927. return b;
  928. }
  929. static int
  930. rxcansleep(void *v)
  931. {
  932. Ctlr *c;
  933. Slot *s;
  934. Slotparts *sp;
  935. Done *d;
  936. c = v;
  937. d = &c->done;
  938. s = c->done.entry;
  939. sp = (Slotparts *)(s + (d->i & d->m));
  940. if(sp->len != 0)
  941. return -1;
  942. c->irqack[0] = pbit32(3);
  943. return 0;
  944. }
  945. static void
  946. m10rx(void *v)
  947. {
  948. Ether *e;
  949. Ctlr *c;
  950. Block *b;
  951. e = v;
  952. c = e->ctlr;
  953. for(;;){
  954. replenish(&c->sm);
  955. replenish(&c->bg);
  956. sleep(&c->rxrendez, rxcansleep, c);
  957. while(b = nextblock(c))
  958. etheriq(e, b, 1);
  959. }
  960. }
  961. static void
  962. txcleanup(Tx *tx, ulong n)
  963. {
  964. Block *b;
  965. uint j, l, m;
  966. if(tx->npkt == n)
  967. return;
  968. l = 0;
  969. m = tx->m;
  970. /*
  971. * if tx->cnt == tx->i, yet tx->npkt == n-1, we just
  972. * caught ourselves and myricom card updating.
  973. */
  974. for(;; tx->cnt++){
  975. j = tx->cnt & tx->m;
  976. if(b = tx->bring[j]){
  977. tx->bring[j] = 0;
  978. tx->nbytes += BLEN(b);
  979. freeb(b);
  980. if(++tx->npkt == n)
  981. return;
  982. }
  983. if(tx->cnt == tx->i)
  984. return;
  985. if(l++ == m){
  986. iprint("tx ovrun: %lud %lud\n", n, tx->npkt);
  987. return;
  988. }
  989. }
  990. }
  991. static int
  992. txcansleep(void *v)
  993. {
  994. Ctlr *c;
  995. c = v;
  996. if(c->tx.cnt != c->tx.i && c->tx.npkt != gbit32(c->stats->txcnt))
  997. return -1;
  998. return 0;
  999. }
  1000. static void
  1001. txproc(void *v)
  1002. {
  1003. Ether *e;
  1004. Ctlr *c;
  1005. Tx *tx;
  1006. e = v;
  1007. c = e->ctlr;
  1008. tx = &c->tx;
  1009. for(;;){
  1010. sleep(&c->txrendez, txcansleep, c);
  1011. txcleanup(tx, gbit32(c->stats->txcnt));
  1012. }
  1013. }
  1014. static void
  1015. submittx(Tx *tx, int n)
  1016. {
  1017. Send *l, *h;
  1018. int i0, i, m;
  1019. m = tx->m;
  1020. i0 = tx->i & m;
  1021. l = tx->lanai;
  1022. h = tx->host;
  1023. for(i = n-1; i >= 0; i--)
  1024. memmove(l+(i + i0 & m), h+(i + i0 & m), sizeof *h);
  1025. tx->i += n;
  1026. // coherence();
  1027. }
  1028. static int
  1029. nsegments(Block *b, int segsz)
  1030. {
  1031. uintptr bus, end, slen, len;
  1032. int i;
  1033. bus = PCIWADDR(b->rp);
  1034. i = 0;
  1035. for(len = BLEN(b); len; len -= slen){
  1036. end = bus + segsz & ~(segsz-1);
  1037. slen = end - bus;
  1038. if(slen > len)
  1039. slen = len;
  1040. bus += slen;
  1041. i++;
  1042. }
  1043. return i;
  1044. }
  1045. static void
  1046. m10gtransmit(Ether *e)
  1047. {
  1048. ushort slen;
  1049. ulong i, cnt, rdma, nseg, count, end, bus, len, segsz;
  1050. uchar flags;
  1051. Block *b;
  1052. Ctlr *c;
  1053. Send *s, *s0, *s0m8;
  1054. Tx *tx;
  1055. c = e->ctlr;
  1056. tx = &c->tx;
  1057. segsz = tx->segsz;
  1058. qlock(tx);
  1059. count = 0;
  1060. s = tx->host + (tx->i & tx->m);
  1061. cnt = tx->cnt;
  1062. s0 = tx->host + (cnt & tx->m);
  1063. s0m8 = tx->host + ((cnt - 8) & tx->m);
  1064. i = tx->i;
  1065. for(; s >= s0 || s < s0m8; i += nseg){
  1066. if((b = qget(e->oq)) == nil)
  1067. break;
  1068. flags = SFfirst|SFnotso;
  1069. if((len = BLEN(b)) < 1520)
  1070. flags |= SFsmall;
  1071. rdma = nseg = nsegments(b, segsz);
  1072. bus = PCIWADDR(b->rp);
  1073. for(; len; len -= slen){
  1074. end = (bus + segsz) & ~(segsz-1);
  1075. slen = end - bus;
  1076. if(slen > len)
  1077. slen = len;
  1078. s->low = pbit32(bus);
  1079. s->len = pbit16(slen);
  1080. s->nrdma = rdma;
  1081. s->flags = flags;
  1082. bus += slen;
  1083. if(++s == tx->host + tx->n)
  1084. s = tx->host;
  1085. count++;
  1086. flags &= ~SFfirst;
  1087. rdma = 1;
  1088. }
  1089. tx->bring[(i + nseg - 1) & tx->m] = b;
  1090. if(1 || count > 0){
  1091. submittx(tx, count);
  1092. count = 0;
  1093. cnt = tx->cnt;
  1094. s0 = tx->host + (cnt & tx->m);
  1095. s0m8 = tx->host + ((cnt - 8) & tx->m);
  1096. }
  1097. }
  1098. qunlock(tx);
  1099. }
  1100. static void
  1101. checkstats(Ether *e, Ctlr *c, Stats *s)
  1102. {
  1103. ulong i;
  1104. if(s->updated == 0)
  1105. return;
  1106. i = gbit32(s->linkstat);
  1107. if(c->linkstat != i){
  1108. e->link = i;
  1109. if(c->linkstat = i)
  1110. dprint("m10g: link up\n");
  1111. else
  1112. dprint("m10g: link down\n");
  1113. }
  1114. i = gbit32(s->nrdma);
  1115. if(i != c->nrdma){
  1116. dprint("m10g: rdma timeout %ld\n", i);
  1117. c->nrdma = i;
  1118. }
  1119. }
  1120. static void
  1121. waitintx(Ctlr *c)
  1122. {
  1123. int i;
  1124. for(i = 0; i < 1024*1024; i++){
  1125. if(c->stats->valid == 0)
  1126. break;
  1127. coherence();
  1128. }
  1129. }
  1130. static void
  1131. m10ginterrupt(Ureg *, void *v)
  1132. {
  1133. Ether *e;
  1134. Ctlr *c;
  1135. e = v;
  1136. c = e->ctlr;
  1137. if(c->state != Runed || c->stats->valid == 0) /* not ready for us? */
  1138. return;
  1139. if(c->stats->valid & 1)
  1140. wakeup(&c->rxrendez);
  1141. if(gbit32(c->stats->txcnt) != c->tx.npkt)
  1142. wakeup(&c->txrendez);
  1143. if(c->msi == 0)
  1144. *c->irqdeass = 0;
  1145. else
  1146. c->stats->valid = 0;
  1147. waitintx(c);
  1148. checkstats(e, c, c->stats);
  1149. c->irqack[1] = pbit32(3);
  1150. }
  1151. static void
  1152. m10gattach(Ether *e)
  1153. {
  1154. Ctlr *c;
  1155. char name[12];
  1156. dprint("m10gattach\n");
  1157. qlock(e->ctlr);
  1158. c = e->ctlr;
  1159. if(c->state != Detached){
  1160. qunlock(c);
  1161. return;
  1162. }
  1163. if(waserror()){
  1164. c->state = Detached;
  1165. qunlock(c);
  1166. nexterror();
  1167. }
  1168. reset(e, c);
  1169. c->state = Attached;
  1170. open0(e, c);
  1171. if(c->kprocs == 0){
  1172. c->kprocs++;
  1173. snprint(name, sizeof name, "#l%drxproc", e->ctlrno);
  1174. kproc(name, m10rx, e);
  1175. snprint(name, sizeof name, "#l%dtxproc", e->ctlrno);
  1176. kproc(name, txproc, e);
  1177. }
  1178. c->state = Runed;
  1179. qunlock(c);
  1180. poperror();
  1181. }
  1182. static int
  1183. m10gdetach(Ctlr *c)
  1184. {
  1185. dprint("m10gdetach\n");
  1186. // reset(e->ctlr);
  1187. vunmap(c->ram, c->pcidev->mem[0].size);
  1188. ctlrfree(c);
  1189. return -1;
  1190. }
  1191. static int
  1192. lstcount(Block *b)
  1193. {
  1194. int i;
  1195. i = 0;
  1196. for(; b; b = b->next)
  1197. i++;
  1198. return i;
  1199. }
  1200. static long
  1201. m10gifstat(Ether *e, void *v, long n, ulong off)
  1202. {
  1203. int l, lim;
  1204. char *p;
  1205. Ctlr *c;
  1206. Stats s;
  1207. c = e->ctlr;
  1208. lim = 2*READSTR-1;
  1209. p = malloc(lim+1);
  1210. l = 0;
  1211. /* no point in locking this because this is done via dma. */
  1212. memmove(&s, c->stats, sizeof s);
  1213. // l +=
  1214. snprint(p+l, lim,
  1215. "txcnt = %lud\n" "linkstat = %lud\n" "dlink = %lud\n"
  1216. "derror = %lud\n" "drunt = %lud\n" "doverrun = %lud\n"
  1217. "dnosm = %lud\n" "dnobg = %lud\n" "nrdma = %lud\n"
  1218. "txstopped = %ud\n" "down = %ud\n" "updated = %ud\n"
  1219. "valid = %ud\n\n"
  1220. "tx pkt = %lud\n" "tx bytes = %lld\n"
  1221. "tx cnt = %ud\n" "tx n = %ud\n" "tx i = %ud\n"
  1222. "sm cnt = %ud\n" "sm i = %ud\n" "sm n = %ud\n"
  1223. "sm lst = %ud\n"
  1224. "bg cnt = %ud\n" "bg i = %ud\n" "bg n = %ud\n"
  1225. "bg lst = %ud\n"
  1226. "segsz = %lud\n" "coal = %lud\n",
  1227. gbit32(s.txcnt), gbit32(s.linkstat), gbit32(s.dlink),
  1228. gbit32(s.derror), gbit32(s.drunt), gbit32(s.doverrun),
  1229. gbit32(s.dnosm), gbit32(s.dnobg), gbit32(s.nrdma),
  1230. s.txstopped, s.down, s.updated, s.valid,
  1231. c->tx.npkt, c->tx.nbytes,
  1232. c->tx.cnt, c->tx.n, c->tx.i,
  1233. c->sm.cnt, c->sm.i, c->sm.pool->n, lstcount(c->sm.pool->head),
  1234. c->bg.cnt, c->bg.i, c->bg.pool->n, lstcount(c->bg.pool->head),
  1235. c->tx.segsz, gbit32((uchar*)c->coal));
  1236. n = readstr(off, v, n, p);
  1237. free(p);
  1238. return n;
  1239. }
  1240. //static void
  1241. //summary(Ether *e)
  1242. //{
  1243. // char *buf;
  1244. // int n, i, j;
  1245. //
  1246. // if(e == 0)
  1247. // return;
  1248. // buf = malloc(n=250);
  1249. // if(buf == 0)
  1250. // return;
  1251. //
  1252. // snprint(buf, n, "oq\n");
  1253. // qsummary(e->oq, buf+3, n-3-1);
  1254. // iprint("%s", buf);
  1255. //
  1256. // if(e->f) for(i = 0; e->f[i]; i++){
  1257. // j = snprint(buf, n, "f%d %d\n", i, e->f[i]->type);
  1258. // qsummary(e->f[i]->in, buf+j, n-j-1);
  1259. // print("%s", buf);
  1260. // }
  1261. //
  1262. // free(buf);
  1263. //}
  1264. static void
  1265. rxring(Ctlr *c)
  1266. {
  1267. Done *d;
  1268. Slot *s;
  1269. Slotparts *sp;
  1270. int i;
  1271. d = &c->done;
  1272. s = d->entry;
  1273. for(i = 0; i < d->n; i++) {
  1274. sp = (Slotparts *)(s + i);
  1275. if(sp->len)
  1276. iprint("s[%d] = %d\n", i, sp->len);
  1277. }
  1278. }
  1279. enum {
  1280. CMdebug,
  1281. CMcoal,
  1282. CMwakeup,
  1283. CMtxwakeup,
  1284. CMqsummary,
  1285. CMrxring,
  1286. };
  1287. static Cmdtab ctab[] = {
  1288. CMdebug, "debug", 2,
  1289. CMcoal, "coal", 2,
  1290. CMwakeup, "wakeup", 1,
  1291. CMtxwakeup, "txwakeup", 1,
  1292. // CMqsummary, "q", 1,
  1293. CMrxring, "rxring", 1,
  1294. };
  1295. static long
  1296. m10gctl(Ether *e, void *v, long n)
  1297. {
  1298. int i;
  1299. Cmdbuf *c;
  1300. Cmdtab *t;
  1301. dprint("m10gctl\n");
  1302. if(e->ctlr == nil)
  1303. error(Enonexist);
  1304. c = parsecmd(v, n);
  1305. if(waserror()){
  1306. free(c);
  1307. nexterror();
  1308. }
  1309. t = lookupcmd(c, ctab, nelem(ctab));
  1310. switch(t->index){
  1311. case CMdebug:
  1312. debug = (strcmp(c->f[1], "on") == 0);
  1313. break;
  1314. case CMcoal:
  1315. i = atoi(c->f[1]);
  1316. if(i < 0 || i > 1000)
  1317. error(Ebadarg);
  1318. *((Ctlr*)e->ctlr)->coal = pbit32(i);
  1319. break;
  1320. case CMwakeup:
  1321. wakeup(&((Ctlr*)e->ctlr)->rxrendez); /* you're kidding, right? */
  1322. break;
  1323. case CMtxwakeup:
  1324. wakeup(&((Ctlr*)e->ctlr)->txrendez); /* you're kidding, right? */
  1325. break;
  1326. // case CMqsummary:
  1327. // summary(e);
  1328. // break;
  1329. case CMrxring:
  1330. rxring(e->ctlr);
  1331. break;
  1332. default:
  1333. error(Ebadarg);
  1334. }
  1335. free(c);
  1336. poperror();
  1337. return n;
  1338. }
  1339. static void
  1340. m10gshutdown(Ether *e)
  1341. {
  1342. dprint("m10gshutdown\n");
  1343. m10gdetach(e->ctlr);
  1344. }
  1345. static void
  1346. m10gpromiscuous(void *v, int on)
  1347. {
  1348. Ether *e;
  1349. int i;
  1350. dprint("m10gpromiscuous\n");
  1351. e = v;
  1352. if(on)
  1353. i = Cpromisc;
  1354. else
  1355. i = Cnopromisc;
  1356. cmd(e->ctlr, i, 0);
  1357. }
  1358. static int mcctab[] = { CSleavemc, CSjoinmc };
  1359. static char *mcntab[] = { "leave", "join" };
  1360. static void
  1361. m10gmulticast(void *v, uchar *ea, int on)
  1362. {
  1363. Ether *e;
  1364. int i;
  1365. dprint("m10gmulticast\n");
  1366. e = v;
  1367. if((i = maccmd(e->ctlr, mcctab[on], ea)) != 0)
  1368. print("m10g: can't %s %E: %d\n", mcntab[on], ea, i);
  1369. }
  1370. static void
  1371. m10gpci(void)
  1372. {
  1373. Pcidev *p;
  1374. Ctlr *t, *c;
  1375. t = 0;
  1376. for(p = 0; p = pcimatch(p, 0x14c1, 0x0008); ){
  1377. c = malloc(sizeof *c);
  1378. if(c == nil)
  1379. continue;
  1380. c->pcidev = p;
  1381. c->id = p->did<<16 | p->vid;
  1382. c->boot = pcicap(p, PciCapVND);
  1383. // kickthebaby(p, c);
  1384. pcisetbme(p);
  1385. if(setmem(p, c) == -1){
  1386. print("m10g failed\n");
  1387. free(c);
  1388. /* cleanup */
  1389. continue;
  1390. }
  1391. if(t)
  1392. t->next = c;
  1393. else
  1394. ctlrs = c;
  1395. t = c;
  1396. }
  1397. }
  1398. static int
  1399. m10gpnp(Ether *e)
  1400. {
  1401. Ctlr *c;
  1402. if(ctlrs == nil)
  1403. m10gpci();
  1404. for(c = ctlrs; c != nil; c = c->next)
  1405. if(c->active)
  1406. continue;
  1407. else if(e->port == 0 || e->port == c->port)
  1408. break;
  1409. if(c == nil)
  1410. return -1;
  1411. c->active = 1;
  1412. e->ctlr = c;
  1413. e->port = c->port;
  1414. e->irq = c->pcidev->intl;
  1415. e->tbdf = c->pcidev->tbdf;
  1416. e->mbps = 10000;
  1417. memmove(e->ea, c->ra, Eaddrlen);
  1418. e->attach = m10gattach;
  1419. e->detach = m10gshutdown;
  1420. e->transmit = m10gtransmit;
  1421. e->interrupt = m10ginterrupt;
  1422. e->ifstat = m10gifstat;
  1423. e->ctl = m10gctl;
  1424. // e->power = m10gpower;
  1425. e->shutdown = m10gshutdown;
  1426. e->arg = e;
  1427. e->promiscuous = m10gpromiscuous;
  1428. e->multicast = m10gmulticast;
  1429. return 0;
  1430. }
  1431. void
  1432. etherm10glink(void)
  1433. {
  1434. addethercard("m10g", m10gpnp);
  1435. }