io.h 9.2 KB

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  1. #define X86STEPPING(x) ((x) & 0x0F)
  2. #define X86MODEL(x) (((x)>>4) & 0x0F)
  3. #define X86FAMILY(x) (((x)>>8) & 0x0F)
  4. enum {
  5. VectorNMI = 2, /* non-maskable interrupt */
  6. VectorBPT = 3, /* breakpoint */
  7. VectorUD = 6, /* invalid opcode exception */
  8. VectorCNA = 7, /* coprocessor not available */
  9. Vector2F = 8, /* double fault */
  10. VectorCSO = 9, /* coprocessor segment overrun */
  11. VectorPF = 14, /* page fault */
  12. Vector15 = 15, /* reserved */
  13. VectorCERR = 16, /* coprocessor error */
  14. VectorPIC = 32, /* external i8259 interrupts */
  15. IrqCLOCK = 0,
  16. IrqKBD = 1,
  17. IrqUART1 = 3,
  18. IrqUART0 = 4,
  19. IrqPCMCIA = 5,
  20. IrqFLOPPY = 6,
  21. IrqLPT = 7,
  22. IrqIRQ7 = 7,
  23. IrqAUX = 12, /* PS/2 port */
  24. IrqIRQ13 = 13, /* coprocessor on 386 */
  25. IrqATA0 = 14,
  26. IrqATA1 = 15,
  27. MaxIrqPIC = 15,
  28. VectorLAPIC = VectorPIC+16, /* local APIC interrupts */
  29. IrqLINT0 = 16, /* LINT[01] must be offsets 0 and 1 */
  30. IrqLINT1 = 17,
  31. IrqTIMER = 18,
  32. IrqERROR = 19,
  33. IrqPCINT = 20,
  34. IrqSPURIOUS = 31, /* must have bits [3-0] == 0x0F */
  35. MaxIrqLAPIC = 31,
  36. VectorSYSCALL = 64,
  37. VectorAPIC = 65, /* external APIC interrupts */
  38. MaxVectorAPIC = 255,
  39. };
  40. typedef struct Vctl {
  41. Vctl* next; /* handlers on this vector */
  42. char name[KNAMELEN]; /* of driver */
  43. int isintr; /* interrupt or fault/trap */
  44. int irq;
  45. int tbdf;
  46. int (*isr)(int); /* get isr bit for this irq */
  47. int (*eoi)(int); /* eoi */
  48. void (*f)(Ureg*, void*); /* handler to call */
  49. void* a; /* argument to call it with */
  50. } Vctl;
  51. enum {
  52. BusCBUS = 0, /* Corollary CBUS */
  53. BusCBUSII, /* Corollary CBUS II */
  54. BusEISA, /* Extended ISA */
  55. BusFUTURE, /* IEEE Futurebus */
  56. BusINTERN, /* Internal bus */
  57. BusISA, /* Industry Standard Architecture */
  58. BusMBI, /* Multibus I */
  59. BusMBII, /* Multibus II */
  60. BusMCA, /* Micro Channel Architecture */
  61. BusMPI, /* MPI */
  62. BusMPSA, /* MPSA */
  63. BusNUBUS, /* Apple Macintosh NuBus */
  64. BusPCI, /* Peripheral Component Interconnect */
  65. BusPCMCIA, /* PC Memory Card International Association */
  66. BusTC, /* DEC TurboChannel */
  67. BusVL, /* VESA Local bus */
  68. BusVME, /* VMEbus */
  69. BusXPRESS, /* Express System Bus */
  70. };
  71. #define MKBUS(t,b,d,f) (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
  72. #define BUSFNO(tbdf) (((tbdf)>>8)&0x07)
  73. #define BUSDNO(tbdf) (((tbdf)>>11)&0x1F)
  74. #define BUSBNO(tbdf) (((tbdf)>>16)&0xFF)
  75. #define BUSTYPE(tbdf) ((tbdf)>>24)
  76. #define BUSBDF(tbdf) ((tbdf)&0x00FFFF00)
  77. #define BUSUNKNOWN (-1)
  78. enum {
  79. MaxEISA = 16,
  80. CfgEISA = 0xC80,
  81. };
  82. /*
  83. * PCI support code.
  84. */
  85. enum { /* type 0 & type 1 pre-defined header */
  86. PciVID = 0x00, /* vendor ID */
  87. PciDID = 0x02, /* device ID */
  88. PciPCR = 0x04, /* command */
  89. PciPSR = 0x06, /* status */
  90. PciRID = 0x08, /* revision ID */
  91. PciCCRp = 0x09, /* programming interface class code */
  92. PciCCRu = 0x0A, /* sub-class code */
  93. PciCCRb = 0x0B, /* base class code */
  94. PciCLS = 0x0C, /* cache line size */
  95. PciLTR = 0x0D, /* latency timer */
  96. PciHDT = 0x0E, /* header type */
  97. PciBST = 0x0F, /* BIST */
  98. PciBAR0 = 0x10, /* base address */
  99. PciBAR1 = 0x14,
  100. PciINTL = 0x3C, /* interrupt line */
  101. PciINTP = 0x3D, /* interrupt pin */
  102. };
  103. /* ccrb (base class code) values; controller types */
  104. enum {
  105. Pcibcpci1 = 0, /* pci 1.0; no class codes defined */
  106. Pcibcstore = 1, /* mass storage */
  107. Pcibcnet = 2, /* network */
  108. Pcibcdisp = 3, /* display */
  109. Pcibcmmedia = 4, /* multimedia */
  110. Pcibcmem = 5, /* memory */
  111. Pcibcbridge = 6, /* bridge */
  112. Pcibccomm = 7, /* simple comms (e.g., serial) */
  113. Pcibcbasesys = 8, /* base system */
  114. Pcibcinput = 9, /* input */
  115. Pcibcdock = 0xa, /* docking stations */
  116. Pcibcproc = 0xb, /* processors */
  117. Pcibcserial = 0xc, /* serial bus (e.g., USB) */
  118. Pcibcwireless = 0xd, /* wireless */
  119. Pcibcintell = 0xe, /* intelligent i/o */
  120. Pcibcsatcom = 0xf, /* satellite comms */
  121. Pcibccrypto = 0x10, /* encryption/decryption */
  122. Pcibcdacq = 0x11, /* data acquisition & signal proc. */
  123. };
  124. /* ccru (sub-class code) values; common cases only */
  125. enum {
  126. /* mass storage */
  127. Pciscscsi = 0, /* SCSI */
  128. Pciscide = 1, /* IDE (ATA) */
  129. /* network */
  130. Pciscether = 0, /* Ethernet */
  131. /* display */
  132. Pciscvga = 0, /* VGA */
  133. Pciscxga = 1, /* XGA */
  134. Pcisc3d = 2, /* 3D */
  135. /* bridges */
  136. Pcischostpci = 0, /* host/pci */
  137. Pciscpcicpci = 1, /* pci/pci */
  138. /* simple comms */
  139. Pciscserial = 0, /* 16450, etc. */
  140. Pciscmultiser = 1, /* multiport serial */
  141. /* serial bus */
  142. Pciscusb = 3, /* USB */
  143. };
  144. enum { /* type 0 pre-defined header */
  145. PciCIS = 0x28, /* cardbus CIS pointer */
  146. PciSVID = 0x2C, /* subsystem vendor ID */
  147. PciSID = 0x2E, /* cardbus CIS pointer */
  148. PciEBAR0 = 0x30, /* expansion ROM base address */
  149. PciMGNT = 0x3E, /* burst period length */
  150. PciMLT = 0x3F, /* maximum latency between bursts */
  151. };
  152. enum { /* type 1 pre-defined header */
  153. PciPBN = 0x18, /* primary bus number */
  154. PciSBN = 0x19, /* secondary bus number */
  155. PciUBN = 0x1A, /* subordinate bus number */
  156. PciSLTR = 0x1B, /* secondary latency timer */
  157. PciIBR = 0x1C, /* I/O base */
  158. PciILR = 0x1D, /* I/O limit */
  159. PciSPSR = 0x1E, /* secondary status */
  160. PciMBR = 0x20, /* memory base */
  161. PciMLR = 0x22, /* memory limit */
  162. PciPMBR = 0x24, /* prefetchable memory base */
  163. PciPMLR = 0x26, /* prefetchable memory limit */
  164. PciPUBR = 0x28, /* prefetchable base upper 32 bits */
  165. PciPULR = 0x2C, /* prefetchable limit upper 32 bits */
  166. PciIUBR = 0x30, /* I/O base upper 16 bits */
  167. PciIULR = 0x32, /* I/O limit upper 16 bits */
  168. PciEBAR1 = 0x28, /* expansion ROM base address */
  169. PciBCR = 0x3E, /* bridge control register */
  170. };
  171. enum { /* type 2 pre-defined header */
  172. PciCBExCA = 0x10,
  173. PciCBSPSR = 0x16,
  174. PciCBPBN = 0x18, /* primary bus number */
  175. PciCBSBN = 0x19, /* secondary bus number */
  176. PciCBUBN = 0x1A, /* subordinate bus number */
  177. PciCBSLTR = 0x1B, /* secondary latency timer */
  178. PciCBMBR0 = 0x1C,
  179. PciCBMLR0 = 0x20,
  180. PciCBMBR1 = 0x24,
  181. PciCBMLR1 = 0x28,
  182. PciCBIBR0 = 0x2C, /* I/O base */
  183. PciCBILR0 = 0x30, /* I/O limit */
  184. PciCBIBR1 = 0x34, /* I/O base */
  185. PciCBILR1 = 0x38, /* I/O limit */
  186. PciCBSVID = 0x40, /* subsystem vendor ID */
  187. PciCBSID = 0x42, /* subsystem ID */
  188. PciCBLMBAR = 0x44, /* legacy mode base address */
  189. };
  190. typedef struct Pcisiz Pcisiz;
  191. struct Pcisiz
  192. {
  193. Pcidev* dev;
  194. int siz;
  195. int bar;
  196. };
  197. typedef struct Pcidev Pcidev;
  198. struct Pcidev
  199. {
  200. int tbdf; /* type+bus+device+function */
  201. ushort vid; /* vendor ID */
  202. ushort did; /* device ID */
  203. ushort pcr;
  204. uchar rid;
  205. uchar ccrp;
  206. uchar ccru;
  207. uchar ccrb;
  208. uchar cls;
  209. uchar ltr;
  210. struct {
  211. ulong bar; /* base address */
  212. int size;
  213. } mem[6];
  214. struct {
  215. ulong bar;
  216. int size;
  217. } rom;
  218. uchar intl; /* interrupt line */
  219. Pcidev* list;
  220. Pcidev* link; /* next device on this bno */
  221. Pcidev* bridge; /* down a bus */
  222. struct {
  223. ulong bar;
  224. int size;
  225. } ioa, mema;
  226. int pmrb; /* power management register block */
  227. };
  228. #define PCIWINDOW 0
  229. #define PCIWADDR(va) (PADDR(va)+PCIWINDOW)
  230. #define ISAWINDOW 0
  231. #define ISAWADDR(va) (PADDR(va)+ISAWINDOW)
  232. /* SMBus transactions */
  233. enum
  234. {
  235. SMBquick, /* sends address only */
  236. /* write */
  237. SMBsend, /* sends address and cmd */
  238. SMBbytewrite, /* sends address and cmd and 1 byte */
  239. SMBwordwrite, /* sends address and cmd and 2 bytes */
  240. /* read */
  241. SMBrecv, /* sends address, recvs 1 byte */
  242. SMBbyteread, /* sends address and cmd, recv's byte */
  243. SMBwordread, /* sends address and cmd, recv's 2 bytes */
  244. };
  245. typedef struct SMBus SMBus;
  246. struct SMBus {
  247. QLock; /* mutex */
  248. Rendez r; /* rendezvous point for completion interrupts */
  249. void *arg; /* implementation dependent */
  250. ulong base; /* port or memory base of smbus */
  251. int busy;
  252. void (*transact)(SMBus*, int, int, int, uchar*);
  253. };
  254. /*
  255. * PCMCIA support code.
  256. */
  257. typedef struct PCMslot PCMslot;
  258. typedef struct PCMconftab PCMconftab;
  259. /*
  260. * Map between ISA memory space and PCMCIA card memory space.
  261. */
  262. struct PCMmap {
  263. ulong ca; /* card address */
  264. ulong cea; /* card end address */
  265. ulong isa; /* ISA address */
  266. int len; /* length of the ISA area */
  267. int attr; /* attribute memory */
  268. int ref;
  269. };
  270. /* configuration table entry */
  271. struct PCMconftab
  272. {
  273. int index;
  274. ushort irqs; /* legal irqs */
  275. uchar irqtype;
  276. uchar bit16; /* true for 16 bit access */
  277. struct {
  278. ulong start;
  279. ulong len;
  280. } io[16];
  281. int nio;
  282. uchar vpp1;
  283. uchar vpp2;
  284. uchar memwait;
  285. ulong maxwait;
  286. ulong readywait;
  287. ulong otherwait;
  288. };
  289. /* a card slot */
  290. struct PCMslot
  291. {
  292. Lock;
  293. int ref;
  294. void *cp; /* controller for this slot */
  295. long memlen; /* memory length */
  296. uchar base; /* index register base */
  297. uchar slotno; /* slot number */
  298. /* status */
  299. uchar special; /* in use for a special device */
  300. uchar already; /* already inited */
  301. uchar occupied;
  302. uchar battery;
  303. uchar wrprot;
  304. uchar powered;
  305. uchar configed;
  306. uchar enabled;
  307. uchar busy;
  308. /* cis info */
  309. ulong msec; /* time of last slotinfo call */
  310. char verstr[512]; /* version string */
  311. int ncfg; /* number of configurations */
  312. struct {
  313. ushort cpresent; /* config registers present */
  314. ulong caddr; /* relative address of config registers */
  315. } cfg[8];
  316. int nctab; /* number of config table entries */
  317. PCMconftab ctab[8];
  318. PCMconftab *def; /* default conftab */
  319. /* memory maps */
  320. Lock mlock; /* lock down the maps */
  321. int time;
  322. PCMmap mmap[4]; /* maps, last is always for the kernel */
  323. };