mp.c 17 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "ureg.h"
  8. #include "mp.h"
  9. #include "apbootstrap.h"
  10. static Bus* mpbus;
  11. static Bus* mpbuslast;
  12. static int mpisabus = -1;
  13. static int mpeisabus = -1;
  14. extern int i8259elcr; /* mask of level-triggered interrupts */
  15. static Apic mpapic[MaxAPICNO+1];
  16. static int machno2apicno[MaxAPICNO+1]; /* inverse map: machno -> APIC ID */
  17. static Lock mprdthilock;
  18. static int mprdthi;
  19. static Ref mpvnoref; /* unique vector assignment */
  20. static int mpmachno = 1;
  21. static char* buses[] = {
  22. "CBUSI ",
  23. "CBUSII",
  24. "EISA ",
  25. "FUTURE",
  26. "INTERN",
  27. "ISA ",
  28. "MBI ",
  29. "MBII ",
  30. "MCA ",
  31. "MPI ",
  32. "MPSA ",
  33. "NUBUS ",
  34. "PCI ",
  35. "PCMCIA",
  36. "TC ",
  37. "VL ",
  38. "VME ",
  39. "XPRESS",
  40. 0,
  41. };
  42. static Apic*
  43. mkprocessor(PCMPprocessor* p)
  44. {
  45. Apic *apic;
  46. if(!(p->flags & PcmpEN) || p->apicno > MaxAPICNO)
  47. return 0;
  48. apic = &mpapic[p->apicno];
  49. apic->type = PcmpPROCESSOR;
  50. apic->apicno = p->apicno;
  51. apic->flags = p->flags;
  52. apic->lintr[0] = ApicIMASK;
  53. apic->lintr[1] = ApicIMASK;
  54. if(p->flags & PcmpBP){
  55. machno2apicno[0] = p->apicno;
  56. apic->machno = 0;
  57. }
  58. else{
  59. machno2apicno[mpmachno] = p->apicno;
  60. apic->machno = mpmachno;
  61. mpmachno++;
  62. }
  63. return apic;
  64. }
  65. static Bus*
  66. mkbus(PCMPbus* p)
  67. {
  68. Bus *bus;
  69. int i;
  70. for(i = 0; buses[i]; i++){
  71. if(strncmp(buses[i], p->string, sizeof(p->string)) == 0)
  72. break;
  73. }
  74. if(buses[i] == 0)
  75. return 0;
  76. bus = xalloc(sizeof(Bus));
  77. if(mpbus)
  78. mpbuslast->next = bus;
  79. else
  80. mpbus = bus;
  81. mpbuslast = bus;
  82. bus->type = i;
  83. bus->busno = p->busno;
  84. if(bus->type == BusEISA){
  85. bus->po = PcmpLOW;
  86. bus->el = PcmpLEVEL;
  87. if(mpeisabus != -1)
  88. print("mkbus: more than one EISA bus\n");
  89. mpeisabus = bus->busno;
  90. }
  91. else if(bus->type == BusPCI){
  92. bus->po = PcmpLOW;
  93. bus->el = PcmpLEVEL;
  94. }
  95. else if(bus->type == BusISA){
  96. bus->po = PcmpHIGH;
  97. bus->el = PcmpEDGE;
  98. if(mpisabus != -1)
  99. print("mkbus: more than one ISA bus\n");
  100. mpisabus = bus->busno;
  101. }
  102. else{
  103. bus->po = PcmpHIGH;
  104. bus->el = PcmpEDGE;
  105. }
  106. return bus;
  107. }
  108. static Bus*
  109. mpgetbus(int busno)
  110. {
  111. Bus *bus;
  112. for(bus = mpbus; bus; bus = bus->next){
  113. if(bus->busno == busno)
  114. return bus;
  115. }
  116. print("mpgetbus: can't find bus %d\n", busno);
  117. return 0;
  118. }
  119. static Apic*
  120. mkioapic(PCMPioapic* p)
  121. {
  122. Apic *apic;
  123. void *va;
  124. if(!(p->flags & PcmpEN) || p->apicno > MaxAPICNO)
  125. return 0;
  126. /*
  127. * Map the I/O APIC.
  128. */
  129. if((va = vmap(p->addr, 1024)) == nil)
  130. return 0;
  131. apic = &mpapic[p->apicno];
  132. apic->type = PcmpIOAPIC;
  133. apic->apicno = p->apicno;
  134. apic->addr = va;
  135. apic->paddr = p->addr;
  136. apic->flags = p->flags;
  137. return apic;
  138. }
  139. static Aintr*
  140. mkiointr(PCMPintr* p)
  141. {
  142. Bus *bus;
  143. Aintr *aintr;
  144. /*
  145. * According to the MultiProcessor Specification, a destination
  146. * I/O APIC of 0xFF means the signal is routed to all I/O APICs.
  147. * It's unclear how that can possibly be correct so treat it as
  148. * an error for now.
  149. */
  150. if(p->apicno == 0xFF)
  151. return 0;
  152. if((bus = mpgetbus(p->busno)) == 0)
  153. return 0;
  154. aintr = xalloc(sizeof(Aintr));
  155. aintr->intr = p;
  156. aintr->apic = &mpapic[p->apicno];
  157. aintr->next = bus->aintr;
  158. bus->aintr = aintr;
  159. return aintr;
  160. }
  161. static int
  162. mpintrinit(Bus* bus, PCMPintr* intr, int vno, int /*irq*/)
  163. {
  164. int el, po, v;
  165. /*
  166. * Parse an I/O or Local APIC interrupt table entry and
  167. * return the encoded vector.
  168. */
  169. v = vno;
  170. po = intr->flags & PcmpPOMASK;
  171. el = intr->flags & PcmpELMASK;
  172. switch(intr->intr){
  173. default: /* PcmpINT */
  174. v |= ApicLOWEST;
  175. break;
  176. case PcmpNMI:
  177. v |= ApicNMI;
  178. po = PcmpHIGH;
  179. el = PcmpEDGE;
  180. break;
  181. case PcmpSMI:
  182. v |= ApicSMI;
  183. break;
  184. case PcmpExtINT:
  185. v |= ApicExtINT;
  186. /*
  187. * The AMI Goliath doesn't boot successfully with it's LINTR0
  188. * entry which decodes to low+level. The PPro manual says ExtINT
  189. * should be level, whereas the Pentium is edge. Setting the
  190. * Goliath to edge+high seems to cure the problem. Other PPro
  191. * MP tables (e.g. ASUS P/I-P65UP5 have a entry which decodes
  192. * to edge+high, so who knows.
  193. * Perhaps it would be best just to not set an ExtINT entry at
  194. * all, it shouldn't be needed for SMP mode.
  195. */
  196. po = PcmpHIGH;
  197. el = PcmpEDGE;
  198. break;
  199. }
  200. /*
  201. */
  202. if(bus->type == BusEISA && !po && !el /*&& !(i8259elcr & (1<<irq))*/){
  203. po = PcmpHIGH;
  204. el = PcmpEDGE;
  205. }
  206. if(!po)
  207. po = bus->po;
  208. if(po == PcmpLOW)
  209. v |= ApicLOW;
  210. else if(po != PcmpHIGH){
  211. print("mpintrinit: bad polarity 0x%uX\n", po);
  212. return ApicIMASK;
  213. }
  214. if(!el)
  215. el = bus->el;
  216. if(el == PcmpLEVEL)
  217. v |= ApicLEVEL;
  218. else if(el != PcmpEDGE){
  219. print("mpintrinit: bad trigger 0x%uX\n", el);
  220. return ApicIMASK;
  221. }
  222. return v;
  223. }
  224. static int
  225. mklintr(PCMPintr* p)
  226. {
  227. Apic *apic;
  228. Bus *bus;
  229. int intin, v;
  230. /*
  231. * The offsets of vectors for LINT[01] are known to be
  232. * 0 and 1 from the local APIC vector space at VectorLAPIC.
  233. */
  234. if((bus = mpgetbus(p->busno)) == 0)
  235. return 0;
  236. intin = p->intin;
  237. /*
  238. * Pentium Pros have problems if LINT[01] are set to ExtINT
  239. * so just bag it, SMP mode shouldn't need ExtINT anyway.
  240. */
  241. if(p->intr == PcmpExtINT || p->intr == PcmpNMI)
  242. v = ApicIMASK;
  243. else
  244. v = mpintrinit(bus, p, VectorLAPIC+intin, p->irq);
  245. if(p->apicno == 0xFF){
  246. for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
  247. if((apic->flags & PcmpEN)
  248. && apic->type == PcmpPROCESSOR)
  249. apic->lintr[intin] = v;
  250. }
  251. }
  252. else{
  253. apic = &mpapic[p->apicno];
  254. if((apic->flags & PcmpEN) && apic->type == PcmpPROCESSOR)
  255. apic->lintr[intin] = v;
  256. }
  257. return v;
  258. }
  259. static void
  260. checkmtrr(void)
  261. {
  262. int i, vcnt;
  263. Mach *mach0;
  264. /*
  265. * If there are MTRR registers, snarf them for validation.
  266. */
  267. if(!(m->cpuiddx & 0x1000))
  268. return;
  269. rdmsr(0x0FE, &m->mtrrcap);
  270. rdmsr(0x2FF, &m->mtrrdef);
  271. if(m->mtrrcap & 0x0100){
  272. rdmsr(0x250, &m->mtrrfix[0]);
  273. rdmsr(0x258, &m->mtrrfix[1]);
  274. rdmsr(0x259, &m->mtrrfix[2]);
  275. for(i = 0; i < 8; i++)
  276. rdmsr(0x268+i, &m->mtrrfix[(i+3)]);
  277. }
  278. vcnt = m->mtrrcap & 0x00FF;
  279. if(vcnt > nelem(m->mtrrvar))
  280. vcnt = nelem(m->mtrrvar);
  281. for(i = 0; i < vcnt; i++)
  282. rdmsr(0x200+i, &m->mtrrvar[i]);
  283. /*
  284. * If not the bootstrap processor, compare.
  285. */
  286. if(m->machno == 0)
  287. return;
  288. mach0 = MACHP(0);
  289. if(mach0->mtrrcap != m->mtrrcap)
  290. print("mtrrcap%d: %lluX %lluX\n",
  291. m->machno, mach0->mtrrcap, m->mtrrcap);
  292. if(mach0->mtrrdef != m->mtrrdef)
  293. print("mtrrdef%d: %lluX %lluX\n",
  294. m->machno, mach0->mtrrdef, m->mtrrdef);
  295. for(i = 0; i < 11; i++){
  296. if(mach0->mtrrfix[i] != m->mtrrfix[i])
  297. print("mtrrfix%d: i%d: %lluX %lluX\n",
  298. m->machno, i, mach0->mtrrfix[i], m->mtrrfix[i]);
  299. }
  300. for(i = 0; i < vcnt; i++){
  301. if(mach0->mtrrvar[i] != m->mtrrvar[i])
  302. print("mtrrvar%d: i%d: %lluX %lluX\n",
  303. m->machno, i, mach0->mtrrvar[i], m->mtrrvar[i]);
  304. }
  305. }
  306. static void
  307. squidboy(Apic* apic)
  308. {
  309. // iprint("Hello Squidboy\n");
  310. machinit();
  311. mmuinit();
  312. cpuidentify();
  313. cpuidprint();
  314. checkmtrr();
  315. lock(&mprdthilock);
  316. mprdthi |= (1<<apic->apicno)<<24;
  317. unlock(&mprdthilock);
  318. lapicinit(apic);
  319. lapiconline();
  320. syncclock();
  321. timersinit();
  322. fpoff();
  323. lock(&active);
  324. active.machs |= 1<<m->machno;
  325. unlock(&active);
  326. while(!active.thunderbirdsarego)
  327. microdelay(100);
  328. schedinit();
  329. }
  330. static void
  331. mpstartap(Apic* apic)
  332. {
  333. ulong *apbootp, *pdb, *pte;
  334. Mach *mach, *mach0;
  335. int i, machno;
  336. uchar *p;
  337. mach0 = MACHP(0);
  338. /*
  339. * Initialise the AP page-tables and Mach structure. The page-tables
  340. * are the same as for the bootstrap processor with the exception of
  341. * the PTE for the Mach structure.
  342. * Xspanalloc will panic if an allocation can't be made.
  343. */
  344. p = xspanalloc(4*BY2PG, BY2PG, 0);
  345. pdb = (ulong*)p;
  346. memmove(pdb, mach0->pdb, BY2PG);
  347. p += BY2PG;
  348. if((pte = mmuwalk(pdb, MACHADDR, 1, 0)) == nil)
  349. return;
  350. memmove(p, KADDR(PPN(*pte)), BY2PG);
  351. *pte = PADDR(p)|PTEWRITE|PTEVALID;
  352. if(mach0->havepge)
  353. *pte |= PTEGLOBAL;
  354. p += BY2PG;
  355. mach = (Mach*)p;
  356. if((pte = mmuwalk(pdb, MACHADDR, 2, 0)) == nil)
  357. return;
  358. *pte = PADDR(mach)|PTEWRITE|PTEVALID;
  359. if(mach0->havepge)
  360. *pte |= PTEGLOBAL;
  361. p += BY2PG;
  362. machno = apic->machno;
  363. MACHP(machno) = mach;
  364. mach->machno = machno;
  365. mach->pdb = pdb;
  366. mach->gdt = (Segdesc*)p; /* filled by mmuinit */
  367. /*
  368. * Tell the AP where its kernel vector and pdb are.
  369. * The offsets are known in the AP bootstrap code.
  370. */
  371. apbootp = (ulong*)(APBOOTSTRAP+0x08);
  372. *apbootp++ = (ulong)squidboy;
  373. *apbootp++ = PADDR(pdb);
  374. *apbootp = (ulong)apic;
  375. /*
  376. * Universal Startup Algorithm.
  377. */
  378. p = KADDR(0x467);
  379. *p++ = PADDR(APBOOTSTRAP);
  380. *p++ = PADDR(APBOOTSTRAP)>>8;
  381. i = (PADDR(APBOOTSTRAP) & ~0xFFFF)/16;
  382. /* code assumes i==0 */
  383. if(i != 0)
  384. print("mp: bad APBOOTSTRAP\n");
  385. *p++ = i;
  386. *p = i>>8;
  387. nvramwrite(0x0F, 0x0A);
  388. lapicstartap(apic, PADDR(APBOOTSTRAP));
  389. for(i = 0; i < 1000; i++){
  390. lock(&mprdthilock);
  391. if(mprdthi & ((1<<apic->apicno)<<24)){
  392. unlock(&mprdthilock);
  393. break;
  394. }
  395. unlock(&mprdthilock);
  396. delay(10);
  397. }
  398. nvramwrite(0x0F, 0x00);
  399. }
  400. void
  401. mpinit(void)
  402. {
  403. int ncpu;
  404. char *cp;
  405. PCMP *pcmp;
  406. uchar *e, *p;
  407. Apic *apic, *bpapic;
  408. void *va;
  409. i8259init();
  410. syncclock();
  411. if(_mp_ == 0)
  412. return;
  413. pcmp = KADDR(_mp_->physaddr);
  414. /*
  415. * Map the local APIC.
  416. */
  417. if((va = vmap(pcmp->lapicbase, 1024)) == nil)
  418. return;
  419. print("LAPIC: %.8lux %.8lux\n", pcmp->lapicbase, (ulong)va);
  420. bpapic = nil;
  421. /*
  422. * Run through the table saving information needed for starting
  423. * application processors and initialising any I/O APICs. The table
  424. * is guaranteed to be in order such that only one pass is necessary.
  425. */
  426. p = ((uchar*)pcmp)+sizeof(PCMP);
  427. e = ((uchar*)pcmp)+pcmp->length;
  428. while(p < e) switch(*p){
  429. default:
  430. print("mpinit: unknown PCMP type 0x%uX (e-p 0x%luX)\n",
  431. *p, e-p);
  432. while(p < e){
  433. print("%uX ", *p);
  434. p++;
  435. }
  436. break;
  437. case PcmpPROCESSOR:
  438. if(apic = mkprocessor((PCMPprocessor*)p)){
  439. /*
  440. * Must take a note of bootstrap processor APIC
  441. * now as it will be needed in order to start the
  442. * application processors later and there's no
  443. * guarantee that the bootstrap processor appears
  444. * first in the table before the others.
  445. */
  446. apic->addr = va;
  447. apic->paddr = pcmp->lapicbase;
  448. if(apic->flags & PcmpBP)
  449. bpapic = apic;
  450. }
  451. p += sizeof(PCMPprocessor);
  452. continue;
  453. case PcmpBUS:
  454. mkbus((PCMPbus*)p);
  455. p += sizeof(PCMPbus);
  456. continue;
  457. case PcmpIOAPIC:
  458. if(apic = mkioapic((PCMPioapic*)p))
  459. ioapicinit(apic, ((PCMPioapic*)p)->apicno);
  460. p += sizeof(PCMPioapic);
  461. continue;
  462. case PcmpIOINTR:
  463. mkiointr((PCMPintr*)p);
  464. p += sizeof(PCMPintr);
  465. continue;
  466. case PcmpLINTR:
  467. mklintr((PCMPintr*)p);
  468. p += sizeof(PCMPintr);
  469. continue;
  470. }
  471. /*
  472. * No bootstrap processor, no need to go further.
  473. */
  474. if(bpapic == 0)
  475. return;
  476. lapicinit(bpapic);
  477. lock(&mprdthilock);
  478. mprdthi |= (1<<bpapic->apicno)<<24;
  479. unlock(&mprdthilock);
  480. /*
  481. * These interrupts are local to the processor
  482. * and do not appear in the I/O APIC so it is OK
  483. * to set them now.
  484. */
  485. intrenable(IrqTIMER, lapicclock, 0, BUSUNKNOWN, "clock");
  486. intrenable(IrqERROR, lapicerror, 0, BUSUNKNOWN, "lapicerror");
  487. intrenable(IrqSPURIOUS, lapicspurious, 0, BUSUNKNOWN, "lapicspurious");
  488. lapiconline();
  489. checkmtrr();
  490. /*
  491. * Initialise the application processors.
  492. */
  493. if(cp = getconf("*ncpu")){
  494. ncpu = strtol(cp, 0, 0);
  495. if(ncpu < 1)
  496. ncpu = 1;
  497. }
  498. else
  499. ncpu = MaxAPICNO;
  500. memmove((void*)APBOOTSTRAP, apbootstrap, sizeof(apbootstrap));
  501. for(apic = mpapic; apic <= &mpapic[MaxAPICNO]; apic++){
  502. if(ncpu <= 1)
  503. break;
  504. if((apic->flags & (PcmpBP|PcmpEN)) == PcmpEN
  505. && apic->type == PcmpPROCESSOR){
  506. mpstartap(apic);
  507. conf.nmach++;
  508. ncpu--;
  509. }
  510. }
  511. /*
  512. * we don't really know the number of processors till
  513. * here.
  514. *
  515. * set conf.copymode here if nmach > 1.
  516. * Should look for an ExtINT line and enable it.
  517. */
  518. if(X86FAMILY(m->cpuidax) == 3 || conf.nmach > 1)
  519. conf.copymode = 1;
  520. }
  521. static int
  522. mpintrenablex(Vctl* v, int tbdf)
  523. {
  524. Bus *bus;
  525. Aintr *aintr;
  526. Apic *apic;
  527. Pcidev *pcidev;
  528. int bno, dno, irq, lo, n, type, vno;
  529. /*
  530. * Find the bus.
  531. */
  532. type = BUSTYPE(tbdf);
  533. bno = BUSBNO(tbdf);
  534. dno = BUSDNO(tbdf);
  535. if(type == BusISA)
  536. bno = mpisabus;
  537. for(bus = mpbus; bus != nil; bus = bus->next){
  538. if(bus->type != type)
  539. continue;
  540. if(bus->busno == bno)
  541. break;
  542. }
  543. if(bus == nil){
  544. print("ioapicirq: can't find bus type %d\n", type);
  545. return -1;
  546. }
  547. /*
  548. * For PCI devices the interrupt pin (INT[ABCD]) and device
  549. * number are encoded into the entry irq field, so create something
  550. * to match on. The interrupt pin used by the device has to be
  551. * obtained from the PCI config space.
  552. */
  553. if(bus->type == BusPCI){
  554. pcidev = pcimatchtbdf(tbdf);
  555. if(pcidev != nil && (n = pcicfgr8(pcidev, PciINTP)) != 0)
  556. irq = (dno<<2)|(n-1);
  557. else
  558. irq = -1;
  559. //print("pcidev %uX: irq %uX v->irq %uX\n", tbdf, irq, v->irq);
  560. }
  561. else
  562. irq = v->irq;
  563. /*
  564. * Find a matching interrupt entry from the list of interrupts
  565. * attached to this bus.
  566. */
  567. for(aintr = bus->aintr; aintr; aintr = aintr->next){
  568. if(aintr->intr->irq != irq)
  569. continue;
  570. /*
  571. * Check if already enabled. Multifunction devices may share
  572. * INT[A-D]# so, if already enabled, check the polarity matches
  573. * and the trigger is level.
  574. *
  575. * Should check the devices differ only in the function number,
  576. * but that can wait for the planned enable/disable rewrite.
  577. * The RDT read here is safe for now as currently interrupts
  578. * are never disabled once enabled.
  579. */
  580. apic = aintr->apic;
  581. ioapicrdtr(apic, aintr->intr->intin, 0, &lo);
  582. if(!(lo & ApicIMASK)){
  583. vno = lo & 0xFF;
  584. n = mpintrinit(bus, aintr->intr, vno, v->irq);
  585. n |= ApicLOGICAL;
  586. lo &= ~(ApicRemoteIRR|ApicDELIVS);
  587. if(n != lo || !(n & ApicLEVEL)){
  588. print("mpintrenable: multiple botch irq%d, tbdf %uX, lo %8.8uX, n %8.8uX\n",
  589. v->irq, tbdf, lo, n);
  590. return -1;
  591. }
  592. v->isr = lapicisr;
  593. v->eoi = lapiceoi;
  594. return vno;
  595. }
  596. /*
  597. * With the APIC a unique vector can be assigned to each
  598. * request to enable an interrupt. There are two reasons this
  599. * is a good idea:
  600. * 1) to prevent lost interrupts, no more than 2 interrupts
  601. * should be assigned per block of 16 vectors (there is an
  602. * in-service entry and a holding entry for each priority
  603. * level and there is one priority level per block of 16
  604. * interrupts).
  605. * 2) each input pin on the IOAPIC will receive a different
  606. * vector regardless of whether the devices on that pin use
  607. * the same IRQ as devices on another pin.
  608. */
  609. vno = VectorAPIC + (incref(&mpvnoref)-1)*8;
  610. if(vno > MaxVectorAPIC){
  611. print("mpintrenable: vno %d, irq %d, tbdf %uX\n",
  612. vno, v->irq, tbdf);
  613. return -1;
  614. }
  615. lo = mpintrinit(bus, aintr->intr, vno, v->irq);
  616. //print("lo 0x%uX: busno %d intr %d vno %d irq %d elcr 0x%uX\n",
  617. // lo, bus->busno, aintr->intr->irq, vno,
  618. // v->irq, i8259elcr);
  619. if(lo & ApicIMASK)
  620. return -1;
  621. lo |= ApicLOGICAL;
  622. if((apic->flags & PcmpEN) && apic->type == PcmpIOAPIC){
  623. lock(&mprdthilock);
  624. ioapicrdtw(apic, aintr->intr->intin, mprdthi, lo);
  625. unlock(&mprdthilock);
  626. }
  627. //else
  628. // print("lo not enabled 0x%uX %d\n",
  629. // apic->flags, apic->type);
  630. v->isr = lapicisr;
  631. v->eoi = lapiceoi;
  632. return vno;
  633. }
  634. return -1;
  635. }
  636. int
  637. mpintrenable(Vctl* v)
  638. {
  639. int irq, tbdf, vno;
  640. /*
  641. * If the bus is known, try it.
  642. * BUSUNKNOWN is given both by [E]ISA devices and by
  643. * interrupts local to the processor (local APIC, coprocessor
  644. * breakpoint and page-fault).
  645. */
  646. tbdf = v->tbdf;
  647. if(tbdf != BUSUNKNOWN && (vno = mpintrenablex(v, tbdf)) != -1)
  648. return vno;
  649. irq = v->irq;
  650. if(irq >= IrqLINT0 && irq <= MaxIrqLAPIC){
  651. if(irq != IrqSPURIOUS)
  652. v->isr = lapiceoi;
  653. return VectorPIC+irq;
  654. }
  655. if(irq < 0 || irq > MaxIrqPIC){
  656. print("mpintrenable: irq %d out of range\n", irq);
  657. return -1;
  658. }
  659. /*
  660. * Either didn't find it or have to try the default buses
  661. * (ISA and EISA). This hack is due to either over-zealousness
  662. * or laziness on the part of some manufacturers.
  663. *
  664. * The MP configuration table on some older systems
  665. * (e.g. ASUS PCI/E-P54NP4) has an entry for the EISA bus
  666. * but none for ISA. It also has the interrupt type and
  667. * polarity set to 'default for this bus' which wouldn't
  668. * be compatible with ISA.
  669. */
  670. if(mpeisabus != -1){
  671. vno = mpintrenablex(v, MKBUS(BusEISA, 0, 0, 0));
  672. if(vno != -1)
  673. return vno;
  674. }
  675. if(mpisabus != -1){
  676. vno = mpintrenablex(v, MKBUS(BusISA, 0, 0, 0));
  677. if(vno != -1)
  678. return vno;
  679. }
  680. print("mpintrenable: out of choices eisa %d isa %d tbdf %#ux irq %d\n",
  681. mpeisabus, mpisabus, v->tbdf, v->irq);
  682. return -1;
  683. }
  684. static Lock mpshutdownlock;
  685. void
  686. mpshutdown(void)
  687. {
  688. /*
  689. * To be done...
  690. */
  691. if(!canlock(&mpshutdownlock)){
  692. /*
  693. * If this processor received the CTRL-ALT-DEL from
  694. * the keyboard, acknowledge it. Send an INIT to self.
  695. */
  696. #ifdef FIXTHIS
  697. if(lapicisr(VectorKBD))
  698. lapiceoi(VectorKBD);
  699. #endif /* FIX THIS */
  700. idle();
  701. }
  702. print("apshutdown: active = 0x%2.2uX\n", active.machs);
  703. delay(1000);
  704. splhi();
  705. /*
  706. * INIT all excluding self.
  707. */
  708. lapicicrw(0, 0x000C0000|ApicINIT);
  709. #ifdef notdef
  710. /*
  711. * Often the BIOS hangs during restart if a conventional 8042
  712. * warm-boot sequence is tried. The following is Intel specific and
  713. * seems to perform a cold-boot, but at least it comes back.
  714. */
  715. *(ushort*)KADDR(0x472) = 0x1234; /* BIOS warm-boot flag */
  716. outb(0xCF9, 0x02);
  717. outb(0xCF9, 0x06);
  718. #else
  719. pcireset();
  720. i8042reset();
  721. #endif /* notdef */
  722. }