mp.h 6.6 KB

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  1. /*
  2. * MultiProcessor Specification Version 1.[14].
  3. */
  4. typedef struct { /* floating pointer */
  5. uchar signature[4]; /* "_MP_" */
  6. long physaddr; /* physical address of MP configuration table */
  7. uchar length; /* 1 */
  8. uchar specrev; /* [14] */
  9. uchar checksum; /* all bytes must add up to 0 */
  10. uchar type; /* MP system configuration type */
  11. uchar imcrp;
  12. uchar reserved[3];
  13. } _MP_;
  14. typedef struct { /* configuration table header */
  15. uchar signature[4]; /* "PCMP" */
  16. ushort length; /* total table length */
  17. uchar version; /* [14] */
  18. uchar checksum; /* all bytes must add up to 0 */
  19. uchar product[20]; /* product id */
  20. ulong oemtable; /* OEM table pointer */
  21. ushort oemlength; /* OEM table length */
  22. ushort entry; /* entry count */
  23. ulong lapicbase; /* address of local APIC */
  24. ushort xlength; /* extended table length */
  25. uchar xchecksum; /* extended table checksum */
  26. uchar reserved;
  27. } PCMP;
  28. typedef struct { /* processor table entry */
  29. uchar type; /* entry type (0) */
  30. uchar apicno; /* local APIC id */
  31. uchar version; /* local APIC verison */
  32. uchar flags; /* CPU flags */
  33. uchar signature[4]; /* CPU signature */
  34. ulong feature; /* feature flags from CPUID instruction */
  35. uchar reserved[8];
  36. } PCMPprocessor;
  37. typedef struct { /* bus table entry */
  38. uchar type; /* entry type (1) */
  39. uchar busno; /* bus id */
  40. char string[6]; /* bus type string */
  41. } PCMPbus;
  42. typedef struct { /* I/O APIC table entry */
  43. uchar type; /* entry type (2) */
  44. uchar apicno; /* I/O APIC id */
  45. uchar version; /* I/O APIC version */
  46. uchar flags; /* I/O APIC flags */
  47. ulong addr; /* I/O APIC address */
  48. } PCMPioapic;
  49. typedef struct { /* interrupt table entry */
  50. uchar type; /* entry type ([34]) */
  51. uchar intr; /* interrupt type */
  52. ushort flags; /* interrupt flag */
  53. uchar busno; /* source bus id */
  54. uchar irq; /* source bus irq */
  55. uchar apicno; /* destination APIC id */
  56. uchar intin; /* destination APIC [L]INTIN# */
  57. } PCMPintr;
  58. typedef struct { /* system address space mapping entry */
  59. uchar type; /* entry type (128) */
  60. uchar length; /* of this entry (20) */
  61. uchar busno; /* bus id */
  62. uchar addrtype;
  63. ulong addrbase[2];
  64. ulong addrlength[2];
  65. } PCMPsasm;
  66. typedef struct { /* bus hierarchy descriptor entry */
  67. uchar type; /* entry type (129) */
  68. uchar length; /* of this entry (8) */
  69. uchar busno; /* bus id */
  70. uchar info; /* bus info */
  71. uchar parent; /* parent bus */
  72. uchar reserved[3];
  73. } PCMPhierarchy;
  74. typedef struct { /* compatibility bus address space modifier entry */
  75. uchar type; /* entry type (130) */
  76. uchar length; /* of this entry (8) */
  77. uchar busno; /* bus id */
  78. uchar modifier; /* address modifier */
  79. ulong range; /* predefined range list */
  80. } PCMPcbasm;
  81. enum { /* table entry types */
  82. PcmpPROCESSOR = 0x00, /* one entry per processor */
  83. PcmpBUS = 0x01, /* one entry per bus */
  84. PcmpIOAPIC = 0x02, /* one entry per I/O APIC */
  85. PcmpIOINTR = 0x03, /* one entry per bus interrupt source */
  86. PcmpLINTR = 0x04, /* one entry per system interrupt source */
  87. PcmpSASM = 0x80,
  88. PcmpHIERARCHY = 0x81,
  89. PcmpCBASM = 0x82,
  90. /* PCMPprocessor and PCMPioapic flags */
  91. PcmpEN = 0x01, /* enabled */
  92. PcmpBP = 0x02, /* bootstrap processor */
  93. /* PCMPiointr and PCMPlintr flags */
  94. PcmpPOMASK = 0x03, /* polarity conforms to specifications of bus */
  95. PcmpHIGH = 0x01, /* active high */
  96. PcmpLOW = 0x03, /* active low */
  97. PcmpELMASK = 0x0C, /* trigger mode of APIC input signals */
  98. PcmpEDGE = 0x04, /* edge-triggered */
  99. PcmpLEVEL = 0x0C, /* level-triggered */
  100. /* PCMPiointr and PCMPlintr interrupt type */
  101. PcmpINT = 0x00, /* vectored interrupt from APIC Rdt */
  102. PcmpNMI = 0x01, /* non-maskable interrupt */
  103. PcmpSMI = 0x02, /* system management interrupt */
  104. PcmpExtINT = 0x03, /* vectored interrupt from external PIC */
  105. /* PCMPsasm addrtype */
  106. PcmpIOADDR = 0x00, /* I/O address */
  107. PcmpMADDR = 0x01, /* memory address */
  108. PcmpPADDR = 0x02, /* prefetch address */
  109. /* PCMPhierarchy info */
  110. PcmpSD = 0x01, /* subtractive decode bus */
  111. /* PCMPcbasm modifier */
  112. PcmpPR = 0x01, /* predefined range list */
  113. };
  114. /*
  115. * Condensed form of the MP Configuration Table.
  116. * This is created during a single pass through the MP Configuration
  117. * table.
  118. */
  119. typedef struct Aintr Aintr;
  120. typedef struct Bus Bus;
  121. typedef struct Apic Apic;
  122. typedef struct Bus {
  123. uchar type;
  124. uchar busno;
  125. uchar po;
  126. uchar el;
  127. Aintr* aintr; /* interrupts tied to this bus */
  128. Bus* next;
  129. } Bus;
  130. typedef struct Aintr {
  131. PCMPintr* intr;
  132. Apic* apic;
  133. Aintr* next;
  134. };
  135. typedef struct Apic {
  136. int type;
  137. int apicno;
  138. ulong* addr; /* register base address */
  139. ulong paddr;
  140. int flags; /* PcmpBP|PcmpEN */
  141. Lock; /* I/O APIC: register access */
  142. int mre; /* I/O APIC: maximum redirection entry */
  143. int lintr[2]; /* Local APIC */
  144. int machno;
  145. } Apic;
  146. enum {
  147. MaxAPICNO = 31,
  148. };
  149. enum { /* I/O APIC registers */
  150. IoapicID = 0x00, /* ID */
  151. IoapicVER = 0x01, /* version */
  152. IoapicARB = 0x02, /* arbitration ID */
  153. IoapicRDT = 0x10, /* redirection table */
  154. };
  155. /*
  156. * Common bits for
  157. * I/O APIC Redirection Table Entry;
  158. * Local APIC Local Interrupt Vector Table;
  159. * Local APIC Inter-Processor Interrupt;
  160. * Local APIC Timer Vector Table.
  161. */
  162. enum {
  163. ApicFIXED = 0x00000000, /* [10:8] Delivery Mode */
  164. ApicLOWEST = 0x00000100, /* Lowest priority */
  165. ApicSMI = 0x00000200, /* System Management Interrupt */
  166. ApicRR = 0x00000300, /* Remote Read */
  167. ApicNMI = 0x00000400,
  168. ApicINIT = 0x00000500, /* INIT/RESET */
  169. ApicSTARTUP = 0x00000600, /* Startup IPI */
  170. ApicExtINT = 0x00000700,
  171. ApicPHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */
  172. ApicLOGICAL = 0x00000800,
  173. ApicDELIVS = 0x00001000, /* [12] Delivery Status (RO) */
  174. ApicHIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */
  175. ApicLOW = 0x00002000,
  176. ApicRemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */
  177. ApicEDGE = 0x00000000, /* [15] Trigger Mode (RW) */
  178. ApicLEVEL = 0x00008000,
  179. ApicIMASK = 0x00010000, /* [16] Interrupt Mask */
  180. };
  181. extern void ioapicinit(Apic*, int);
  182. extern void ioapicrdtr(Apic*, int, int*, int*);
  183. extern void ioapicrdtw(Apic*, int, int, int);
  184. extern void lapicclock(Ureg*, void*);
  185. extern int lapiceoi(int);
  186. extern void lapicerror(Ureg*, void*);
  187. extern void lapicicrw(ulong, ulong);
  188. extern void lapicinit(Apic*);
  189. extern void lapicintroff(void);
  190. extern void lapicintron(void);
  191. extern int lapicisr(int);
  192. extern void lapicnmidisable(void);
  193. extern void lapicnmienable(void);
  194. extern void lapiconline(void);
  195. extern void lapicspurious(Ureg*, void*);
  196. extern void lapicstartap(Apic*, int);
  197. extern void lapictimerset(uvlong);
  198. extern void mpinit(void);
  199. extern int mpintrenable(Vctl*);
  200. extern void mpshutdown(void);
  201. extern _MP_ *_mp_;