pci.c 29 KB

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  1. /*
  2. * PCI support code.
  3. * Needs a massive rewrite.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #define DBG if(0) pcilog
  13. struct
  14. {
  15. char output[16384];
  16. int ptr;
  17. }PCICONS;
  18. int
  19. pcilog(char *fmt, ...)
  20. {
  21. int n;
  22. va_list arg;
  23. char buf[PRINTSIZE];
  24. va_start(arg, fmt);
  25. n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;
  26. va_end(arg);
  27. memmove(PCICONS.output+PCICONS.ptr, buf, n);
  28. PCICONS.ptr += n;
  29. return n;
  30. }
  31. enum
  32. { /* configuration mechanism #1 */
  33. PciADDR = 0xCF8, /* CONFIG_ADDRESS */
  34. PciDATA = 0xCFC, /* CONFIG_DATA */
  35. /* configuration mechanism #2 */
  36. PciCSE = 0xCF8, /* configuration space enable */
  37. PciFORWARD = 0xCFA, /* which bus */
  38. MaxFNO = 7,
  39. MaxUBN = 255,
  40. };
  41. enum
  42. { /* command register */
  43. IOen = (1<<0),
  44. MEMen = (1<<1),
  45. MASen = (1<<2),
  46. MemWrInv = (1<<4),
  47. PErrEn = (1<<6),
  48. SErrEn = (1<<8),
  49. };
  50. static Lock pcicfglock;
  51. static Lock pcicfginitlock;
  52. static int pcicfgmode = -1;
  53. static int pcimaxbno = 7;
  54. static int pcimaxdno;
  55. static Pcidev* pciroot;
  56. static Pcidev* pcilist;
  57. static Pcidev* pcitail;
  58. static int nobios, nopcirouting;
  59. static BIOS32si* pcibiossi;
  60. static int pcicfgrw8raw(int, int, int, int);
  61. static int pcicfgrw16raw(int, int, int, int);
  62. static int pcicfgrw32raw(int, int, int, int);
  63. static int (*pcicfgrw8)(int, int, int, int) = pcicfgrw8raw;
  64. static int (*pcicfgrw16)(int, int, int, int) = pcicfgrw16raw;
  65. static int (*pcicfgrw32)(int, int, int, int) = pcicfgrw32raw;
  66. static char* bustypes[] = {
  67. "CBUSI",
  68. "CBUSII",
  69. "EISA",
  70. "FUTURE",
  71. "INTERN",
  72. "ISA",
  73. "MBI",
  74. "MBII",
  75. "MCA",
  76. "MPI",
  77. "MPSA",
  78. "NUBUS",
  79. "PCI",
  80. "PCMCIA",
  81. "TC",
  82. "VL",
  83. "VME",
  84. "XPRESS",
  85. };
  86. #pragma varargck type "T" int
  87. static int
  88. tbdffmt(Fmt* fmt)
  89. {
  90. char *p;
  91. int l, r, type, tbdf;
  92. if((p = malloc(READSTR)) == nil)
  93. return fmtstrcpy(fmt, "(tbdfconv)");
  94. switch(fmt->r){
  95. case 'T':
  96. tbdf = va_arg(fmt->args, int);
  97. type = BUSTYPE(tbdf);
  98. if(type < nelem(bustypes))
  99. l = snprint(p, READSTR, bustypes[type]);
  100. else
  101. l = snprint(p, READSTR, "%d", type);
  102. snprint(p+l, READSTR-l, ".%d.%d.%d",
  103. BUSBNO(tbdf), BUSDNO(tbdf), BUSFNO(tbdf));
  104. break;
  105. default:
  106. snprint(p, READSTR, "(tbdfconv)");
  107. break;
  108. }
  109. r = fmtstrcpy(fmt, p);
  110. free(p);
  111. return r;
  112. }
  113. ulong
  114. pcibarsize(Pcidev *p, int rno)
  115. {
  116. ulong v, size;
  117. v = pcicfgrw32(p->tbdf, rno, 0, 1);
  118. pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
  119. size = pcicfgrw32(p->tbdf, rno, 0, 1);
  120. if(v & 1)
  121. size |= 0xFFFF0000;
  122. pcicfgrw32(p->tbdf, rno, v, 0);
  123. return -(size & ~0x0F);
  124. }
  125. static int
  126. pcisizcmp(void *a, void *b)
  127. {
  128. Pcisiz *aa, *bb;
  129. aa = a;
  130. bb = b;
  131. return aa->siz - bb->siz;
  132. }
  133. static ulong
  134. pcimask(ulong v)
  135. {
  136. ulong m;
  137. m = BI2BY*sizeof(v);
  138. for(m = 1<<(m-1); m != 0; m >>= 1) {
  139. if(m & v)
  140. break;
  141. }
  142. m--;
  143. if((v & m) == 0)
  144. return v;
  145. v |= m;
  146. return v+1;
  147. }
  148. static void
  149. pcibusmap(Pcidev *root, ulong *pmema, ulong *pioa, int wrreg)
  150. {
  151. Pcidev *p;
  152. int ntb, i, size, rno, hole;
  153. ulong v, mema, ioa, sioa, smema, base, limit;
  154. Pcisiz *table, *tptr, *mtb, *itb;
  155. if(!nobios)
  156. return;
  157. ioa = *pioa;
  158. mema = *pmema;
  159. DBG("pcibusmap wr=%d %T mem=%luX io=%luX\n",
  160. wrreg, root->tbdf, mema, ioa);
  161. ntb = 0;
  162. for(p = root; p != nil; p = p->link)
  163. ntb++;
  164. ntb *= (PciCIS-PciBAR0)/4;
  165. table = malloc(2*ntb*sizeof(Pcisiz));
  166. itb = table;
  167. mtb = table+ntb;
  168. /*
  169. * Build a table of sizes
  170. */
  171. for(p = root; p != nil; p = p->link) {
  172. if(p->ccrb == 0x06) {
  173. if(p->ccru != 0x04 || p->bridge == nil) {
  174. // DBG("pci: ignored bridge %T\n", p->tbdf);
  175. continue;
  176. }
  177. sioa = ioa;
  178. smema = mema;
  179. pcibusmap(p->bridge, &smema, &sioa, 0);
  180. hole = pcimask(smema-mema);
  181. if(hole < (1<<20))
  182. hole = 1<<20;
  183. p->mema.size = hole;
  184. hole = pcimask(sioa-ioa);
  185. if(hole < (1<<12))
  186. hole = 1<<12;
  187. p->ioa.size = hole;
  188. itb->dev = p;
  189. itb->bar = -1;
  190. itb->siz = p->ioa.size;
  191. itb++;
  192. mtb->dev = p;
  193. mtb->bar = -1;
  194. mtb->siz = p->mema.size;
  195. mtb++;
  196. continue;
  197. }
  198. for(i = 0; i <= 5; i++) {
  199. rno = PciBAR0 + i*4;
  200. v = pcicfgrw32(p->tbdf, rno, 0, 1);
  201. size = pcibarsize(p, rno);
  202. if(size == 0)
  203. continue;
  204. if(v & 1) {
  205. itb->dev = p;
  206. itb->bar = i;
  207. itb->siz = size;
  208. itb++;
  209. }
  210. else {
  211. mtb->dev = p;
  212. mtb->bar = i;
  213. mtb->siz = size;
  214. mtb++;
  215. }
  216. p->mem[i].size = size;
  217. }
  218. }
  219. /*
  220. * Sort both tables IO smallest first, Memory largest
  221. */
  222. qsort(table, itb-table, sizeof(Pcisiz), pcisizcmp);
  223. tptr = table+ntb;
  224. qsort(tptr, mtb-tptr, sizeof(Pcisiz), pcisizcmp);
  225. /*
  226. * Allocate IO address space on this bus
  227. */
  228. for(tptr = table; tptr < itb; tptr++) {
  229. hole = tptr->siz;
  230. if(tptr->bar == -1)
  231. hole = 1<<12;
  232. ioa = (ioa+hole-1) & ~(hole-1);
  233. p = tptr->dev;
  234. if(tptr->bar == -1)
  235. p->ioa.bar = ioa;
  236. else {
  237. p->pcr |= IOen;
  238. p->mem[tptr->bar].bar = ioa|1;
  239. if(wrreg)
  240. pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), ioa|1, 0);
  241. }
  242. ioa += tptr->siz;
  243. }
  244. /*
  245. * Allocate Memory address space on this bus
  246. */
  247. for(tptr = table+ntb; tptr < mtb; tptr++) {
  248. hole = tptr->siz;
  249. if(tptr->bar == -1)
  250. hole = 1<<20;
  251. mema = (mema+hole-1) & ~(hole-1);
  252. p = tptr->dev;
  253. if(tptr->bar == -1)
  254. p->mema.bar = mema;
  255. else {
  256. p->pcr |= MEMen;
  257. p->mem[tptr->bar].bar = mema;
  258. if(wrreg)
  259. pcicfgrw32(p->tbdf, PciBAR0+(tptr->bar*4), mema, 0);
  260. }
  261. mema += tptr->siz;
  262. }
  263. *pmema = mema;
  264. *pioa = ioa;
  265. free(table);
  266. if(wrreg == 0)
  267. return;
  268. /*
  269. * Finally set all the bridge addresses & registers
  270. */
  271. for(p = root; p != nil; p = p->link) {
  272. if(p->bridge == nil) {
  273. pcicfgrw8(p->tbdf, PciLTR, 64, 0);
  274. p->pcr |= MASen;
  275. pcicfgrw16(p->tbdf, PciPCR, p->pcr, 0);
  276. continue;
  277. }
  278. base = p->ioa.bar;
  279. limit = base+p->ioa.size-1;
  280. v = pcicfgrw32(p->tbdf, PciIBR, 0, 1);
  281. v = (v&0xFFFF0000)|(limit & 0xF000)|((base & 0xF000)>>8);
  282. pcicfgrw32(p->tbdf, PciIBR, v, 0);
  283. v = (limit & 0xFFFF0000)|(base>>16);
  284. pcicfgrw32(p->tbdf, PciIUBR, v, 0);
  285. base = p->mema.bar;
  286. limit = base+p->mema.size-1;
  287. v = (limit & 0xFFF00000)|((base & 0xFFF00000)>>16);
  288. pcicfgrw32(p->tbdf, PciMBR, v, 0);
  289. /*
  290. * Disable memory prefetch
  291. */
  292. pcicfgrw32(p->tbdf, PciPMBR, 0x0000FFFF, 0);
  293. pcicfgrw8(p->tbdf, PciLTR, 64, 0);
  294. /*
  295. * Enable the bridge
  296. */
  297. p->pcr |= IOen|MEMen|MASen;
  298. pcicfgrw32(p->tbdf, PciPCR, 0xFFFF0000|p->pcr , 0);
  299. sioa = p->ioa.bar;
  300. smema = p->mema.bar;
  301. pcibusmap(p->bridge, &smema, &sioa, 1);
  302. }
  303. }
  304. static int
  305. pcilscan(int bno, Pcidev** list)
  306. {
  307. Pcidev *p, *head, *tail;
  308. int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
  309. maxubn = bno;
  310. head = nil;
  311. tail = nil;
  312. for(dno = 0; dno <= pcimaxdno; dno++){
  313. maxfno = 0;
  314. for(fno = 0; fno <= maxfno; fno++){
  315. /*
  316. * For this possible device, form the
  317. * bus+device+function triplet needed to address it
  318. * and try to read the vendor and device ID.
  319. * If successful, allocate a device struct and
  320. * start to fill it in with some useful information
  321. * from the device's configuration space.
  322. */
  323. tbdf = MKBUS(BusPCI, bno, dno, fno);
  324. l = pcicfgrw32(tbdf, PciVID, 0, 1);
  325. if(l == 0xFFFFFFFF || l == 0)
  326. continue;
  327. p = malloc(sizeof(*p));
  328. p->tbdf = tbdf;
  329. p->vid = l;
  330. p->did = l>>16;
  331. if(pcilist != nil)
  332. pcitail->list = p;
  333. else
  334. pcilist = p;
  335. pcitail = p;
  336. p->pcr = pcicfgr16(p, PciPCR);
  337. p->rid = pcicfgr8(p, PciRID);
  338. p->ccrp = pcicfgr8(p, PciCCRp);
  339. p->ccru = pcicfgr8(p, PciCCRu);
  340. p->ccrb = pcicfgr8(p, PciCCRb);
  341. p->cls = pcicfgr8(p, PciCLS);
  342. p->ltr = pcicfgr8(p, PciLTR);
  343. p->intl = pcicfgr8(p, PciINTL);
  344. /*
  345. * If the device is a multi-function device adjust the
  346. * loop count so all possible functions are checked.
  347. */
  348. hdt = pcicfgr8(p, PciHDT);
  349. if(hdt & 0x80)
  350. maxfno = MaxFNO;
  351. /*
  352. * If appropriate, read the base address registers
  353. * and work out the sizes.
  354. */
  355. switch(p->ccrb) {
  356. case 0x01: /* mass storage controller */
  357. case 0x02: /* network controller */
  358. case 0x03: /* display controller */
  359. case 0x04: /* multimedia device */
  360. case 0x07: /* simple comm. controllers */
  361. case 0x08: /* base system peripherals */
  362. case 0x09: /* input devices */
  363. case 0x0A: /* docking stations */
  364. case 0x0B: /* processors */
  365. case 0x0C: /* serial bus controllers */
  366. if((hdt & 0x7F) != 0)
  367. break;
  368. rno = PciBAR0 - 4;
  369. for(i = 0; i < nelem(p->mem); i++) {
  370. rno += 4;
  371. p->mem[i].bar = pcicfgr32(p, rno);
  372. p->mem[i].size = pcibarsize(p, rno);
  373. }
  374. break;
  375. case 0x00:
  376. case 0x05: /* memory controller */
  377. case 0x06: /* bridge device */
  378. default:
  379. break;
  380. }
  381. if(head != nil)
  382. tail->link = p;
  383. else
  384. head = p;
  385. tail = p;
  386. }
  387. }
  388. *list = head;
  389. for(p = head; p != nil; p = p->link){
  390. /*
  391. * Find PCI-PCI bridges and recursively descend the tree.
  392. */
  393. if(p->ccrb != 0x06 || p->ccru != 0x04)
  394. continue;
  395. /*
  396. * If the secondary or subordinate bus number is not
  397. * initialised try to do what the PCI BIOS should have
  398. * done and fill in the numbers as the tree is descended.
  399. * On the way down the subordinate bus number is set to
  400. * the maximum as it's not known how many buses are behind
  401. * this one; the final value is set on the way back up.
  402. */
  403. sbn = pcicfgr8(p, PciSBN);
  404. ubn = pcicfgr8(p, PciUBN);
  405. if(sbn == 0 || ubn == 0 || nobios) {
  406. sbn = maxubn+1;
  407. /*
  408. * Make sure memory, I/O and master enables are
  409. * off, set the primary, secondary and subordinate
  410. * bus numbers and clear the secondary status before
  411. * attempting to scan the secondary bus.
  412. *
  413. * Initialisation of the bridge should be done here.
  414. */
  415. pcicfgw32(p, PciPCR, 0xFFFF0000);
  416. l = (MaxUBN<<16)|(sbn<<8)|bno;
  417. pcicfgw32(p, PciPBN, l);
  418. pcicfgw16(p, PciSPSR, 0xFFFF);
  419. maxubn = pcilscan(sbn, &p->bridge);
  420. l = (maxubn<<16)|(sbn<<8)|bno;
  421. pcicfgw32(p, PciPBN, l);
  422. }
  423. else {
  424. if(ubn > maxubn)
  425. maxubn = ubn;
  426. pcilscan(sbn, &p->bridge);
  427. }
  428. }
  429. return maxubn;
  430. }
  431. int
  432. pciscan(int bno, Pcidev **list)
  433. {
  434. int ubn;
  435. lock(&pcicfginitlock);
  436. ubn = pcilscan(bno, list);
  437. unlock(&pcicfginitlock);
  438. return ubn;
  439. }
  440. static uchar
  441. pIIxget(Pcidev *router, uchar link)
  442. {
  443. uchar pirq;
  444. /* link should be 0x60, 0x61, 0x62, 0x63 */
  445. pirq = pcicfgr8(router, link);
  446. return (pirq < 16)? pirq: 0;
  447. }
  448. static void
  449. pIIxset(Pcidev *router, uchar link, uchar irq)
  450. {
  451. pcicfgw8(router, link, irq);
  452. }
  453. static uchar
  454. viaget(Pcidev *router, uchar link)
  455. {
  456. uchar pirq;
  457. /* link should be 1, 2, 3, 5 */
  458. pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
  459. return (link & 1)? (pirq >> 4): (pirq & 15);
  460. }
  461. static void
  462. viaset(Pcidev *router, uchar link, uchar irq)
  463. {
  464. uchar pirq;
  465. pirq = pcicfgr8(router, 0x55 + (link >> 1));
  466. pirq &= (link & 1)? 0x0f: 0xf0;
  467. pirq |= (link & 1)? (irq << 4): (irq & 15);
  468. pcicfgw8(router, 0x55 + (link>>1), pirq);
  469. }
  470. static uchar
  471. optiget(Pcidev *router, uchar link)
  472. {
  473. uchar pirq = 0;
  474. /* link should be 0x02, 0x12, 0x22, 0x32 */
  475. if ((link & 0xcf) == 0x02)
  476. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  477. return (link & 0x10)? (pirq >> 4): (pirq & 15);
  478. }
  479. static void
  480. optiset(Pcidev *router, uchar link, uchar irq)
  481. {
  482. uchar pirq;
  483. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  484. pirq &= (link & 0x10)? 0x0f : 0xf0;
  485. pirq |= (link & 0x10)? (irq << 4): (irq & 15);
  486. pcicfgw8(router, 0xb8 + (link >> 5), pirq);
  487. }
  488. static uchar
  489. aliget(Pcidev *router, uchar link)
  490. {
  491. /* No, you're not dreaming */
  492. static const uchar map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
  493. uchar pirq;
  494. /* link should be 0x01..0x08 */
  495. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  496. return (link & 1)? map[pirq&15]: map[pirq>>4];
  497. }
  498. static void
  499. aliset(Pcidev *router, uchar link, uchar irq)
  500. {
  501. /* Inverse of map in aliget */
  502. static const uchar map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
  503. uchar pirq;
  504. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  505. pirq &= (link & 1)? 0x0f: 0xf0;
  506. pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
  507. pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
  508. }
  509. static uchar
  510. cyrixget(Pcidev *router, uchar link)
  511. {
  512. uchar pirq;
  513. /* link should be 1, 2, 3, 4 */
  514. pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
  515. return ((link & 1)? pirq >> 4: pirq & 15);
  516. }
  517. static void
  518. cyrixset(Pcidev *router, uchar link, uchar irq)
  519. {
  520. uchar pirq;
  521. pirq = pcicfgr8(router, 0x5c + (link>>1));
  522. pirq &= (link & 1)? 0x0f: 0xf0;
  523. pirq |= (link & 1)? (irq << 4): (irq & 15);
  524. pcicfgw8(router, 0x5c + (link>>1), pirq);
  525. }
  526. typedef struct Bridge Bridge;
  527. struct Bridge
  528. {
  529. ushort vid;
  530. ushort did;
  531. uchar (*get)(Pcidev *, uchar);
  532. void (*set)(Pcidev *, uchar, uchar);
  533. };
  534. static Bridge southbridges[] = {
  535. { 0x8086, 0x122e, pIIxget, pIIxset }, /* Intel 82371FB */
  536. { 0x8086, 0x1234, pIIxget, pIIxset }, /* Intel 82371MX */
  537. { 0x8086, 0x7000, pIIxget, pIIxset }, /* Intel 82371SB */
  538. { 0x8086, 0x7110, pIIxget, pIIxset }, /* Intel 82371AB */
  539. { 0x8086, 0x7198, pIIxget, pIIxset }, /* Intel 82443MX (fn 1) */
  540. { 0x8086, 0x2410, pIIxget, pIIxset }, /* Intel 82801AA */
  541. { 0x8086, 0x2420, pIIxget, pIIxset }, /* Intel 82801AB */
  542. { 0x8086, 0x2440, pIIxget, pIIxset }, /* Intel 82801BA */
  543. { 0x8086, 0x244c, pIIxget, pIIxset }, /* Intel 82801BAM */
  544. { 0x8086, 0x2480, pIIxget, pIIxset }, /* Intel 82801CA */
  545. { 0x8086, 0x248c, pIIxget, pIIxset }, /* Intel 82801CAM */
  546. { 0x8086, 0x24c0, pIIxget, pIIxset }, /* Intel 82801DBL */
  547. { 0x8086, 0x24cc, pIIxget, pIIxset }, /* Intel 82801DBM */
  548. { 0x8086, 0x24d0, pIIxget, pIIxset }, /* Intel 82801EB */
  549. { 0x8086, 0x2640, pIIxget, pIIxset }, /* Intel 82801FB */
  550. { 0x8086, 0x27b8, pIIxget, pIIxset }, /* Intel 82801GB */
  551. { 0x8086, 0x27b9, pIIxget, pIIxset }, /* Intel 82801GBM */
  552. { 0x1106, 0x0586, viaget, viaset }, /* Viatech 82C586 */
  553. { 0x1106, 0x0596, viaget, viaset }, /* Viatech 82C596 */
  554. { 0x1106, 0x0686, viaget, viaset }, /* Viatech 82C686 */
  555. { 0x1106, 0x3227, viaget, viaset }, /* Viatech VT8237 */
  556. { 0x1045, 0xc700, optiget, optiset }, /* Opti 82C700 */
  557. { 0x10b9, 0x1533, aliget, aliset }, /* Al M1533 */
  558. { 0x1039, 0x0008, pIIxget, pIIxset }, /* SI 503 */
  559. { 0x1039, 0x0496, pIIxget, pIIxset }, /* SI 496 */
  560. { 0x1078, 0x0100, cyrixget, cyrixset }, /* Cyrix 5530 Legacy */
  561. { 0x1022, 0x746B, nil, nil }, /* AMD 8111 */
  562. { 0x10DE, 0x00D1, nil, nil }, /* NVIDIA nForce 3 */
  563. { 0x10DE, 0x00E0, nil, nil }, /* NVIDIA nForce 3 250 Series */
  564. { 0x10DE, 0x00E1, nil, nil }, /* NVIDIA nForce 3 250 Series */
  565. { 0x1166, 0x0200, nil, nil }, /* ServerWorks ServerSet III LE */
  566. { 0x1002, 0x4377, nil, nil }, /* ATI Radeon Xpress 200M */
  567. { 0x1002, 0x4372, nil, nil }, /* ATI SB400 */
  568. };
  569. typedef struct Slot Slot;
  570. struct Slot {
  571. uchar bus; /* Pci bus number */
  572. uchar dev; /* Pci device number */
  573. uchar maps[12]; /* Avoid structs! Link and mask. */
  574. uchar slot; /* Add-in/built-in slot */
  575. uchar reserved;
  576. };
  577. typedef struct Router Router;
  578. struct Router {
  579. uchar signature[4]; /* Routing table signature */
  580. uchar version[2]; /* Version number */
  581. uchar size[2]; /* Total table size */
  582. uchar bus; /* Interrupt router bus number */
  583. uchar devfn; /* Router's devfunc */
  584. uchar pciirqs[2]; /* Exclusive PCI irqs */
  585. uchar compat[4]; /* Compatible PCI interrupt router */
  586. uchar miniport[4]; /* Miniport data */
  587. uchar reserved[11];
  588. uchar checksum;
  589. };
  590. static ushort pciirqs; /* Exclusive PCI irqs */
  591. static Bridge *southbridge; /* Which southbridge to use. */
  592. static void
  593. pcirouting(void)
  594. {
  595. Slot *e;
  596. Router *r;
  597. int size, i, fn, tbdf;
  598. Pcidev *sbpci, *pci;
  599. uchar *p, pin, irq, link, *map;
  600. /* Search for PCI interrupt routing table in BIOS */
  601. for(p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
  602. if(p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
  603. break;
  604. if(p >= (uchar *)KADDR(0xfffff))
  605. return;
  606. r = (Router *)p;
  607. // print("PCI interrupt routing table version %d.%d at %.6uX\n",
  608. // r->version[0], r->version[1], (ulong)r & 0xfffff);
  609. tbdf = (BusPCI << 24)|(r->bus << 16)|(r->devfn << 8);
  610. sbpci = pcimatchtbdf(tbdf);
  611. if(sbpci == nil) {
  612. print("pcirouting: Cannot find south bridge %T\n", tbdf);
  613. return;
  614. }
  615. for(i = 0; i != nelem(southbridges); i++)
  616. if(sbpci->vid == southbridges[i].vid && sbpci->did == southbridges[i].did)
  617. break;
  618. if(i == nelem(southbridges)) {
  619. print("pcirouting: ignoring south bridge %T %.4uX/%.4uX\n", tbdf, sbpci->vid, sbpci->did);
  620. return;
  621. }
  622. southbridge = &southbridges[i];
  623. if(southbridge->get == nil || southbridge->set == nil)
  624. return;
  625. pciirqs = (r->pciirqs[1] << 8)|r->pciirqs[0];
  626. size = (r->size[1] << 8)|r->size[0];
  627. for(e = (Slot *)&r[1]; (uchar *)e < p + size; e++) {
  628. if (0) {
  629. print("%.2uX/%.2uX %.2uX: ", e->bus, e->dev, e->slot);
  630. for (i = 0; i != 4; i++) {
  631. uchar *m = &e->maps[i * 3];
  632. print("[%d] %.2uX %.4uX ",
  633. i, m[0], (m[2] << 8)|m[1]);
  634. }
  635. print("\n");
  636. }
  637. for(fn = 0; fn != 8; fn++) {
  638. tbdf = (BusPCI << 24)|(e->bus << 16)|((e->dev | fn) << 8);
  639. pci = pcimatchtbdf(tbdf);
  640. if(pci == nil)
  641. continue;
  642. pin = pcicfgr8(pci, PciINTP);
  643. if(pin == 0 || pin == 0xff)
  644. continue;
  645. map = &e->maps[(pin - 1) * 3];
  646. link = map[0];
  647. irq = southbridge->get(sbpci, link);
  648. if(irq == 0 || irq == pci->intl)
  649. continue;
  650. if(pci->intl != 0 && pci->intl != 0xFF) {
  651. print("pcirouting: BIOS workaround: %T at pin %d link %d irq %d -> %d\n",
  652. tbdf, pin, link, irq, pci->intl);
  653. southbridge->set(sbpci, link, pci->intl);
  654. continue;
  655. }
  656. print("pcirouting: %T at pin %d link %d irq %d\n", tbdf, pin, link, irq);
  657. pcicfgw8(pci, PciINTL, irq);
  658. pci->intl = irq;
  659. }
  660. }
  661. }
  662. static void pcireservemem(void);
  663. static int
  664. pcicfgrw8bios(int tbdf, int rno, int data, int read)
  665. {
  666. BIOS32ci ci;
  667. if(pcibiossi == nil)
  668. return -1;
  669. memset(&ci, 0, sizeof(BIOS32ci));
  670. ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
  671. ci.edi = rno;
  672. if(read){
  673. ci.eax = 0xB108;
  674. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  675. return ci.ecx & 0xFF;
  676. }
  677. else{
  678. ci.eax = 0xB10B;
  679. ci.ecx = data & 0xFF;
  680. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  681. return 0;
  682. }
  683. return -1;
  684. }
  685. static int
  686. pcicfgrw16bios(int tbdf, int rno, int data, int read)
  687. {
  688. BIOS32ci ci;
  689. if(pcibiossi == nil)
  690. return -1;
  691. memset(&ci, 0, sizeof(BIOS32ci));
  692. ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
  693. ci.edi = rno;
  694. if(read){
  695. ci.eax = 0xB109;
  696. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  697. return ci.ecx & 0xFFFF;
  698. }
  699. else{
  700. ci.eax = 0xB10C;
  701. ci.ecx = data & 0xFFFF;
  702. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  703. return 0;
  704. }
  705. return -1;
  706. }
  707. static int
  708. pcicfgrw32bios(int tbdf, int rno, int data, int read)
  709. {
  710. BIOS32ci ci;
  711. if(pcibiossi == nil)
  712. return -1;
  713. memset(&ci, 0, sizeof(BIOS32ci));
  714. ci.ebx = (BUSBNO(tbdf)<<8)|(BUSDNO(tbdf)<<3)|BUSFNO(tbdf);
  715. ci.edi = rno;
  716. if(read){
  717. ci.eax = 0xB10A;
  718. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  719. return ci.ecx;
  720. }
  721. else{
  722. ci.eax = 0xB10D;
  723. ci.ecx = data;
  724. if(!bios32ci(pcibiossi, &ci)/* && !(ci.eax & 0xFF)*/)
  725. return 0;
  726. }
  727. return -1;
  728. }
  729. static BIOS32si*
  730. pcibiosinit(void)
  731. {
  732. BIOS32ci ci;
  733. BIOS32si *si;
  734. if((si = bios32open("$PCI")) == nil)
  735. return nil;
  736. memset(&ci, 0, sizeof(BIOS32ci));
  737. ci.eax = 0xB101;
  738. if(bios32ci(si, &ci) || ci.edx != ((' '<<24)|('I'<<16)|('C'<<8)|'P')){
  739. free(si);
  740. return nil;
  741. }
  742. if(ci.eax & 0x01)
  743. pcimaxdno = 31;
  744. else
  745. pcimaxdno = 15;
  746. pcimaxbno = ci.ecx & 0xff;
  747. return si;
  748. }
  749. void
  750. pcibussize(Pcidev *root, ulong *msize, ulong *iosize)
  751. {
  752. *msize = 0;
  753. *iosize = 0;
  754. pcibusmap(root, msize, iosize, 0);
  755. }
  756. static void
  757. pcicfginit(void)
  758. {
  759. char *p;
  760. Pcidev **list;
  761. ulong mema, ioa;
  762. int bno, n, pcibios;
  763. lock(&pcicfginitlock);
  764. if(pcicfgmode != -1)
  765. goto out;
  766. pcibios = 0;
  767. if(getconf("*nobios"))
  768. nobios = 1;
  769. else if(getconf("*pcibios"))
  770. pcibios = 1;
  771. if(getconf("*nopcirouting"))
  772. nopcirouting = 1;
  773. /*
  774. * Try to determine which PCI configuration mode is implemented.
  775. * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
  776. * a DWORD at 0xCF8 and another at 0xCFC and will pass through
  777. * any non-DWORD accesses as normal I/O cycles. There shouldn't be
  778. * a device behind these addresses so if Mode1 accesses fail try
  779. * for Mode2 (Mode2 is deprecated).
  780. */
  781. if(!pcibios){
  782. /*
  783. * Bits [30:24] of PciADDR must be 0,
  784. * according to the spec.
  785. */
  786. n = inl(PciADDR);
  787. if(!(n & 0x7F000000)){
  788. outl(PciADDR, 0x80000000);
  789. outb(PciADDR+3, 0);
  790. if(inl(PciADDR) & 0x80000000){
  791. pcicfgmode = 1;
  792. pcimaxdno = 31;
  793. }
  794. }
  795. outl(PciADDR, n);
  796. if(pcicfgmode < 0){
  797. /*
  798. * The 'key' part of PciCSE should be 0.
  799. */
  800. n = inb(PciCSE);
  801. if(!(n & 0xF0)){
  802. outb(PciCSE, 0x0E);
  803. if(inb(PciCSE) == 0x0E){
  804. pcicfgmode = 2;
  805. pcimaxdno = 15;
  806. }
  807. }
  808. outb(PciCSE, n);
  809. }
  810. }
  811. if(pcicfgmode < 0 || pcibios) {
  812. if((pcibiossi = pcibiosinit()) == nil)
  813. goto out;
  814. pcicfgrw8 = pcicfgrw8bios;
  815. pcicfgrw16 = pcicfgrw16bios;
  816. pcicfgrw32 = pcicfgrw32bios;
  817. pcicfgmode = 3;
  818. }
  819. fmtinstall('T', tbdffmt);
  820. if(p = getconf("*pcimaxbno")){
  821. n = strtoul(p, 0, 0);
  822. if(n < pcimaxbno)
  823. pcimaxbno = n;
  824. }
  825. if(p = getconf("*pcimaxdno")){
  826. n = strtoul(p, 0, 0);
  827. if(n < pcimaxdno)
  828. pcimaxdno = n;
  829. }
  830. list = &pciroot;
  831. for(bno = 0; bno <= pcimaxbno; bno++) {
  832. int sbno = bno;
  833. bno = pcilscan(bno, list);
  834. while(*list)
  835. list = &(*list)->link;
  836. if (sbno == 0) {
  837. Pcidev *pci;
  838. /*
  839. * If we have found a PCI-to-Cardbus bridge, make sure
  840. * it has no valid mappings anymore.
  841. */
  842. for(pci = pciroot; pci != nil; pci = pci->link){
  843. if (pci->ccrb == 6 && pci->ccru == 7) {
  844. ushort bcr;
  845. /* reset the cardbus */
  846. bcr = pcicfgr16(pci, PciBCR);
  847. pcicfgw16(pci, PciBCR, 0x40 | bcr);
  848. delay(50);
  849. }
  850. }
  851. }
  852. }
  853. if(pciroot == nil)
  854. goto out;
  855. if(nobios) {
  856. /*
  857. * Work out how big the top bus is
  858. */
  859. pcibussize(pciroot, &mema, &ioa);
  860. /*
  861. * Align the windows and map it
  862. */
  863. ioa = 0x1000;
  864. mema = 0x90000000;
  865. pcilog("Mask sizes: mem=%lux io=%lux\n", mema, ioa);
  866. pcibusmap(pciroot, &mema, &ioa, 1);
  867. DBG("Sizes2: mem=%lux io=%lux\n", mema, ioa);
  868. unlock(&pcicfginitlock);
  869. return;
  870. }
  871. if (!nopcirouting)
  872. pcirouting();
  873. out:
  874. pcireservemem();
  875. unlock(&pcicfginitlock);
  876. if(getconf("*pcihinv"))
  877. pcihinv(nil);
  878. }
  879. static void
  880. pcireservemem(void)
  881. {
  882. int i;
  883. Pcidev *p;
  884. /*
  885. * mark all the physical address space claimed by pci devices
  886. * as in use, so that upaalloc doesn't give it out.
  887. */
  888. for(p=pciroot; p; p=p->list)
  889. for(i=0; i<nelem(p->mem); i++)
  890. if(p->mem[i].bar && (p->mem[i].bar&1) == 0)
  891. upareserve(p->mem[i].bar&~0x0F, p->mem[i].size);
  892. }
  893. static int
  894. pcicfgrw8raw(int tbdf, int rno, int data, int read)
  895. {
  896. int o, type, x;
  897. if(pcicfgmode == -1)
  898. pcicfginit();
  899. if(BUSBNO(tbdf))
  900. type = 0x01;
  901. else
  902. type = 0x00;
  903. x = -1;
  904. if(BUSDNO(tbdf) > pcimaxdno)
  905. return x;
  906. lock(&pcicfglock);
  907. switch(pcicfgmode){
  908. case 1:
  909. o = rno & 0x03;
  910. rno &= ~0x03;
  911. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  912. if(read)
  913. x = inb(PciDATA+o);
  914. else
  915. outb(PciDATA+o, data);
  916. outl(PciADDR, 0);
  917. break;
  918. case 2:
  919. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  920. outb(PciFORWARD, BUSBNO(tbdf));
  921. if(read)
  922. x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  923. else
  924. outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  925. outb(PciCSE, 0);
  926. break;
  927. }
  928. unlock(&pcicfglock);
  929. return x;
  930. }
  931. int
  932. pcicfgr8(Pcidev* pcidev, int rno)
  933. {
  934. return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
  935. }
  936. void
  937. pcicfgw8(Pcidev* pcidev, int rno, int data)
  938. {
  939. pcicfgrw8(pcidev->tbdf, rno, data, 0);
  940. }
  941. static int
  942. pcicfgrw16raw(int tbdf, int rno, int data, int read)
  943. {
  944. int o, type, x;
  945. if(pcicfgmode == -1)
  946. pcicfginit();
  947. if(BUSBNO(tbdf))
  948. type = 0x01;
  949. else
  950. type = 0x00;
  951. x = -1;
  952. if(BUSDNO(tbdf) > pcimaxdno)
  953. return x;
  954. lock(&pcicfglock);
  955. switch(pcicfgmode){
  956. case 1:
  957. o = rno & 0x02;
  958. rno &= ~0x03;
  959. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  960. if(read)
  961. x = ins(PciDATA+o);
  962. else
  963. outs(PciDATA+o, data);
  964. outl(PciADDR, 0);
  965. break;
  966. case 2:
  967. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  968. outb(PciFORWARD, BUSBNO(tbdf));
  969. if(read)
  970. x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  971. else
  972. outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  973. outb(PciCSE, 0);
  974. break;
  975. }
  976. unlock(&pcicfglock);
  977. return x;
  978. }
  979. int
  980. pcicfgr16(Pcidev* pcidev, int rno)
  981. {
  982. return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
  983. }
  984. void
  985. pcicfgw16(Pcidev* pcidev, int rno, int data)
  986. {
  987. pcicfgrw16(pcidev->tbdf, rno, data, 0);
  988. }
  989. static int
  990. pcicfgrw32raw(int tbdf, int rno, int data, int read)
  991. {
  992. int type, x;
  993. if(pcicfgmode == -1)
  994. pcicfginit();
  995. if(BUSBNO(tbdf))
  996. type = 0x01;
  997. else
  998. type = 0x00;
  999. x = -1;
  1000. if(BUSDNO(tbdf) > pcimaxdno)
  1001. return x;
  1002. lock(&pcicfglock);
  1003. switch(pcicfgmode){
  1004. case 1:
  1005. rno &= ~0x03;
  1006. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  1007. if(read)
  1008. x = inl(PciDATA);
  1009. else
  1010. outl(PciDATA, data);
  1011. outl(PciADDR, 0);
  1012. break;
  1013. case 2:
  1014. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  1015. outb(PciFORWARD, BUSBNO(tbdf));
  1016. if(read)
  1017. x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  1018. else
  1019. outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  1020. outb(PciCSE, 0);
  1021. break;
  1022. }
  1023. unlock(&pcicfglock);
  1024. return x;
  1025. }
  1026. int
  1027. pcicfgr32(Pcidev* pcidev, int rno)
  1028. {
  1029. return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
  1030. }
  1031. void
  1032. pcicfgw32(Pcidev* pcidev, int rno, int data)
  1033. {
  1034. pcicfgrw32(pcidev->tbdf, rno, data, 0);
  1035. }
  1036. Pcidev*
  1037. pcimatch(Pcidev* prev, int vid, int did)
  1038. {
  1039. if(pcicfgmode == -1)
  1040. pcicfginit();
  1041. if(prev == nil)
  1042. prev = pcilist;
  1043. else
  1044. prev = prev->list;
  1045. while(prev != nil){
  1046. if((vid == 0 || prev->vid == vid)
  1047. && (did == 0 || prev->did == did))
  1048. break;
  1049. prev = prev->list;
  1050. }
  1051. return prev;
  1052. }
  1053. Pcidev*
  1054. pcimatchtbdf(int tbdf)
  1055. {
  1056. Pcidev *pcidev;
  1057. if(pcicfgmode == -1)
  1058. pcicfginit();
  1059. for(pcidev = pcilist; pcidev != nil; pcidev = pcidev->list) {
  1060. if(pcidev->tbdf == tbdf)
  1061. break;
  1062. }
  1063. return pcidev;
  1064. }
  1065. uchar
  1066. pciipin(Pcidev *pci, uchar pin)
  1067. {
  1068. if (pci == nil)
  1069. pci = pcilist;
  1070. while (pci) {
  1071. uchar intl;
  1072. if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
  1073. return pci->intl;
  1074. if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
  1075. return intl;
  1076. pci = pci->list;
  1077. }
  1078. return 0;
  1079. }
  1080. static void
  1081. pcilhinv(Pcidev* p)
  1082. {
  1083. int i;
  1084. Pcidev *t;
  1085. if(p == nil) {
  1086. putstrn(PCICONS.output, PCICONS.ptr);
  1087. p = pciroot;
  1088. print("bus dev type vid did intl memory\n");
  1089. }
  1090. for(t = p; t != nil; t = t->link) {
  1091. print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
  1092. BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
  1093. t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
  1094. for(i = 0; i < nelem(p->mem); i++) {
  1095. if(t->mem[i].size == 0)
  1096. continue;
  1097. print("%d:%.8lux %d ", i,
  1098. t->mem[i].bar, t->mem[i].size);
  1099. }
  1100. if(t->ioa.bar || t->ioa.size)
  1101. print("ioa:%.8lux %d ", t->ioa.bar, t->ioa.size);
  1102. if(t->mema.bar || t->mema.size)
  1103. print("mema:%.8lux %d ", t->mema.bar, t->mema.size);
  1104. if(t->bridge)
  1105. print("->%d", BUSBNO(t->bridge->tbdf));
  1106. print("\n");
  1107. }
  1108. while(p != nil) {
  1109. if(p->bridge != nil)
  1110. pcilhinv(p->bridge);
  1111. p = p->link;
  1112. }
  1113. }
  1114. void
  1115. pcihinv(Pcidev* p)
  1116. {
  1117. if(pcicfgmode == -1)
  1118. pcicfginit();
  1119. lock(&pcicfginitlock);
  1120. pcilhinv(p);
  1121. unlock(&pcicfginitlock);
  1122. }
  1123. void
  1124. pcireset(void)
  1125. {
  1126. Pcidev *p;
  1127. if(pcicfgmode == -1)
  1128. pcicfginit();
  1129. for(p = pcilist; p != nil; p = p->list) {
  1130. /* don't mess with the bridges */
  1131. if(p->ccrb == 0x06)
  1132. continue;
  1133. pciclrbme(p);
  1134. }
  1135. }
  1136. void
  1137. pcisetioe(Pcidev* p)
  1138. {
  1139. p->pcr |= IOen;
  1140. pcicfgw16(p, PciPCR, p->pcr);
  1141. }
  1142. void
  1143. pciclrioe(Pcidev* p)
  1144. {
  1145. p->pcr &= ~IOen;
  1146. pcicfgw16(p, PciPCR, p->pcr);
  1147. }
  1148. void
  1149. pcisetbme(Pcidev* p)
  1150. {
  1151. p->pcr |= MASen;
  1152. pcicfgw16(p, PciPCR, p->pcr);
  1153. }
  1154. void
  1155. pciclrbme(Pcidev* p)
  1156. {
  1157. p->pcr &= ~MASen;
  1158. pcicfgw16(p, PciPCR, p->pcr);
  1159. }
  1160. void
  1161. pcisetmwi(Pcidev* p)
  1162. {
  1163. p->pcr |= MemWrInv;
  1164. pcicfgw16(p, PciPCR, p->pcr);
  1165. }
  1166. void
  1167. pciclrmwi(Pcidev* p)
  1168. {
  1169. p->pcr &= ~MemWrInv;
  1170. pcicfgw16(p, PciPCR, p->pcr);
  1171. }
  1172. static int
  1173. pcigetpmrb(Pcidev* p)
  1174. {
  1175. int ptr;
  1176. if(p->pmrb != 0)
  1177. return p->pmrb;
  1178. p->pmrb = -1;
  1179. /*
  1180. * If there are no extended capabilities implemented,
  1181. * (bit 4 in the status register) assume there's no standard
  1182. * power management method.
  1183. * Find the capabilities pointer based on PCI header type.
  1184. */
  1185. if(!(pcicfgr16(p, PciPSR) & 0x0010))
  1186. return -1;
  1187. switch(pcicfgr8(p, PciHDT)){
  1188. default:
  1189. return -1;
  1190. case 0: /* all other */
  1191. case 1: /* PCI to PCI bridge */
  1192. ptr = 0x34;
  1193. break;
  1194. case 2: /* CardBus bridge */
  1195. ptr = 0x14;
  1196. break;
  1197. }
  1198. ptr = pcicfgr32(p, ptr);
  1199. while(ptr != 0){
  1200. /*
  1201. * Check for validity.
  1202. * Can't be in standard header and must be double
  1203. * word aligned.
  1204. */
  1205. if(ptr < 0x40 || (ptr & ~0xFC))
  1206. return -1;
  1207. if(pcicfgr8(p, ptr) == 0x01){
  1208. p->pmrb = ptr;
  1209. return ptr;
  1210. }
  1211. ptr = pcicfgr8(p, ptr+1);
  1212. }
  1213. return -1;
  1214. }
  1215. int
  1216. pcigetpms(Pcidev* p)
  1217. {
  1218. int pmcsr, ptr;
  1219. if((ptr = pcigetpmrb(p)) == -1)
  1220. return -1;
  1221. /*
  1222. * Power Management Register Block:
  1223. * offset 0: Capability ID
  1224. * 1: next item pointer
  1225. * 2: capabilities
  1226. * 4: control/status
  1227. * 6: bridge support extensions
  1228. * 7: data
  1229. */
  1230. pmcsr = pcicfgr16(p, ptr+4);
  1231. return pmcsr & 0x0003;
  1232. }
  1233. int
  1234. pcisetpms(Pcidev* p, int state)
  1235. {
  1236. int ostate, pmc, pmcsr, ptr;
  1237. if((ptr = pcigetpmrb(p)) == -1)
  1238. return -1;
  1239. pmc = pcicfgr16(p, ptr+2);
  1240. pmcsr = pcicfgr16(p, ptr+4);
  1241. ostate = pmcsr & 0x0003;
  1242. pmcsr &= ~0x0003;
  1243. switch(state){
  1244. default:
  1245. return -1;
  1246. case 0:
  1247. break;
  1248. case 1:
  1249. if(!(pmc & 0x0200))
  1250. return -1;
  1251. break;
  1252. case 2:
  1253. if(!(pmc & 0x0400))
  1254. return -1;
  1255. break;
  1256. case 3:
  1257. break;
  1258. }
  1259. pmcsr |= state;
  1260. pcicfgw16(p, ptr+4, pmcsr);
  1261. return ostate;
  1262. }