sd53c8xx.c 54 KB

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  1. /*
  2. * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
  3. * Nigel Roles (nigel@9fs.org)
  4. *
  5. * 27/5/02 Fixed problems with transfers >= 256 * 512
  6. *
  7. * 13/3/01 Fixed microcode to support targets > 7
  8. *
  9. * 01/12/00 Removed previous comments. Fixed a small problem in
  10. * mismatch recovery for targets with synchronous offsets of >=16
  11. * connected to >=875s. Thanks, Jean.
  12. *
  13. * Known problems
  14. *
  15. * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
  16. */
  17. #define MAXTARGET 16 /* can be 8 or 16 */
  18. #include "u.h"
  19. #include "../port/lib.h"
  20. #include "mem.h"
  21. #include "dat.h"
  22. #include "fns.h"
  23. #include "io.h"
  24. #include "../port/sd.h"
  25. extern SDifc sd53c8xxifc;
  26. /**********************************/
  27. /* Portable configuration macros */
  28. /**********************************/
  29. //#define BOOTDEBUG
  30. //#define ASYNC_ONLY
  31. //#define INTERNAL_SCLK
  32. //#define ALWAYS_DO_WDTR
  33. #define WMR_DEBUG
  34. /**********************************/
  35. /* CPU specific macros */
  36. /**********************************/
  37. #define PRINTPREFIX "sd53c8xx: "
  38. #ifdef BOOTDEBUG
  39. #define KPRINT oprint
  40. #define IPRINT intrprint
  41. #define DEBUG(n) 1
  42. #define IFLUSH() iflush()
  43. #else
  44. static int idebug = 1;
  45. #define KPRINT if(0) iprint
  46. #define IPRINT if(idebug) iprint
  47. #define DEBUG(n) (0)
  48. #define IFLUSH()
  49. #endif /* BOOTDEBUG */
  50. /*******************************/
  51. /* General */
  52. /*******************************/
  53. #ifndef DMASEG
  54. #define DMASEG(x) PCIWADDR(x)
  55. #define legetl(x) (*(ulong*)(x))
  56. #define lesetl(x,v) (*(ulong*)(x) = (v))
  57. #define swabl(a,b,c)
  58. #else
  59. #endif /*DMASEG */
  60. #define DMASEG_TO_KADDR(x) KADDR((x)-PCIWINDOW)
  61. #define KPTR(x) ((x) == 0 ? 0 : DMASEG_TO_KADDR(x))
  62. #define MEGA 1000000L
  63. #ifdef INTERNAL_SCLK
  64. #define SCLK (33 * MEGA)
  65. #else
  66. #define SCLK (40 * MEGA)
  67. #endif /* INTERNAL_SCLK */
  68. #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
  69. #define MAXSYNCSCSIRATE (5 * MEGA)
  70. #define MAXFASTSYNCSCSIRATE (10 * MEGA)
  71. #define MAXULTRASYNCSCSIRATE (20 * MEGA)
  72. #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
  73. #define MAXASYNCCORERATE (25 * MEGA)
  74. #define MAXSYNCCORERATE (25 * MEGA)
  75. #define MAXFASTSYNCCORERATE (50 * MEGA)
  76. #define MAXULTRASYNCCORERATE (80 * MEGA)
  77. #define MAXULTRA2SYNCCORERATE (160 * MEGA)
  78. #define X_MSG 1
  79. #define X_MSG_SDTR 1
  80. #define X_MSG_WDTR 3
  81. struct na_patch {
  82. unsigned lwoff;
  83. unsigned char type;
  84. };
  85. typedef struct Ncr {
  86. uchar scntl0; /* 00 */
  87. uchar scntl1;
  88. uchar scntl2;
  89. uchar scntl3;
  90. uchar scid; /* 04 */
  91. uchar sxfer;
  92. uchar sdid;
  93. uchar gpreg;
  94. uchar sfbr; /* 08 */
  95. uchar socl;
  96. uchar ssid;
  97. uchar sbcl;
  98. uchar dstat; /* 0c */
  99. uchar sstat0;
  100. uchar sstat1;
  101. uchar sstat2;
  102. uchar dsa[4]; /* 10 */
  103. uchar istat; /* 14 */
  104. uchar istatpad[3];
  105. uchar ctest0; /* 18 */
  106. uchar ctest1;
  107. uchar ctest2;
  108. uchar ctest3;
  109. uchar temp[4]; /* 1c */
  110. uchar dfifo; /* 20 */
  111. uchar ctest4;
  112. uchar ctest5;
  113. uchar ctest6;
  114. uchar dbc[3]; /* 24 */
  115. uchar dcmd; /* 27 */
  116. uchar dnad[4]; /* 28 */
  117. uchar dsp[4]; /* 2c */
  118. uchar dsps[4]; /* 30 */
  119. uchar scratcha[4]; /* 34 */
  120. uchar dmode; /* 38 */
  121. uchar dien;
  122. uchar dwt;
  123. uchar dcntl;
  124. uchar adder[4]; /* 3c */
  125. uchar sien0; /* 40 */
  126. uchar sien1;
  127. uchar sist0;
  128. uchar sist1;
  129. uchar slpar; /* 44 */
  130. uchar slparpad0;
  131. uchar macntl;
  132. uchar gpcntl;
  133. uchar stime0; /* 48 */
  134. uchar stime1;
  135. uchar respid;
  136. uchar respidpad0;
  137. uchar stest0; /* 4c */
  138. uchar stest1;
  139. uchar stest2;
  140. uchar stest3;
  141. uchar sidl; /* 50 */
  142. uchar sidlpad[3];
  143. uchar sodl; /* 54 */
  144. uchar sodlpad[3];
  145. uchar sbdl; /* 58 */
  146. uchar sbdlpad[3];
  147. uchar scratchb[4]; /* 5c */
  148. } Ncr;
  149. typedef struct Movedata {
  150. uchar dbc[4];
  151. uchar pa[4];
  152. } Movedata;
  153. typedef enum NegoState {
  154. NeitherDone, WideInit, WideResponse, WideDone,
  155. SyncInit, SyncResponse, BothDone
  156. } NegoState;
  157. typedef enum State {
  158. Allocated, Queued, Active, Done
  159. } State;
  160. typedef struct Dsa Dsa;
  161. struct Dsa {
  162. uchar stateb;
  163. uchar result;
  164. uchar dmablks;
  165. uchar flag; /* setbyte(state,3,...) */
  166. union {
  167. ulong dmancr; /* For block transfer: NCR order (little-endian) */
  168. uchar dmaaddr[4];
  169. };
  170. uchar target; /* Target */
  171. uchar pad0[3];
  172. uchar lun; /* Logical Unit Number */
  173. uchar pad1[3];
  174. uchar scntl3;
  175. uchar sxfer;
  176. uchar pad2[2];
  177. uchar next[4]; /* chaining for SCRIPT (NCR byte order) */
  178. Dsa *freechain; /* chaining for freelist */
  179. Rendez;
  180. uchar scsi_id_buf[4];
  181. Movedata msg_out_buf;
  182. Movedata cmd_buf;
  183. Movedata data_buf;
  184. Movedata status_buf;
  185. uchar msg_out[10]; /* enough to include SDTR */
  186. uchar status;
  187. int p9status;
  188. uchar parityerror;
  189. };
  190. typedef enum Feature {
  191. BigFifo = 1, /* 536 byte fifo */
  192. BurstOpCodeFetch = 2, /* burst fetch opcodes */
  193. Prefetch = 4, /* prefetch 8 longwords */
  194. LocalRAM = 8, /* 4K longwords of local RAM */
  195. Differential = 16, /* Differential support */
  196. Wide = 32, /* Wide capable */
  197. Ultra = 64, /* Ultra capable */
  198. ClockDouble = 128, /* Has clock doubler */
  199. ClockQuad = 256, /* Has clock quadrupler (same as Ultra2) */
  200. Ultra2 = 256,
  201. } Feature;
  202. typedef enum Burst {
  203. Burst2 = 0,
  204. Burst4 = 1,
  205. Burst8 = 2,
  206. Burst16 = 3,
  207. Burst32 = 4,
  208. Burst64 = 5,
  209. Burst128 = 6
  210. } Burst;
  211. typedef struct Variant {
  212. ushort did;
  213. uchar maxrid; /* maximum allowed revision ID */
  214. char *name;
  215. Burst burst; /* codings for max burst */
  216. uchar maxsyncoff; /* max synchronous offset */
  217. uchar registers; /* number of 32 bit registers */
  218. unsigned feature;
  219. } Variant;
  220. static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
  221. #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
  222. #define NULTRASCF (NULTRA2SCF - 2)
  223. #define NSCF (NULTRASCF - 1)
  224. typedef struct Controller {
  225. Lock;
  226. struct {
  227. uchar scntl3;
  228. uchar stest2;
  229. } bios;
  230. uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
  231. NegoState s[MAXTARGET];
  232. uchar scntl3[MAXTARGET];
  233. uchar sxfer[MAXTARGET];
  234. uchar cap[MAXTARGET]; /* capabilities byte from Identify */
  235. ushort capvalid; /* bit per target for validity of cap[] */
  236. ushort wide; /* bit per target set if wide negotiated */
  237. ulong sclk; /* clock speed of controller */
  238. uchar clockmult; /* set by synctabinit */
  239. uchar ccf; /* CCF bits */
  240. uchar tpf; /* best tpf value for this controller */
  241. uchar feature; /* requested features */
  242. int running; /* is the script processor running? */
  243. int ssm; /* single step mode */
  244. Ncr *n; /* pointer to registers */
  245. Variant *v; /* pointer to variant type */
  246. ulong *script; /* where the real script is */
  247. ulong scriptpa; /* where the real script is */
  248. Pcidev* pcidev;
  249. SDev* sdev;
  250. struct {
  251. Lock;
  252. uchar head[4]; /* head of free list (NCR byte order) */
  253. Dsa *freechain;
  254. } dsalist;
  255. QLock q[MAXTARGET]; /* queues for each target */
  256. } Controller;
  257. #define SYNCOFFMASK(c) (((c)->v->maxsyncoff * 2) - 1)
  258. #define SSIDMASK(c) (((c)->v->feature & Wide) ? 15 : 7)
  259. /* ISTAT */
  260. enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
  261. /* DSTAT */
  262. enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
  263. /* SSTAT */
  264. enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
  265. static void setmovedata(Movedata*, ulong, ulong);
  266. static void advancedata(Movedata*, long);
  267. static int bios_set_differential(Controller *c);
  268. static char *phase[] = {
  269. "data out", "data in", "command", "status",
  270. "reserved out", "reserved in", "message out", "message in"
  271. };
  272. #ifdef BOOTDEBUG
  273. #define DEBUGSIZE 10240
  274. char debugbuf[DEBUGSIZE];
  275. char *debuglast;
  276. static void
  277. intrprint(char *format, ...)
  278. {
  279. if (debuglast == 0)
  280. debuglast = debugbuf;
  281. debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  282. }
  283. static void
  284. iflush()
  285. {
  286. int s;
  287. char *endp;
  288. s = splhi();
  289. if (debuglast == 0)
  290. debuglast = debugbuf;
  291. if (debuglast == debugbuf) {
  292. splx(s);
  293. return;
  294. }
  295. endp = debuglast;
  296. splx(s);
  297. screenputs(debugbuf, endp - debugbuf);
  298. s = splhi();
  299. memmove(debugbuf, endp, debuglast - endp);
  300. debuglast -= endp - debugbuf;
  301. splx(s);
  302. }
  303. static void
  304. oprint(char *format, ...)
  305. {
  306. int s;
  307. iflush();
  308. s = splhi();
  309. if (debuglast == 0)
  310. debuglast = debugbuf;
  311. debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  312. splx(s);
  313. iflush();
  314. }
  315. #endif
  316. #include "sd53c8xx.i"
  317. /*
  318. * We used to use a linked list of Dsas with nil as the terminator,
  319. * but occasionally the 896 card seems not to notice that the 0
  320. * is really a 0, and then it tries to reference the Dsa at address 0.
  321. * To address this, we use a sentinel dsa that links back to itself
  322. * and has state A_STATE_END. If the card takes an iteration or
  323. * two to notice that the state says A_STATE_END, that's no big
  324. * deal. Clearly this isn't the right approach, but I'm just
  325. * stumped. Even with this, we occasionally get prints about
  326. * "WSR set", usually with about the same frequency that the
  327. * card used to walk past 0.
  328. */
  329. static Dsa *dsaend;
  330. static Dsa*
  331. dsaallocnew(Controller *c)
  332. {
  333. Dsa *d;
  334. /* c->dsalist must be ilocked */
  335. d = xalloc(sizeof *d);
  336. if (d == nil)
  337. panic("sd53c8xx dsaallocnew: no memory");
  338. lesetl(d->next, legetl(c->dsalist.head));
  339. lesetl(&d->stateb, A_STATE_FREE);
  340. coherence();
  341. lesetl(c->dsalist.head, DMASEG(d));
  342. coherence();
  343. return d;
  344. }
  345. static Dsa *
  346. dsaalloc(Controller *c, int target, int lun)
  347. {
  348. Dsa *d;
  349. ilock(&c->dsalist);
  350. if ((d = c->dsalist.freechain) != 0) {
  351. if (DEBUG(1))
  352. IPRINT(PRINTPREFIX "%d/%d: reused dsa %lux\n", target, lun, (ulong)d);
  353. } else {
  354. d = dsaallocnew(c);
  355. if (DEBUG(1))
  356. IPRINT(PRINTPREFIX "%d/%d: allocated dsa %lux\n", target, lun, (ulong)d);
  357. }
  358. c->dsalist.freechain = d->freechain;
  359. lesetl(&d->stateb, A_STATE_ALLOCATED);
  360. iunlock(&c->dsalist);
  361. d->target = target;
  362. d->lun = lun;
  363. return d;
  364. }
  365. static void
  366. dsafree(Controller *c, Dsa *d)
  367. {
  368. ilock(&c->dsalist);
  369. d->freechain = c->dsalist.freechain;
  370. c->dsalist.freechain = d;
  371. lesetl(&d->stateb, A_STATE_FREE);
  372. iunlock(&c->dsalist);
  373. }
  374. static void
  375. dsadump(Controller *c)
  376. {
  377. Dsa *d;
  378. u32int *a;
  379. iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
  380. for(d=KPTR(legetl(c->dsalist.head)); d != dsaend; d=KPTR(legetl(d->next))){
  381. if(d == (void*)-1){
  382. iprint("\t dsa %p\n", d);
  383. break;
  384. }
  385. a = (u32int*)d;
  386. iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
  387. }
  388. /*
  389. a = KPTR(c->scriptpa+E_dsa_addr);
  390. iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  391. a[0], a[1], a[2], a[3], a[4]);
  392. a = KPTR(c->scriptpa+E_issue_addr);
  393. iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  394. a[0], a[1], a[2], a[3], a[4]);
  395. a = KPTR(c->scriptpa+E_issue_test_begin);
  396. e = KPTR(c->scriptpa+E_issue_test_end);
  397. iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
  398. i = 0;
  399. for(; a<e; a++){
  400. iprint(" %.8ux", *a);
  401. if(++i%8 == 0)
  402. iprint("\n");
  403. }
  404. if(i%8)
  405. iprint("\n");
  406. */
  407. }
  408. static Dsa *
  409. dsafind(Controller *c, uchar target, uchar lun, uchar state)
  410. {
  411. Dsa *d;
  412. for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  413. if (d->target != 0xff && d->target != target)
  414. continue;
  415. if (lun != 0xff && d->lun != lun)
  416. continue;
  417. if (state != 0xff && d->stateb != state)
  418. continue;
  419. break;
  420. }
  421. return d;
  422. }
  423. static void
  424. dumpncrregs(Controller *c, int intr)
  425. {
  426. int i;
  427. Ncr *n = c->n;
  428. int depth = c->v->registers / 4;
  429. if (intr) {
  430. IPRINT("sa = %.8lux\n", c->scriptpa);
  431. }
  432. else {
  433. KPRINT("sa = %.8lux\n", c->scriptpa);
  434. }
  435. for (i = 0; i < depth; i++) {
  436. int j;
  437. for (j = 0; j < 4; j++) {
  438. int k = j * depth + i;
  439. uchar *p;
  440. /* display little-endian to make 32-bit values readable */
  441. p = (uchar*)n+k*4;
  442. if (intr) {
  443. IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  444. }
  445. else {
  446. KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  447. }
  448. USED(p);
  449. }
  450. if (intr) {
  451. IPRINT("\n");
  452. }
  453. else {
  454. KPRINT("\n");
  455. }
  456. }
  457. }
  458. static int
  459. chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
  460. {
  461. /* find lowest entry >= tpf */
  462. int besttpf = 1000;
  463. int bestscfi = 0;
  464. int bestxferp = 0;
  465. int scf, xferp;
  466. int maxscf;
  467. if (c->v->feature & Ultra2)
  468. maxscf = NULTRA2SCF;
  469. else if (c->v->feature & Ultra)
  470. maxscf = NULTRASCF;
  471. else
  472. maxscf = NSCF;
  473. /*
  474. * search large clock factors first since this should
  475. * result in more reliable transfers
  476. */
  477. for (scf = maxscf; scf >= 1; scf--) {
  478. for (xferp = 0; xferp < 8; xferp++) {
  479. unsigned char v = c->synctab[scf - 1][xferp];
  480. if (v == 0)
  481. continue;
  482. if (v >= tpf && v < besttpf) {
  483. besttpf = v;
  484. bestscfi = scf;
  485. bestxferp = xferp;
  486. }
  487. }
  488. }
  489. if (besttpf == 1000)
  490. return 0;
  491. if (scfp)
  492. *scfp = bestscfi;
  493. if (xferpp)
  494. *xferpp = bestxferp;
  495. return besttpf;
  496. }
  497. static void
  498. synctabinit(Controller *c)
  499. {
  500. int scf;
  501. unsigned long scsilimit;
  502. int xferp;
  503. unsigned long cr, sr;
  504. int tpf;
  505. int fast;
  506. int maxscf;
  507. if (c->v->feature & Ultra2)
  508. maxscf = NULTRA2SCF;
  509. else if (c->v->feature & Ultra)
  510. maxscf = NULTRASCF;
  511. else
  512. maxscf = NSCF;
  513. /*
  514. * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
  515. * first spin of the 875), assume 80MHz
  516. * otherwise use the internal (33 Mhz) or external (40MHz) default
  517. */
  518. if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
  519. c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
  520. else
  521. c->sclk = SCLK;
  522. /*
  523. * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
  524. * invoke the doubler
  525. */
  526. if (SCLK <= 40000000) {
  527. if (c->v->feature & ClockDouble) {
  528. c->sclk *= 2;
  529. c->clockmult = 1;
  530. }
  531. else if (c->v->feature & ClockQuad) {
  532. c->sclk *= 4;
  533. c->clockmult = 1;
  534. }
  535. else
  536. c->clockmult = 0;
  537. }
  538. else
  539. c->clockmult = 0;
  540. /* derive CCF from sclk */
  541. /* woebetide anyone with SCLK < 16.7 or > 80MHz */
  542. if (c->sclk <= 25 * MEGA)
  543. c->ccf = 1;
  544. else if (c->sclk <= 3750000)
  545. c->ccf = 2;
  546. else if (c->sclk <= 50 * MEGA)
  547. c->ccf = 3;
  548. else if (c->sclk <= 75 * MEGA)
  549. c->ccf = 4;
  550. else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
  551. c->ccf = 5;
  552. else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
  553. c->ccf = 6;
  554. else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
  555. c->ccf = 7;
  556. for (scf = 1; scf < maxscf; scf++) {
  557. /* check for legal core rate */
  558. /* round up so we run slower for safety */
  559. cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
  560. if (cr <= MAXSYNCCORERATE) {
  561. scsilimit = MAXSYNCSCSIRATE;
  562. fast = 0;
  563. }
  564. else if (cr <= MAXFASTSYNCCORERATE) {
  565. scsilimit = MAXFASTSYNCSCSIRATE;
  566. fast = 1;
  567. }
  568. else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
  569. scsilimit = MAXULTRASYNCSCSIRATE;
  570. fast = 2;
  571. }
  572. else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
  573. scsilimit = MAXULTRA2SYNCSCSIRATE;
  574. fast = 3;
  575. }
  576. else
  577. continue;
  578. for (xferp = 11; xferp >= 4; xferp--) {
  579. int ok;
  580. int tp;
  581. /* calculate scsi rate - round up again */
  582. /* start from sclk for accuracy */
  583. int totaldivide = xferp * cf2[scf];
  584. sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
  585. if (sr > scsilimit)
  586. break;
  587. /*
  588. * now work out transfer period
  589. * round down now so that period is pessimistic
  590. */
  591. tp = (MEGA * 1000) / sr;
  592. /*
  593. * bounds check it
  594. */
  595. if (tp < 25 || tp > 255 * 4)
  596. continue;
  597. /*
  598. * spot stupid special case for Ultra or Ultra2
  599. * while working out factor
  600. */
  601. if (tp == 25)
  602. tpf = 10;
  603. else if (tp == 50)
  604. tpf = 12;
  605. else if (tp < 52)
  606. continue;
  607. else
  608. tpf = tp / 4;
  609. /*
  610. * now check tpf looks sensible
  611. * given core rate
  612. */
  613. switch (fast) {
  614. case 0:
  615. /* scf must be ccf for SCSI 1 */
  616. ok = tpf >= 50 && scf == c->ccf;
  617. break;
  618. case 1:
  619. ok = tpf >= 25 && tpf < 50;
  620. break;
  621. case 2:
  622. /*
  623. * must use xferp of 4, or 5 at a pinch
  624. * for an Ultra transfer
  625. */
  626. ok = xferp <= 5 && tpf >= 12 && tpf < 25;
  627. break;
  628. case 3:
  629. ok = xferp == 4 && (tpf == 10 || tpf == 11);
  630. break;
  631. default:
  632. ok = 0;
  633. }
  634. if (!ok)
  635. continue;
  636. c->synctab[scf - 1][xferp - 4] = tpf;
  637. }
  638. }
  639. #ifndef NO_ULTRA2
  640. if (c->v->feature & Ultra2)
  641. tpf = 10;
  642. else
  643. #endif
  644. if (c->v->feature & Ultra)
  645. tpf = 12;
  646. else
  647. tpf = 25;
  648. for (; tpf < 256; tpf++) {
  649. if (chooserate(c, tpf, &scf, &xferp) == tpf) {
  650. unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
  651. unsigned long khz = (MEGA + tp - 1) / (tp);
  652. KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
  653. tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
  654. xferp + 4, khz / 1000, khz % 1000);
  655. USED(khz);
  656. if (c->tpf == 0)
  657. c->tpf = tpf; /* note lowest value for controller */
  658. }
  659. }
  660. }
  661. static void
  662. synctodsa(Dsa *dsa, Controller *c)
  663. {
  664. /*
  665. KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
  666. dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
  667. */
  668. dsa->scntl3 = c->scntl3[dsa->target];
  669. dsa->sxfer = c->sxfer[dsa->target];
  670. }
  671. static void
  672. setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
  673. {
  674. c->scntl3[target] =
  675. (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
  676. c->sxfer[target] = (xferp << 5) | reqack;
  677. c->s[target] = BothDone;
  678. if (dsa) {
  679. synctodsa(dsa, c);
  680. c->n->scntl3 = c->scntl3[target];
  681. c->n->sxfer = c->sxfer[target];
  682. }
  683. }
  684. static void
  685. setasync(Dsa *dsa, Controller *c, int target)
  686. {
  687. setsync(dsa, c, target, 0, c->ccf, 0, 0);
  688. }
  689. static void
  690. setwide(Dsa *dsa, Controller *c, int target, uchar wide)
  691. {
  692. c->scntl3[target] = wide ? (1 << 3) : 0;
  693. setasync(dsa, c, target);
  694. c->s[target] = WideDone;
  695. }
  696. static int
  697. buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
  698. {
  699. *buf++ = X_MSG;
  700. *buf++ = 3;
  701. *buf++ = X_MSG_SDTR;
  702. *buf++ = tpf;
  703. *buf = offset;
  704. return 5;
  705. }
  706. static int
  707. buildwdtrmsg(uchar *buf, uchar expo)
  708. {
  709. *buf++ = X_MSG;
  710. *buf++ = 2;
  711. *buf++ = X_MSG_WDTR;
  712. *buf = expo;
  713. return 4;
  714. }
  715. static void
  716. start(Controller *c, long entry)
  717. {
  718. ulong p;
  719. if (c->running)
  720. panic(PRINTPREFIX "start called while running");
  721. c->running = 1;
  722. p = c->scriptpa + entry;
  723. lesetl(c->n->dsp, p);
  724. coherence();
  725. if (c->ssm)
  726. c->n->dcntl |= 0x4; /* start DMA in SSI mode */
  727. }
  728. static void
  729. ncrcontinue(Controller *c)
  730. {
  731. if (c->running)
  732. panic(PRINTPREFIX "ncrcontinue called while running");
  733. /* set the start DMA bit to continue execution */
  734. c->running = 1;
  735. coherence();
  736. c->n->dcntl |= 0x4;
  737. }
  738. static void
  739. softreset(Controller *c)
  740. {
  741. Ncr *n = c->n;
  742. n->istat = Srst; /* software reset */
  743. n->istat = 0;
  744. /* general initialisation */
  745. n->scid = (1 << 6) | 7; /* respond to reselect, ID 7 */
  746. n->respid = 1 << 7; /* response ID = 7 */
  747. #ifdef INTERNAL_SCLK
  748. n->stest1 = 0x80; /* disable external scsi clock */
  749. #else
  750. n->stest1 = 0x00;
  751. #endif
  752. n->stime0 = 0xdd; /* about 0.5 second timeout on each device */
  753. n->scntl0 |= 0x8; /* Enable parity checking */
  754. /* continued setup */
  755. n->sien0 = 0x8f;
  756. n->sien1 = 0x04;
  757. n->dien = 0x7d;
  758. n->stest3 = 0x80; /* TolerANT enable */
  759. c->running = 0;
  760. if (c->v->feature & BigFifo)
  761. n->ctest5 = (1 << 5);
  762. n->dmode = c->v->burst << 6; /* set burst length bits */
  763. if (c->v->burst & 4)
  764. n->ctest5 |= (1 << 2); /* including overflow into ctest5 bit 2 */
  765. if (c->v->feature & Prefetch)
  766. n->dcntl |= (1 << 5); /* prefetch enable */
  767. else if (c->v->feature & BurstOpCodeFetch)
  768. n->dmode |= (1 << 1); /* burst opcode fetch */
  769. if (c->v->feature & Differential) {
  770. /* chip capable */
  771. if ((c->feature & Differential) || bios_set_differential(c)) {
  772. /* user enabled, or some evidence bios set differential */
  773. if (n->sstat2 & (1 << 2))
  774. print(PRINTPREFIX "can't go differential; wrong cable\n");
  775. else {
  776. n->stest2 = (1 << 5);
  777. print(PRINTPREFIX "differential mode set\n");
  778. }
  779. }
  780. }
  781. if (c->clockmult) {
  782. n->stest1 |= (1 << 3); /* power up doubler */
  783. delay(2);
  784. n->stest3 |= (1 << 5); /* stop clock */
  785. n->stest1 |= (1 << 2); /* enable doubler */
  786. n->stest3 &= ~(1 << 5); /* start clock */
  787. /* pray */
  788. }
  789. }
  790. static void
  791. msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
  792. {
  793. uchar histpf, hisreqack;
  794. int tpf;
  795. int scf, xferp;
  796. int len;
  797. Ncr *n = c->n;
  798. switch (c->s[dsa->target]) {
  799. case SyncInit:
  800. switch (msg) {
  801. case A_SIR_MSG_SDTR:
  802. /* reply to my SDTR */
  803. histpf = n->scratcha[2];
  804. hisreqack = n->scratcha[3];
  805. KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
  806. dsa->target, histpf, hisreqack);
  807. if (hisreqack == 0)
  808. setasync(dsa, c, dsa->target);
  809. else {
  810. /* hisreqack should be <= c->v->maxsyncoff */
  811. tpf = chooserate(c, histpf, &scf, &xferp);
  812. KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
  813. dsa->target, tpf, hisreqack);
  814. setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  815. }
  816. *cont = -2;
  817. return;
  818. case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  819. /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  820. KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  821. KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  822. setasync(dsa, c, dsa->target);
  823. *cont = E_to_decisions;
  824. return;
  825. case A_SIR_MSG_REJECT:
  826. /* rejection of my SDTR */
  827. KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
  828. //async:
  829. KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  830. setasync(dsa, c, dsa->target);
  831. *cont = -2;
  832. return;
  833. }
  834. break;
  835. case WideInit:
  836. switch (msg) {
  837. case A_SIR_MSG_WDTR:
  838. /* reply to my WDTR */
  839. KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
  840. dsa->target, n->scratcha[2]);
  841. setwide(dsa, c, dsa->target, n->scratcha[2]);
  842. *cont = -2;
  843. return;
  844. case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  845. /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  846. KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  847. setwide(dsa, c, dsa->target, 0);
  848. *cont = E_to_decisions;
  849. return;
  850. case A_SIR_MSG_REJECT:
  851. /* rejection of my SDTR */
  852. KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
  853. setwide(dsa, c, dsa->target, 0);
  854. *cont = -2;
  855. return;
  856. }
  857. break;
  858. case NeitherDone:
  859. case WideDone:
  860. case BothDone:
  861. switch (msg) {
  862. case A_SIR_MSG_WDTR: {
  863. uchar hiswide, mywide;
  864. hiswide = n->scratcha[2];
  865. mywide = (c->v->feature & Wide) != 0;
  866. KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
  867. dsa->target, hiswide);
  868. if (hiswide < mywide)
  869. mywide = hiswide;
  870. KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
  871. dsa->target, mywide);
  872. setwide(dsa, c, dsa->target, mywide);
  873. len = buildwdtrmsg(dsa->msg_out, mywide);
  874. setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  875. *cont = E_response;
  876. c->s[dsa->target] = WideResponse;
  877. return;
  878. }
  879. case A_SIR_MSG_SDTR:
  880. #ifdef ASYNC_ONLY
  881. *cont = E_reject;
  882. return;
  883. #else
  884. /* target decides to renegotiate */
  885. histpf = n->scratcha[2];
  886. hisreqack = n->scratcha[3];
  887. KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
  888. dsa->target, histpf, hisreqack);
  889. if (hisreqack == 0) {
  890. /* he wants asynchronous */
  891. setasync(dsa, c, dsa->target);
  892. tpf = 0;
  893. }
  894. else {
  895. /* he wants synchronous */
  896. tpf = chooserate(c, histpf, &scf, &xferp);
  897. if (hisreqack > c->v->maxsyncoff)
  898. hisreqack = c->v->maxsyncoff;
  899. KPRINT(PRINTPREFIX "%d: using %d %d\n",
  900. dsa->target, tpf, hisreqack);
  901. setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  902. }
  903. /* build my SDTR message */
  904. len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
  905. setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  906. *cont = E_response;
  907. c->s[dsa->target] = SyncResponse;
  908. return;
  909. #endif
  910. }
  911. break;
  912. case WideResponse:
  913. switch (msg) {
  914. case A_SIR_EV_RESPONSE_OK:
  915. c->s[dsa->target] = WideDone;
  916. KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
  917. *cont = -2;
  918. return;
  919. case A_SIR_MSG_REJECT:
  920. setwide(dsa, c, dsa->target, 0);
  921. KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
  922. *cont = -2;
  923. return;
  924. }
  925. break;
  926. case SyncResponse:
  927. switch (msg) {
  928. case A_SIR_EV_RESPONSE_OK:
  929. c->s[dsa->target] = BothDone;
  930. KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
  931. dsa->target, phase[n->sstat1 & 7]);
  932. *cont = -2;
  933. return; /* chf */
  934. case A_SIR_MSG_REJECT:
  935. setasync(dsa, c, dsa->target);
  936. KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
  937. *cont = -2;
  938. return;
  939. }
  940. break;
  941. }
  942. KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
  943. dsa->target, c->s[dsa->target], msg);
  944. *wakeme = 1;
  945. return;
  946. }
  947. static void
  948. calcblockdma(Dsa *d, ulong base, ulong count)
  949. {
  950. ulong blocks;
  951. if (DEBUG(3))
  952. blocks = 0;
  953. else {
  954. blocks = count / A_BSIZE;
  955. if (blocks > 255)
  956. blocks = 255;
  957. }
  958. d->dmablks = blocks;
  959. d->dmaaddr[0] = base;
  960. d->dmaaddr[1] = base >> 8;
  961. d->dmaaddr[2] = base >> 16;
  962. d->dmaaddr[3] = base >> 24;
  963. setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
  964. d->flag = legetl(d->data_buf.dbc) == 0;
  965. }
  966. static ulong
  967. read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
  968. {
  969. ulong dbc;
  970. uchar dfifo = n->dfifo;
  971. int inchip;
  972. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  973. if (n->ctest5 & (1 << 5))
  974. inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
  975. else
  976. inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
  977. if (inchip) {
  978. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
  979. dsa->target, dsa->lun, inchip);
  980. }
  981. if (n->sxfer & SYNCOFFMASK(c)) {
  982. /* SCSI FIFO */
  983. uchar fifo = n->sstat1 >> 4;
  984. if (c->v->maxsyncoff > 8)
  985. fifo |= (n->sstat2 & (1 << 4));
  986. if (fifo) {
  987. inchip += fifo;
  988. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
  989. dsa->target, dsa->lun, fifo);
  990. }
  991. }
  992. else {
  993. if (n->sstat0 & (1 << 7)) {
  994. inchip++;
  995. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
  996. dsa->target, dsa->lun);
  997. }
  998. if (n->sstat2 & (1 << 7)) {
  999. inchip++;
  1000. IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
  1001. dsa->target, dsa->lun);
  1002. }
  1003. }
  1004. USED(inchip);
  1005. return dbc;
  1006. }
  1007. static ulong
  1008. write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
  1009. {
  1010. ulong dbc;
  1011. uchar dfifo = n->dfifo;
  1012. int inchip;
  1013. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  1014. USED(dsa);
  1015. if (n->ctest5 & (1 << 5))
  1016. inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
  1017. else
  1018. inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
  1019. #ifdef WMR_DEBUG
  1020. if (inchip) {
  1021. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
  1022. dsa->target, dsa->lun, inchip);
  1023. }
  1024. #endif
  1025. if (n->sstat0 & (1 << 5)) {
  1026. inchip++;
  1027. #ifdef WMR_DEBUG
  1028. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
  1029. #endif
  1030. }
  1031. if (n->sstat2 & (1 << 5)) {
  1032. inchip++;
  1033. #ifdef WMR_DEBUG
  1034. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
  1035. #endif
  1036. }
  1037. if (n->sxfer & SYNCOFFMASK(c)) {
  1038. /* synchronous SODR */
  1039. if (n->sstat0 & (1 << 6)) {
  1040. inchip++;
  1041. #ifdef WMR_DEBUG
  1042. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
  1043. dsa->target, dsa->lun);
  1044. #endif
  1045. }
  1046. if (n->sstat2 & (1 << 6)) {
  1047. inchip++;
  1048. #ifdef WMR_DEBUG
  1049. IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
  1050. dsa->target, dsa->lun);
  1051. #endif
  1052. }
  1053. }
  1054. /* clear the dma fifo */
  1055. n->ctest3 |= (1 << 2);
  1056. /* wait till done */
  1057. while ((n->dstat & Dfe) == 0)
  1058. ;
  1059. return dbc + inchip;
  1060. }
  1061. static void
  1062. sd53c8xxinterrupt(Ureg *ur, void *a)
  1063. {
  1064. uchar istat, dstat;
  1065. ushort sist;
  1066. int wakeme = 0;
  1067. int cont = -1;
  1068. Dsa *dsa;
  1069. ulong dsapa;
  1070. Controller *c = a;
  1071. Ncr *n = c->n;
  1072. USED(ur);
  1073. if (DEBUG(1)) {
  1074. IPRINT(PRINTPREFIX "int\n");
  1075. }
  1076. ilock(c);
  1077. istat = n->istat;
  1078. if (istat & Intf) {
  1079. Dsa *d;
  1080. int wokesomething = 0;
  1081. if (DEBUG(1)) {
  1082. IPRINT(PRINTPREFIX "Intfly\n");
  1083. }
  1084. n->istat = Intf;
  1085. /* search for structures in A_STATE_DONE */
  1086. for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  1087. if (d->stateb == A_STATE_DONE) {
  1088. d->p9status = d->status;
  1089. if (DEBUG(1)) {
  1090. IPRINT(PRINTPREFIX "waking up dsa %lux\n", (ulong)d);
  1091. }
  1092. wakeup(d);
  1093. wokesomething = 1;
  1094. }
  1095. }
  1096. if (!wokesomething) {
  1097. IPRINT(PRINTPREFIX "nothing to wake up\n");
  1098. }
  1099. }
  1100. if ((istat & (Sip | Dip)) == 0) {
  1101. if (DEBUG(1)) {
  1102. IPRINT(PRINTPREFIX "int end %x\n", istat);
  1103. }
  1104. iunlock(c);
  1105. return;
  1106. }
  1107. sist = (n->sist1<<8)|n->sist0; /* BUG? can two-byte read be inconsistent? */
  1108. dstat = n->dstat;
  1109. dsapa = legetl(n->dsa);
  1110. /*
  1111. * Can't compute dsa until we know that dsapa is valid.
  1112. */
  1113. if(dsapa < -KZERO)
  1114. dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
  1115. else{
  1116. dsa = nil;
  1117. /*
  1118. * happens at startup on some cards but we
  1119. * don't actually deref dsa because none of the
  1120. * flags we are about are set.
  1121. * still, print in case that changes and we're
  1122. * about to dereference nil.
  1123. */
  1124. iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
  1125. }
  1126. c->running = 0;
  1127. if (istat & Sip) {
  1128. if (DEBUG(1)) {
  1129. IPRINT("sist = %.4x\n", sist);
  1130. }
  1131. if (sist & 0x80) {
  1132. ulong addr;
  1133. ulong sa;
  1134. ulong dbc;
  1135. ulong tbc;
  1136. int dmablks;
  1137. ulong dmaaddr;
  1138. addr = legetl(n->dsp);
  1139. sa = addr - c->scriptpa;
  1140. if (DEBUG(1) || DEBUG(2)) {
  1141. IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
  1142. dsa->target, dsa->lun, sa);
  1143. }
  1144. /*
  1145. * now recover
  1146. */
  1147. if (sa == E_data_in_mismatch) {
  1148. /*
  1149. * though this is a failure in the residue, there may have been blocks
  1150. * as well. if so, dmablks will not have been zeroed, since the state
  1151. * was not saved by the microcode.
  1152. */
  1153. dbc = read_mismatch_recover(c, n, dsa);
  1154. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1155. dsa->dmablks = 0;
  1156. n->scratcha[2] = 0;
  1157. advancedata(&dsa->data_buf, tbc);
  1158. if (DEBUG(1) || DEBUG(2)) {
  1159. IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
  1160. dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
  1161. }
  1162. cont = E_data_mismatch_recover;
  1163. }
  1164. else if (sa == E_data_in_block_mismatch) {
  1165. dbc = read_mismatch_recover(c, n, dsa);
  1166. tbc = A_BSIZE - dbc;
  1167. /* recover current state from registers */
  1168. dmablks = n->scratcha[2];
  1169. dmaaddr = legetl(n->scratchb);
  1170. /* we have got to dmaaddr + tbc */
  1171. /* we have dmablks * A_BSIZE - tbc + residue left to do */
  1172. /* so remaining transfer is */
  1173. IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
  1174. dmaaddr, tbc, dmablks);
  1175. calcblockdma(dsa, dmaaddr + tbc,
  1176. dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
  1177. /* copy changes into scratch registers */
  1178. IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
  1179. dsa->dmablks, legetl(dsa->dmaaddr),
  1180. legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
  1181. n->scratcha[2] = dsa->dmablks;
  1182. lesetl(n->scratchb, dsa->dmancr);
  1183. cont = E_data_block_mismatch_recover;
  1184. }
  1185. else if (sa == E_data_out_mismatch) {
  1186. dbc = write_mismatch_recover(c, n, dsa);
  1187. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1188. dsa->dmablks = 0;
  1189. n->scratcha[2] = 0;
  1190. advancedata(&dsa->data_buf, tbc);
  1191. if (DEBUG(1) || DEBUG(2)) {
  1192. IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
  1193. dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
  1194. }
  1195. cont = E_data_mismatch_recover;
  1196. }
  1197. else if (sa == E_data_out_block_mismatch) {
  1198. dbc = write_mismatch_recover(c, n, dsa);
  1199. tbc = legetl(dsa->data_buf.dbc) - dbc;
  1200. /* recover current state from registers */
  1201. dmablks = n->scratcha[2];
  1202. dmaaddr = legetl(n->scratchb);
  1203. /* we have got to dmaaddr + tbc */
  1204. /* we have dmablks blocks - tbc + residue left to do */
  1205. /* so remaining transfer is */
  1206. IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
  1207. dmaaddr, tbc, dmablks);
  1208. calcblockdma(dsa, dmaaddr + tbc,
  1209. dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
  1210. /* copy changes into scratch registers */
  1211. n->scratcha[2] = dsa->dmablks;
  1212. lesetl(n->scratchb, dsa->dmancr);
  1213. cont = E_data_block_mismatch_recover;
  1214. }
  1215. else if (sa == E_id_out_mismatch) {
  1216. /*
  1217. * target switched phases while attention held during
  1218. * message out. The possibilities are:
  1219. * 1. It didn't like the last message. This is indicated
  1220. * by the new phase being message_in. Use script to recover
  1221. *
  1222. * 2. It's not SCSI-II compliant. The new phase will be other
  1223. * than message_in. We should also indicate that the device
  1224. * is asynchronous, if it's the SDTR that got ignored
  1225. *
  1226. * For now, if the phase switch is not to message_in, and
  1227. * and it happens after IDENTIFY and before SDTR, we
  1228. * notify the negotiation state machine.
  1229. */
  1230. ulong lim = legetl(dsa->msg_out_buf.dbc);
  1231. uchar p = n->sstat1 & 7;
  1232. dbc = write_mismatch_recover(c, n, dsa);
  1233. tbc = lim - dbc;
  1234. IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
  1235. dsa->target, dsa->lun, tbc, lim, phase[p]);
  1236. if (p != MessageIn && tbc == 1) {
  1237. msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
  1238. }
  1239. else
  1240. cont = E_id_out_mismatch_recover;
  1241. }
  1242. else if (sa == E_cmd_out_mismatch) {
  1243. /*
  1244. * probably the command count is longer than the device wants ...
  1245. */
  1246. ulong lim = legetl(dsa->cmd_buf.dbc);
  1247. uchar p = n->sstat1 & 7;
  1248. dbc = write_mismatch_recover(c, n, dsa);
  1249. tbc = lim - dbc;
  1250. IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
  1251. dsa->target, dsa->lun, tbc, lim, phase[p]);
  1252. USED(p, tbc);
  1253. cont = E_to_decisions;
  1254. }
  1255. else {
  1256. IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
  1257. dsa->target, dsa->lun, sa,
  1258. phase[n->dcmd & 7],
  1259. phase[n->sstat1 & 7]);
  1260. dumpncrregs(c, 1);
  1261. dsa->p9status = SDeio; /* chf */
  1262. wakeme = 1;
  1263. }
  1264. }
  1265. /*else*/ if (sist & 0x400) {
  1266. if (DEBUG(0)) {
  1267. IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
  1268. }
  1269. dsa->p9status = SDtimeout;
  1270. dsa->stateb = A_STATE_DONE;
  1271. coherence();
  1272. softreset(c);
  1273. cont = E_issue_check;
  1274. wakeme = 1;
  1275. }
  1276. if (sist & 0x1) {
  1277. IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
  1278. dsa->parityerror = 1;
  1279. }
  1280. if (sist & 0x4) {
  1281. IPRINT(PRINTPREFIX "%s%d lun %d: unexpected disconnect\n",
  1282. c->sdev->name, dsa->target, dsa->lun);
  1283. dumpncrregs(c, 1);
  1284. //wakeme = 1;
  1285. dsa->p9status = SDeio;
  1286. }
  1287. }
  1288. if (istat & Dip) {
  1289. if (DEBUG(1)) {
  1290. IPRINT("dstat = %.2x\n", dstat);
  1291. }
  1292. /*else*/ if (dstat & Ssi) {
  1293. ulong w = legetl(n->dsp) - c->scriptpa;
  1294. IPRINT("[%lux]", w);
  1295. USED(w);
  1296. cont = -2; /* restart */
  1297. }
  1298. if (dstat & Sir) {
  1299. switch (legetl(n->dsps)) {
  1300. case A_SIR_MSG_IO_COMPLETE:
  1301. dsa->p9status = dsa->status;
  1302. wakeme = 1;
  1303. break;
  1304. case A_SIR_MSG_SDTR:
  1305. case A_SIR_MSG_WDTR:
  1306. case A_SIR_MSG_REJECT:
  1307. case A_SIR_EV_RESPONSE_OK:
  1308. msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
  1309. break;
  1310. case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
  1311. /* back up one in the data transfer */
  1312. IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
  1313. dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
  1314. if (dsa->flag == 2) {
  1315. IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
  1316. dsa->target, dsa->lun);
  1317. }
  1318. else {
  1319. calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
  1320. dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
  1321. }
  1322. cont = -2;
  1323. break;
  1324. case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
  1325. IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
  1326. n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
  1327. dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
  1328. dumpncrregs(c, 1);
  1329. wakeme = 1;
  1330. break;
  1331. case A_SIR_NOTIFY_LOAD_STATE:
  1332. IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
  1333. if (dsa == (void*)KZERO || dsa == (void*)-1) {
  1334. dsadump(c);
  1335. dumpncrregs(c, 1);
  1336. panic("bad dsa in load_state");
  1337. }
  1338. cont = -2;
  1339. break;
  1340. case A_SIR_NOTIFY_MSG_IN:
  1341. IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
  1342. dsa->target, dsa->lun, n->sfbr);
  1343. cont = -2;
  1344. break;
  1345. case A_SIR_NOTIFY_DISC:
  1346. IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
  1347. goto dsadump;
  1348. case A_SIR_NOTIFY_STATUS:
  1349. IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
  1350. cont = -2;
  1351. break;
  1352. case A_SIR_NOTIFY_COMMAND:
  1353. IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
  1354. cont = -2;
  1355. break;
  1356. case A_SIR_NOTIFY_DATA_IN:
  1357. IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
  1358. dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
  1359. cont = -2;
  1360. break;
  1361. case A_SIR_NOTIFY_BLOCK_DATA_IN:
  1362. IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
  1363. dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
  1364. cont = -2;
  1365. break;
  1366. case A_SIR_NOTIFY_DATA_OUT:
  1367. IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
  1368. cont = -2;
  1369. break;
  1370. case A_SIR_NOTIFY_DUMP:
  1371. IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
  1372. dumpncrregs(c, 1);
  1373. cont = -2;
  1374. break;
  1375. case A_SIR_NOTIFY_DUMP2:
  1376. IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
  1377. IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
  1378. IPRINT(" dsa %lux", legetl(n->dsa));
  1379. IPRINT(" sfbr %ux", n->sfbr);
  1380. IPRINT(" a %lux", legetl(n->scratcha));
  1381. IPRINT(" b %lux", legetl(n->scratchb));
  1382. IPRINT(" ssid %ux", n->ssid);
  1383. IPRINT("\n");
  1384. cont = -2;
  1385. break;
  1386. case A_SIR_NOTIFY_WAIT_RESELECT:
  1387. IPRINT(PRINTPREFIX "wait reselect\n");
  1388. cont = -2;
  1389. break;
  1390. case A_SIR_NOTIFY_RESELECT:
  1391. IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
  1392. n->ssid, n->sfbr, TK2MS(m->ticks));
  1393. cont = -2;
  1394. break;
  1395. case A_SIR_NOTIFY_ISSUE:
  1396. IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
  1397. dsadump:
  1398. IPRINT(" tgt=%d", dsa->target);
  1399. IPRINT(" time=%ld", TK2MS(m->ticks));
  1400. IPRINT("\n");
  1401. cont = -2;
  1402. break;
  1403. case A_SIR_NOTIFY_ISSUE_CHECK:
  1404. IPRINT(PRINTPREFIX "issue check\n");
  1405. cont = -2;
  1406. break;
  1407. case A_SIR_NOTIFY_SIGP:
  1408. IPRINT(PRINTPREFIX "responded to SIGP\n");
  1409. cont = -2;
  1410. break;
  1411. case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
  1412. ulong *dsp = c->script + (legetl(n->dsp)-c->scriptpa)/4;
  1413. int x;
  1414. IPRINT(PRINTPREFIX "code at %lux", dsp - c->script);
  1415. for (x = 0; x < 6; x++) {
  1416. IPRINT(" %.8lux", dsp[x]);
  1417. }
  1418. IPRINT("\n");
  1419. USED(dsp);
  1420. cont = -2;
  1421. break;
  1422. }
  1423. case A_SIR_NOTIFY_WSR:
  1424. IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
  1425. cont = -2;
  1426. break;
  1427. case A_SIR_NOTIFY_LOAD_SYNC:
  1428. IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
  1429. dsa->target, dsa->lun, n->scntl3, n->sxfer);
  1430. cont = -2;
  1431. break;
  1432. case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
  1433. if (DEBUG(2)) {
  1434. IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
  1435. dsa->target, dsa->lun);
  1436. }
  1437. cont = -2;
  1438. break;
  1439. case A_error_reselected: /* dsa isn't valid here */
  1440. iprint(PRINTPREFIX "reselection error\n");
  1441. dumpncrregs(c, 1);
  1442. for (dsa = KPTR(legetl(c->dsalist.head)); dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
  1443. IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
  1444. }
  1445. break;
  1446. default:
  1447. IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
  1448. dsa->target, dsa->lun, legetl(n->dsps));
  1449. dumpncrregs(c, 1);
  1450. wakeme = 1;
  1451. }
  1452. }
  1453. /*else*/ if (dstat & Iid) {
  1454. int i, target, lun;
  1455. ulong addr, dbc, *v;
  1456. addr = legetl(n->dsp);
  1457. if(dsa){
  1458. target = dsa->target;
  1459. lun = dsa->lun;
  1460. }else{
  1461. target = -1;
  1462. lun = -1;
  1463. }
  1464. dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
  1465. // if(dsa == nil)
  1466. idebug++;
  1467. IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
  1468. target, lun,
  1469. addr, addr - c->scriptpa, dbc);
  1470. addr = (ulong)c->script + addr - c->scriptpa;
  1471. addr -= 64;
  1472. addr &= ~63;
  1473. v = (ulong*)addr;
  1474. for(i=0; i<8; i++){
  1475. IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n",
  1476. addr, v[0], v[1], v[2], v[3]);
  1477. addr += 4*4;
  1478. v += 4;
  1479. }
  1480. USED(addr, dbc);
  1481. if(dsa == nil){
  1482. dsadump(c);
  1483. dumpncrregs(c, 1);
  1484. panic("bad dsa");
  1485. }
  1486. dsa->p9status = SDeio;
  1487. wakeme = 1;
  1488. }
  1489. /*else*/ if (dstat & Bf) {
  1490. IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
  1491. dumpncrregs(c, 1);
  1492. dsa->p9status = SDeio;
  1493. wakeme = 1;
  1494. }
  1495. }
  1496. if (cont == -2)
  1497. ncrcontinue(c);
  1498. else if (cont >= 0)
  1499. start(c, cont);
  1500. if (wakeme){
  1501. if(dsa->p9status == SDnostatus)
  1502. dsa->p9status = SDeio;
  1503. wakeup(dsa);
  1504. }
  1505. iunlock(c);
  1506. if (DEBUG(1)) {
  1507. IPRINT(PRINTPREFIX "int end 1\n");
  1508. }
  1509. }
  1510. static int
  1511. done(void *arg)
  1512. {
  1513. return ((Dsa *)arg)->p9status != SDnostatus;
  1514. }
  1515. static void
  1516. setmovedata(Movedata *d, ulong pa, ulong bc)
  1517. {
  1518. d->pa[0] = pa;
  1519. d->pa[1] = pa>>8;
  1520. d->pa[2] = pa>>16;
  1521. d->pa[3] = pa>>24;
  1522. d->dbc[0] = bc;
  1523. d->dbc[1] = bc>>8;
  1524. d->dbc[2] = bc>>16;
  1525. d->dbc[3] = bc>>24;
  1526. }
  1527. static void
  1528. advancedata(Movedata *d, long v)
  1529. {
  1530. lesetl(d->pa, legetl(d->pa) + v);
  1531. lesetl(d->dbc, legetl(d->dbc) - v);
  1532. }
  1533. static void
  1534. dumpwritedata(uchar *data, int datalen)
  1535. {
  1536. int i;
  1537. uchar *bp;
  1538. if (!DEBUG(0)){
  1539. USED(data, datalen);
  1540. return;
  1541. }
  1542. if (datalen) {
  1543. KPRINT(PRINTPREFIX "write:");
  1544. for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
  1545. KPRINT("%.2ux", *bp);
  1546. }
  1547. if (i < datalen) {
  1548. KPRINT("...");
  1549. }
  1550. KPRINT("\n");
  1551. }
  1552. }
  1553. static void
  1554. dumpreaddata(uchar *data, int datalen)
  1555. {
  1556. int i;
  1557. uchar *bp;
  1558. if (!DEBUG(0)){
  1559. USED(data, datalen);
  1560. return;
  1561. }
  1562. if (datalen) {
  1563. KPRINT(PRINTPREFIX "read:");
  1564. for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
  1565. KPRINT("%.2ux", *bp);
  1566. }
  1567. if (i < datalen) {
  1568. KPRINT("...");
  1569. }
  1570. KPRINT("\n");
  1571. }
  1572. }
  1573. static void
  1574. busreset(Controller *c)
  1575. {
  1576. int x, ntarget;
  1577. /* bus reset */
  1578. c->n->scntl1 |= (1 << 3);
  1579. delay(500);
  1580. c->n->scntl1 &= ~(1 << 3);
  1581. if(!(c->v->feature & Wide))
  1582. ntarget = 8;
  1583. else
  1584. ntarget = MAXTARGET;
  1585. for (x = 0; x < ntarget; x++) {
  1586. setwide(0, c, x, 0);
  1587. #ifndef ASYNC_ONLY
  1588. c->s[x] = NeitherDone;
  1589. #endif
  1590. }
  1591. c->capvalid = 0;
  1592. }
  1593. static void
  1594. reset(Controller *c)
  1595. {
  1596. /* should wakeup all pending tasks */
  1597. softreset(c);
  1598. busreset(c);
  1599. }
  1600. static int
  1601. sd53c8xxrio(SDreq* r)
  1602. {
  1603. Dsa *d;
  1604. uchar *bp;
  1605. Controller *c;
  1606. uchar target_expo, my_expo;
  1607. int bc, check, i, status, target;
  1608. if((target = r->unit->subno) == 0x07)
  1609. return r->status = SDtimeout; /* assign */
  1610. c = r->unit->dev->ctlr;
  1611. check = 0;
  1612. d = dsaalloc(c, target, r->lun);
  1613. qlock(&c->q[target]); /* obtain access to target */
  1614. docheck:
  1615. /* load the transfer control stuff */
  1616. d->scsi_id_buf[0] = 0;
  1617. d->scsi_id_buf[1] = c->sxfer[target];
  1618. d->scsi_id_buf[2] = target;
  1619. d->scsi_id_buf[3] = c->scntl3[target];
  1620. synctodsa(d, c);
  1621. bc = 0;
  1622. d->msg_out[bc] = 0x80 | r->lun;
  1623. #ifndef NO_DISCONNECT
  1624. d->msg_out[bc] |= (1 << 6);
  1625. #endif
  1626. bc++;
  1627. /* work out what to do about negotiation */
  1628. switch (c->s[target]) {
  1629. default:
  1630. KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
  1631. c->s[target] = NeitherDone;
  1632. /* fall through */
  1633. case NeitherDone:
  1634. if ((c->capvalid & (1 << target)) == 0)
  1635. break;
  1636. target_expo = (c->cap[target] >> 5) & 3;
  1637. my_expo = (c->v->feature & Wide) != 0;
  1638. if (target_expo < my_expo)
  1639. my_expo = target_expo;
  1640. #ifdef ALWAYS_DO_WDTR
  1641. bc += buildwdtrmsg(d->msg_out + bc, my_expo);
  1642. KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
  1643. c->s[target] = WideInit;
  1644. break;
  1645. #else
  1646. if (my_expo) {
  1647. bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
  1648. KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
  1649. c->s[target] = WideInit;
  1650. break;
  1651. }
  1652. KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
  1653. /* fall through */
  1654. #endif
  1655. case WideDone:
  1656. if (c->cap[target] & (1 << 4)) {
  1657. KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
  1658. bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
  1659. c->s[target] = SyncInit;
  1660. break;
  1661. }
  1662. KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
  1663. c->s[target] = BothDone;
  1664. break;
  1665. case BothDone:
  1666. break;
  1667. }
  1668. setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
  1669. setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
  1670. calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
  1671. if (DEBUG(0)) {
  1672. KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
  1673. for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
  1674. KPRINT("%.2ux", *bp);
  1675. }
  1676. KPRINT("\n");
  1677. if (!r->write) {
  1678. KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
  1679. target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
  1680. }
  1681. else
  1682. dumpwritedata(r->data, r->dlen);
  1683. }
  1684. setmovedata(&d->status_buf, DMASEG(&d->status), 1);
  1685. d->p9status = SDnostatus;
  1686. d->parityerror = 0;
  1687. coherence();
  1688. d->stateb = A_STATE_ISSUE; /* start operation */
  1689. coherence();
  1690. ilock(c);
  1691. if (c->ssm)
  1692. c->n->dcntl |= 0x10; /* single step */
  1693. if (c->running) {
  1694. c->n->istat = Sigp;
  1695. }
  1696. else {
  1697. start(c, E_issue_check);
  1698. }
  1699. iunlock(c);
  1700. while(waserror())
  1701. ;
  1702. tsleep(d, done, d, 600 * 1000);
  1703. poperror();
  1704. if (!done(d)) {
  1705. KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
  1706. dumpncrregs(c, 0);
  1707. dsafree(c, d);
  1708. reset(c);
  1709. qunlock(&c->q[target]);
  1710. r->status = SDtimeout;
  1711. return r->status = SDtimeout; /* assign */
  1712. }
  1713. if((status = d->p9status) == SDeio)
  1714. c->s[target] = NeitherDone;
  1715. if (d->parityerror) {
  1716. status = SDeio;
  1717. }
  1718. /*
  1719. * adjust datalen
  1720. */
  1721. r->rlen = r->dlen;
  1722. if (DEBUG(0)) {
  1723. KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
  1724. target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
  1725. }
  1726. r->rlen = r->dlen;
  1727. if (d->flag != 2) {
  1728. r->rlen -= d->dmablks * A_BSIZE;
  1729. r->rlen -= legetl(d->data_buf.dbc);
  1730. }
  1731. if(!r->write)
  1732. dumpreaddata(r->data, r->rlen);
  1733. if (DEBUG(0)) {
  1734. KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
  1735. target, r->lun, d->p9status, status, r->rlen);
  1736. }
  1737. /*
  1738. * spot the identify
  1739. */
  1740. if ((c->capvalid & (1 << target)) == 0
  1741. && (status == SDok || status == SDcheck)
  1742. && r->cmd[0] == 0x12 && r->dlen >= 8) {
  1743. c->capvalid |= 1 << target;
  1744. bp = r->data;
  1745. c->cap[target] = bp[7];
  1746. KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
  1747. }
  1748. if(!check && status == SDcheck && !(r->flags & SDnosense)){
  1749. check = 1;
  1750. r->write = 0;
  1751. memset(r->cmd, 0, sizeof(r->cmd));
  1752. r->cmd[0] = 0x03;
  1753. r->cmd[1] = r->lun<<5;
  1754. r->cmd[4] = sizeof(r->sense)-1;
  1755. r->clen = 6;
  1756. r->data = r->sense;
  1757. r->dlen = sizeof(r->sense)-1;
  1758. /*
  1759. * Clear out the microcode state
  1760. * so the Dsa can be re-used.
  1761. */
  1762. lesetl(&d->stateb, A_STATE_ALLOCATED);
  1763. coherence();
  1764. goto docheck;
  1765. }
  1766. qunlock(&c->q[target]);
  1767. dsafree(c, d);
  1768. if(status == SDok && check){
  1769. status = SDcheck;
  1770. r->flags |= SDvalidsense;
  1771. }
  1772. if(DEBUG(0))
  1773. KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
  1774. target, r->flags, status, r->rlen);
  1775. if(r->flags & SDvalidsense){
  1776. if(!DEBUG(0))
  1777. KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
  1778. target, r->flags, status, r->rlen);
  1779. for(i = 0; i < r->rlen; i++)
  1780. KPRINT(" %2.2uX", r->sense[i]);
  1781. KPRINT("\n");
  1782. }
  1783. return r->status = status;
  1784. }
  1785. static void
  1786. cribbios(Controller *c)
  1787. {
  1788. c->bios.scntl3 = c->n->scntl3;
  1789. c->bios.stest2 = c->n->stest2;
  1790. print(PRINTPREFIX "%s: bios scntl3(%.2x) stest2(%.2x)\n",
  1791. c->sdev->name, c->bios.scntl3, c->bios.stest2);
  1792. }
  1793. static int
  1794. bios_set_differential(Controller *c)
  1795. {
  1796. /* Concept lifted from FreeBSD - thanks Gerard */
  1797. /* basically, if clock conversion factors are set, then there is
  1798. * evidence the bios had a go at the chip, and if so, it would
  1799. * have set the differential enable bit in stest2
  1800. */
  1801. return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
  1802. }
  1803. #define NCR_VID 0x1000
  1804. #define NCR_810_DID 0x0001
  1805. #define NCR_820_DID 0x0002 /* don't know enough about this one to support it */
  1806. #define NCR_825_DID 0x0003
  1807. #define NCR_815_DID 0x0004
  1808. #define SYM_810AP_DID 0x0005
  1809. #define SYM_860_DID 0x0006
  1810. #define SYM_896_DID 0x000b
  1811. #define SYM_895_DID 0x000c
  1812. #define SYM_885_DID 0x000d /* ditto */
  1813. #define SYM_875_DID 0x000f /* ditto */
  1814. #define SYM_1010_DID 0x0020
  1815. #define SYM_1011_DID 0x0021
  1816. #define SYM_875J_DID 0x008f
  1817. static Variant variant[] = {
  1818. { NCR_810_DID, 0x0f, "NCR53C810", Burst16, 8, 24, 0 },
  1819. { NCR_810_DID, 0x1f, "SYM53C810ALV", Burst16, 8, 24, Prefetch },
  1820. { NCR_810_DID, 0xff, "SYM53C810A", Burst16, 8, 24, Prefetch },
  1821. { SYM_810AP_DID, 0xff, "SYM53C810AP", Burst16, 8, 24, Prefetch },
  1822. { NCR_815_DID, 0xff, "NCR53C815", Burst16, 8, 24, BurstOpCodeFetch },
  1823. { NCR_825_DID, 0x0f, "NCR53C825", Burst16, 8, 24, Wide|BurstOpCodeFetch|Differential },
  1824. { NCR_825_DID, 0xff, "SYM53C825A", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
  1825. { SYM_860_DID, 0x0f, "SYM53C860", Burst16, 8, 24, Prefetch|Ultra },
  1826. { SYM_860_DID, 0xff, "SYM53C860LV", Burst16, 8, 24, Prefetch|Ultra },
  1827. { SYM_875_DID, 0x01, "SYM53C875r1", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
  1828. { SYM_875_DID, 0xff, "SYM53C875", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
  1829. { SYM_875J_DID, 0xff, "SYM53C875j", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
  1830. { SYM_885_DID, 0xff, "SYM53C885", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
  1831. { SYM_895_DID, 0xff, "SYM53C895", Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1832. { SYM_896_DID, 0xff, "SYM53C896", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1833. { SYM_1010_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1834. { SYM_1011_DID, 0xff, "SYM53C1010", Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
  1835. };
  1836. static int
  1837. xfunc(Controller *c, enum na_external x, unsigned long *v)
  1838. {
  1839. switch (x) {
  1840. default:
  1841. print("xfunc: can't find external %d\n", x);
  1842. return 0;
  1843. case X_scsi_id_buf:
  1844. *v = offsetof(Dsa, scsi_id_buf[0]);
  1845. break;
  1846. case X_msg_out_buf:
  1847. *v = offsetof(Dsa, msg_out_buf);
  1848. break;
  1849. case X_cmd_buf:
  1850. *v = offsetof(Dsa, cmd_buf);
  1851. break;
  1852. case X_data_buf:
  1853. *v = offsetof(Dsa, data_buf);
  1854. break;
  1855. case X_status_buf:
  1856. *v = offsetof(Dsa, status_buf);
  1857. break;
  1858. case X_dsa_head:
  1859. *v = DMASEG(&c->dsalist.head[0]);
  1860. break;
  1861. case X_ssid_mask:
  1862. *v = SSIDMASK(c);
  1863. break;
  1864. }
  1865. return 1;
  1866. }
  1867. static int
  1868. na_fixup(Controller *c, ulong pa_reg,
  1869. struct na_patch *patch, int patches,
  1870. int (*externval)(Controller*, int, ulong*))
  1871. {
  1872. int p;
  1873. int v;
  1874. ulong *script, pa_script;
  1875. unsigned long lw, lv;
  1876. script = c->script;
  1877. pa_script = c->scriptpa;
  1878. for (p = 0; p < patches; p++) {
  1879. switch (patch[p].type) {
  1880. case 1:
  1881. /* script relative */
  1882. script[patch[p].lwoff] += pa_script;
  1883. break;
  1884. case 2:
  1885. /* register i/o relative */
  1886. script[patch[p].lwoff] += pa_reg;
  1887. break;
  1888. case 3:
  1889. /* data external */
  1890. lw = script[patch[p].lwoff];
  1891. v = (lw >> 8) & 0xff;
  1892. if (!(*externval)(c, v, &lv))
  1893. return 0;
  1894. v = lv & 0xff;
  1895. script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
  1896. break;
  1897. case 4:
  1898. /* 32 bit external */
  1899. lw = script[patch[p].lwoff];
  1900. if (!(*externval)(c, lw, &lv))
  1901. return 0;
  1902. script[patch[p].lwoff] = lv;
  1903. break;
  1904. case 5:
  1905. /* 24 bit external */
  1906. lw = script[patch[p].lwoff];
  1907. if (!(*externval)(c, lw & 0xffffff, &lv))
  1908. return 0;
  1909. script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
  1910. break;
  1911. }
  1912. }
  1913. return 1;
  1914. }
  1915. static SDev*
  1916. sd53c8xxpnp(void)
  1917. {
  1918. char *cp;
  1919. Pcidev *p;
  1920. Variant *v;
  1921. int ba, nctlr;
  1922. void *scriptma;
  1923. Controller *ctlr;
  1924. SDev *sdev, *head, *tail;
  1925. ulong regpa, *script, scriptpa;
  1926. void *regva, *scriptva;
  1927. if(cp = getconf("*maxsd53c8xx"))
  1928. nctlr = strtoul(cp, 0, 0);
  1929. else
  1930. nctlr = 32;
  1931. p = nil;
  1932. head = tail = nil;
  1933. while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
  1934. for(v = variant; v < &variant[nelem(variant)]; v++){
  1935. if(p->did == v->did && p->rid <= v->maxrid)
  1936. break;
  1937. }
  1938. if(v >= &variant[nelem(variant)]) {
  1939. print("no match\n");
  1940. continue;
  1941. }
  1942. print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
  1943. v->name, p->rid, p->intl, p->pcr);
  1944. regpa = p->mem[1].bar;
  1945. ba = 2;
  1946. if(regpa & 0x04){
  1947. if(p->mem[2].bar)
  1948. continue;
  1949. ba++;
  1950. }
  1951. if(regpa == 0)
  1952. print("regpa 0\n");
  1953. regpa &= ~0xF;
  1954. regva = vmap(regpa, p->mem[1].size);
  1955. if(regva == 0)
  1956. continue;
  1957. script = nil;
  1958. scriptpa = 0;
  1959. scriptva = nil;
  1960. scriptma = nil;
  1961. if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
  1962. scriptpa = p->mem[ba].bar;
  1963. if((scriptpa & 0x04) && p->mem[ba+1].bar){
  1964. vunmap(regva, p->mem[1].size);
  1965. continue;
  1966. }
  1967. scriptpa &= ~0x0F;
  1968. scriptva = vmap(scriptpa, p->mem[ba].size);
  1969. if(scriptva)
  1970. script = scriptva;
  1971. }
  1972. if(scriptpa == 0){
  1973. /*
  1974. * Either the map failed, or this chip does not have
  1975. * local RAM. It will need a copy of the microcode.
  1976. */
  1977. scriptma = malloc(sizeof(na_script));
  1978. if(scriptma == nil){
  1979. vunmap(regva, p->mem[1].size);
  1980. continue;
  1981. }
  1982. scriptpa = DMASEG(scriptma);
  1983. script = scriptma;
  1984. }
  1985. ctlr = malloc(sizeof(Controller));
  1986. sdev = malloc(sizeof(SDev));
  1987. if(ctlr == nil || sdev == nil){
  1988. buggery:
  1989. if(ctlr)
  1990. free(ctlr);
  1991. if(sdev)
  1992. free(sdev);
  1993. if(scriptma)
  1994. free(scriptma);
  1995. else if(scriptva)
  1996. vunmap(scriptva, p->mem[ba].size);
  1997. if(regva)
  1998. vunmap(regva, p->mem[1].size);
  1999. continue;
  2000. }
  2001. if(dsaend == nil)
  2002. dsaend = xalloc(sizeof *dsaend);
  2003. if(dsaend == nil)
  2004. panic("sd53c8xxpnp: no memory");
  2005. lesetl(&dsaend->stateb, A_STATE_END);
  2006. // lesetl(dsaend->next, DMASEG(dsaend));
  2007. coherence();
  2008. lesetl(ctlr->dsalist.head, DMASEG(dsaend));
  2009. coherence();
  2010. ctlr->dsalist.freechain = 0;
  2011. ctlr->n = regva;
  2012. ctlr->v = v;
  2013. ctlr->script = script;
  2014. memmove(ctlr->script, na_script, sizeof(na_script));
  2015. /*
  2016. * Because we don't yet have an abstraction for the
  2017. * addresses as seen from the controller side (and on
  2018. * the 386 it doesn't matter), the following two lines
  2019. * are different between the 386 and alpha copies of
  2020. * this driver.
  2021. */
  2022. ctlr->scriptpa = scriptpa;
  2023. if(!na_fixup(ctlr, regpa, na_patches, NA_PATCHES, xfunc)){
  2024. print("script fixup failed\n");
  2025. goto buggery;
  2026. }
  2027. swabl(ctlr->script, ctlr->script, sizeof(na_script));
  2028. ctlr->pcidev = p;
  2029. sdev->ifc = &sd53c8xxifc;
  2030. sdev->ctlr = ctlr;
  2031. sdev->idno = '0';
  2032. if(!(v->feature & Wide))
  2033. sdev->nunit = 8;
  2034. else
  2035. sdev->nunit = MAXTARGET;
  2036. ctlr->sdev = sdev;
  2037. if(head != nil)
  2038. tail->next = sdev;
  2039. else
  2040. head = sdev;
  2041. tail = sdev;
  2042. nctlr--;
  2043. }
  2044. return head;
  2045. }
  2046. static int
  2047. sd53c8xxenable(SDev* sdev)
  2048. {
  2049. Pcidev *pcidev;
  2050. Controller *ctlr;
  2051. char name[32];
  2052. ctlr = sdev->ctlr;
  2053. pcidev = ctlr->pcidev;
  2054. pcisetbme(pcidev);
  2055. ilock(ctlr);
  2056. synctabinit(ctlr);
  2057. cribbios(ctlr);
  2058. reset(ctlr);
  2059. snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
  2060. intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
  2061. iunlock(ctlr);
  2062. return 1;
  2063. }
  2064. SDifc sd53c8xxifc = {
  2065. "53c8xx", /* name */
  2066. sd53c8xxpnp, /* pnp */
  2067. nil, /* legacy */
  2068. sd53c8xxenable, /* enable */
  2069. nil, /* disable */
  2070. scsiverify, /* verify */
  2071. scsionline, /* online */
  2072. sd53c8xxrio, /* rio */
  2073. nil, /* rctl */
  2074. nil, /* wctl */
  2075. scsibio, /* bio */
  2076. nil, /* probe */
  2077. nil, /* clear */
  2078. nil, /* rtopctl */
  2079. nil, /* wtopctl */
  2080. };