sdiahci.c 38 KB

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  1. /*
  2. * intel/amd ahci sata controller
  3. * copyright © 2007-8 coraid, inc.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #include "../port/sd.h"
  13. #include "ahci.h"
  14. #define dprint(...) if(debug) iprint(__VA_ARGS__); else USED(debug)
  15. #define idprint(...) if(prid) iprint(__VA_ARGS__); else USED(prid)
  16. #define aprint(...) if(datapi) iprint(__VA_ARGS__); else USED(datapi)
  17. #define Tname(c) tname[(c)->type]
  18. enum {
  19. NCtlr = 4,
  20. NCtlrdrv= 32,
  21. NDrive = NCtlr*NCtlrdrv,
  22. Read = 0,
  23. Write,
  24. };
  25. /* pci space configuration */
  26. enum {
  27. Pmap = 0x90,
  28. Ppcs = 0x91,
  29. Prev = 0xa8,
  30. };
  31. enum {
  32. Tesb,
  33. Tich,
  34. Tsb600,
  35. Tunk,
  36. };
  37. #define Intel(x) ((x)->pci->vid == 0x8086)
  38. static char *tname[] = {
  39. "63xxesb",
  40. "ich",
  41. "sb600",
  42. "unk",
  43. };
  44. enum {
  45. Dnull,
  46. Dmissing,
  47. Dnew,
  48. Dready,
  49. Derror,
  50. Dreset,
  51. Doffline,
  52. Dportreset,
  53. Dlast,
  54. };
  55. static char *diskstates[Dlast] = {
  56. "null",
  57. "missing",
  58. "new",
  59. "ready",
  60. "error",
  61. "reset",
  62. "offline",
  63. "portreset",
  64. };
  65. extern SDifc sdiahciifc;
  66. typedef struct Ctlr Ctlr;
  67. enum {
  68. DMautoneg,
  69. DMsatai,
  70. DMsataii,
  71. };
  72. static char *modename[] = {
  73. "auto",
  74. "satai",
  75. "sataii",
  76. };
  77. static char *flagname[] = {
  78. "llba",
  79. "smart",
  80. "power",
  81. "nop",
  82. "atapi",
  83. "atapi16",
  84. };
  85. typedef struct {
  86. Lock;
  87. Ctlr *ctlr;
  88. SDunit *unit;
  89. char name[10];
  90. Aport *port;
  91. Aportm portm;
  92. Aportc portc; /* redundant ptr to port and portm. */
  93. uchar mediachange;
  94. uchar state;
  95. uchar smartrs;
  96. uvlong sectors;
  97. ulong intick;
  98. ulong lastseen;
  99. int wait;
  100. uchar mode; /* DMautoneg, satai or sataii. */
  101. uchar active;
  102. char serial[20+1];
  103. char firmware[8+1];
  104. char model[40+1];
  105. ushort info[0x200];
  106. int driveno; /* ctlr*NCtlrdrv + unit */
  107. /* controller port # != driveno when not all ports are enabled */
  108. int portno;
  109. } Drive;
  110. struct Ctlr {
  111. Lock;
  112. int type;
  113. int enabled;
  114. SDev *sdev;
  115. Pcidev *pci;
  116. uchar *mmio;
  117. ulong *lmmio;
  118. Ahba *hba;
  119. Drive rawdrive[NCtlrdrv];
  120. Drive* drive[NCtlrdrv];
  121. int ndrive;
  122. int mport;
  123. };
  124. static Ctlr iactlr[NCtlr];
  125. static SDev sdevs[NCtlr];
  126. static int niactlr;
  127. static Drive *iadrive[NDrive];
  128. static int niadrive;
  129. /* these are fiddled in iawtopctl() */
  130. static int debug;
  131. static int prid = 1;
  132. static int datapi;
  133. static char stab[] = {
  134. [0] 'i', 'm',
  135. [8] 't', 'c', 'p', 'e',
  136. [16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  137. };
  138. static void
  139. serrstr(ulong r, char *s, char *e)
  140. {
  141. int i;
  142. e -= 3;
  143. for(i = 0; i < nelem(stab) && s < e; i++)
  144. if(r & (1<<i) && stab[i]){
  145. *s++ = stab[i];
  146. if(SerrBad & (1<<i))
  147. *s++ = '*';
  148. }
  149. *s = 0;
  150. }
  151. static char ntab[] = "0123456789abcdef";
  152. static void
  153. preg(uchar *reg, int n)
  154. {
  155. int i;
  156. char buf[25*3+1], *e;
  157. e = buf;
  158. for(i = 0; i < n; i++){
  159. *e++ = ntab[reg[i]>>4];
  160. *e++ = ntab[reg[i]&0xf];
  161. *e++ = ' ';
  162. }
  163. *e++ = '\n';
  164. *e = 0;
  165. dprint(buf);
  166. }
  167. static void
  168. dreg(char *s, Aport *p)
  169. {
  170. dprint("%stask=%lux; cmd=%lux; ci=%lux; is=%lux\n", s, p->task, p->cmd,
  171. p->ci, p->isr);
  172. }
  173. static void
  174. esleep(int ms)
  175. {
  176. if(waserror())
  177. return;
  178. tsleep(&up->sleep, return0, 0, ms);
  179. poperror();
  180. }
  181. typedef struct {
  182. Aport *p;
  183. int i;
  184. }Asleep;
  185. static int
  186. ahciclear(void *v)
  187. {
  188. Asleep *s;
  189. s = v;
  190. return (s->p->ci & s->i) == 0;
  191. }
  192. static void
  193. aesleep(Aportm *m, Asleep *a, int ms)
  194. {
  195. if(waserror())
  196. return;
  197. tsleep(m, ahciclear, a, ms);
  198. poperror();
  199. }
  200. static int
  201. ahciwait(Aportc *c, int ms)
  202. {
  203. Asleep as;
  204. Aport *p;
  205. p = c->p;
  206. p->ci = 1;
  207. as.p = p;
  208. as.i = 1;
  209. aesleep(c->m, &as, ms);
  210. if((p->task&1) == 0 && p->ci == 0)
  211. return 0;
  212. dreg("ahciwait timeout ", c->p);
  213. return -1;
  214. }
  215. static int
  216. nop(Aportc *pc)
  217. {
  218. uchar *c;
  219. Actab *t;
  220. Alist *l;
  221. if((pc->m->feat & Dnop) == 0)
  222. return -1;
  223. t = pc->m->ctab;
  224. c = t->cfis;
  225. memset(c, 0, 0x20);
  226. c[0] = 0x27;
  227. c[1] = 0x80;
  228. c[2] = 0x00;
  229. c[7] = 0xa0; /* obsolete device bits */
  230. l = pc->m->list;
  231. l->flags = Lwrite | 0x5;
  232. l->len = 0;
  233. l->ctab = PCIWADDR(t);
  234. l->ctabhi = 0;
  235. return ahciwait(pc, 3*1000);
  236. }
  237. static int
  238. setfeatures(Aportc *pc, uchar f)
  239. {
  240. uchar *c;
  241. Actab *t;
  242. Alist *l;
  243. t = pc->m->ctab;
  244. c = t->cfis;
  245. memset(c, 0, 0x20);
  246. c[0] = 0x27;
  247. c[1] = 0x80;
  248. c[2] = 0xef;
  249. c[3] = f;
  250. c[7] = 0xa0; /* obsolete device bits */
  251. l = pc->m->list;
  252. l->flags = Lwrite | 0x5;
  253. l->len = 0;
  254. l->ctab = PCIWADDR(t);
  255. l->ctabhi = 0;
  256. return ahciwait(pc, 3*1000);
  257. }
  258. static int
  259. setudmamode(Aportc *pc, uchar f)
  260. {
  261. uchar *c;
  262. Actab *t;
  263. Alist *l;
  264. /* hack */
  265. if((pc->p->sig >> 16) == 0xeb14)
  266. return 0;
  267. t = pc->m->ctab;
  268. c = t->cfis;
  269. memset(c, 0, 0x20);
  270. c[0] = 0x27;
  271. c[1] = 0x80;
  272. c[2] = 0xef;
  273. c[3] = 3; /* set transfer mode */
  274. c[7] = 0xa0; /* obsolete device bits */
  275. c[12] = 0x40 | f; /* sector count */
  276. l = pc->m->list;
  277. l->flags = Lwrite | 0x5;
  278. l->len = 0;
  279. l->ctab = PCIWADDR(t);
  280. l->ctabhi = 0;
  281. return ahciwait(pc, 3*1000);
  282. }
  283. static void
  284. asleep(int ms)
  285. {
  286. if(up == nil)
  287. delay(ms);
  288. else
  289. esleep(ms);
  290. }
  291. static int
  292. ahciportreset(Aportc *c)
  293. {
  294. ulong *cmd, i;
  295. Aport *p;
  296. p = c->p;
  297. cmd = &p->cmd;
  298. *cmd &= ~(Afre|Ast);
  299. for(i = 0; i < 500; i += 25){
  300. if((*cmd&Acr) == 0)
  301. break;
  302. asleep(25);
  303. }
  304. p->sctl = 1|(p->sctl&~7);
  305. delay(1);
  306. p->sctl &= ~7;
  307. return 0;
  308. }
  309. static int
  310. smart(Aportc *pc, int n)
  311. {
  312. uchar *c;
  313. Actab *t;
  314. Alist *l;
  315. if((pc->m->feat&Dsmart) == 0)
  316. return -1;
  317. t = pc->m->ctab;
  318. c = t->cfis;
  319. memset(c, 0, 0x20);
  320. c[0] = 0x27;
  321. c[1] = 0x80;
  322. c[2] = 0xb0;
  323. c[3] = 0xd8 + n; /* able smart */
  324. c[5] = 0x4f;
  325. c[6] = 0xc2;
  326. c[7] = 0xa0;
  327. l = pc->m->list;
  328. l->flags = Lwrite | 0x5;
  329. l->len = 0;
  330. l->ctab = PCIWADDR(t);
  331. l->ctabhi = 0;
  332. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  333. dprint("smart fail %lux\n", pc->p->task);
  334. // preg(pc->m->fis.r, 20);
  335. return -1;
  336. }
  337. if(n)
  338. return 0;
  339. return 1;
  340. }
  341. static int
  342. smartrs(Aportc *pc)
  343. {
  344. uchar *c;
  345. Actab *t;
  346. Alist *l;
  347. t = pc->m->ctab;
  348. c = t->cfis;
  349. memset(c, 0, 0x20);
  350. c[0] = 0x27;
  351. c[1] = 0x80;
  352. c[2] = 0xb0;
  353. c[3] = 0xda; /* return smart status */
  354. c[5] = 0x4f;
  355. c[6] = 0xc2;
  356. c[7] = 0xa0;
  357. l = pc->m->list;
  358. l->flags = Lwrite | 0x5;
  359. l->len = 0;
  360. l->ctab = PCIWADDR(t);
  361. l->ctabhi = 0;
  362. c = pc->m->fis.r;
  363. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  364. dprint("smart fail %lux\n", pc->p->task);
  365. preg(c, 20);
  366. return -1;
  367. }
  368. if(c[5] == 0x4f && c[6] == 0xc2)
  369. return 1;
  370. return 0;
  371. }
  372. static int
  373. ahciflushcache(Aportc *pc)
  374. {
  375. uchar *c, llba;
  376. Actab *t;
  377. Alist *l;
  378. static uchar tab[2] = {0xe7, 0xea};
  379. llba = pc->m->feat&Dllba? 1: 0;
  380. t = pc->m->ctab;
  381. c = t->cfis;
  382. memset(c, 0, 0x20);
  383. c[0] = 0x27;
  384. c[1] = 0x80;
  385. c[2] = tab[llba];
  386. c[7] = 0xa0;
  387. l = pc->m->list;
  388. l->flags = Lwrite | 0x5;
  389. l->len = 0;
  390. l->ctab = PCIWADDR(t);
  391. l->ctabhi = 0;
  392. if(ahciwait(pc, 60000) == -1 || pc->p->task & (1|32)){
  393. dprint("ahciflushcache fail %lux\n", pc->p->task);
  394. // preg( pc->m->fis.r, 20);
  395. return -1;
  396. }
  397. return 0;
  398. }
  399. static ushort
  400. gbit16(void *a)
  401. {
  402. ushort j;
  403. uchar *i;
  404. i = a;
  405. j = i[1] << 8;
  406. j |= i[0];
  407. return j;
  408. }
  409. static ulong
  410. gbit32(void *a)
  411. {
  412. ulong j;
  413. uchar *i;
  414. i = a;
  415. j = i[3] << 24;
  416. j |= i[2] << 16;
  417. j |= i[1] << 8;
  418. j |= i[0];
  419. return j;
  420. }
  421. static uvlong
  422. gbit64(void *a)
  423. {
  424. uchar *i;
  425. i = a;
  426. return (uvlong)gbit32(i+4) << 32 | gbit32(a);
  427. }
  428. static int
  429. ahciidentify0(Aportc *pc, void *id, int atapi)
  430. {
  431. uchar *c;
  432. Actab *t;
  433. Alist *l;
  434. Aprdt *p;
  435. static uchar tab[] = { 0xec, 0xa1, };
  436. t = pc->m->ctab;
  437. c = t->cfis;
  438. memset(c, 0, 0x20);
  439. c[0] = 0x27;
  440. c[1] = 0x80;
  441. c[2] = tab[atapi];
  442. c[7] = 0xa0; /* obsolete device bits */
  443. l = pc->m->list;
  444. l->flags = 1<<16 | 0x5;
  445. l->len = 0;
  446. l->ctab = PCIWADDR(t);
  447. l->ctabhi = 0;
  448. memset(id, 0, 0x100);
  449. p = &t->prdt;
  450. p->dba = PCIWADDR(id);
  451. p->dbahi = 0;
  452. p->count = 1<<31 | (0x200-2) | 1;
  453. return ahciwait(pc, 3*1000);
  454. }
  455. static vlong
  456. ahciidentify(Aportc *pc, ushort *id)
  457. {
  458. int i, sig;
  459. vlong s;
  460. Aportm *m;
  461. m = pc->m;
  462. m->feat = 0;
  463. m->smart = 0;
  464. i = 0;
  465. sig = pc->p->sig >> 16;
  466. if(sig == 0xeb14){
  467. m->feat |= Datapi;
  468. i = 1;
  469. }
  470. if(ahciidentify0(pc, id, i) == -1)
  471. return -1;
  472. i = gbit16(id+83) | gbit16(id+86);
  473. if(i & (1<<10)){
  474. m->feat |= Dllba;
  475. s = gbit64(id+100);
  476. }else
  477. s = gbit32(id+60);
  478. if(m->feat&Datapi){
  479. i = gbit16(id+0);
  480. if(i&1)
  481. m->feat |= Datapi16;
  482. }
  483. i = gbit16(id+83);
  484. if((i>>14) == 1) {
  485. if(i & (1<<3))
  486. m->feat |= Dpower;
  487. i = gbit16(id+82);
  488. if(i & 1)
  489. m->feat |= Dsmart;
  490. if(i & (1<<14))
  491. m->feat |= Dnop;
  492. }
  493. return s;
  494. }
  495. static int
  496. ahciquiet(Aport *a)
  497. {
  498. ulong *p, i;
  499. p = &a->cmd;
  500. *p &= ~Ast;
  501. for(i = 0; i < 500; i += 50){
  502. if((*p & Acr) == 0)
  503. goto stop;
  504. asleep(50);
  505. }
  506. return -1;
  507. stop:
  508. if((a->task & (ASdrq|ASbsy)) == 0){
  509. *p |= Ast;
  510. return 0;
  511. }
  512. *p |= Aclo;
  513. for(i = 0; i < 500; i += 50){
  514. if((*p & Aclo) == 0)
  515. goto stop1;
  516. asleep(50);
  517. }
  518. return -1;
  519. stop1:
  520. /* extra check */
  521. dprint("clo clear %lx\n", a->task);
  522. if(a->task & ASbsy)
  523. return -1;
  524. *p |= Ast;
  525. return 0;
  526. }
  527. static int
  528. ahcicomreset(Aportc *pc)
  529. {
  530. uchar *c;
  531. Actab *t;
  532. Alist *l;
  533. dprint("ahcicomreset\n");
  534. dreg("comreset ", pc->p);
  535. if(ahciquiet(pc->p) == -1){
  536. dprint("ahciquiet fails\n");
  537. return -1;
  538. }
  539. dreg("comreset ", pc->p);
  540. t = pc->m->ctab;
  541. c = t->cfis;
  542. memset(c, 0, 0x20);
  543. c[0] = 0x27;
  544. c[1] = 0x00;
  545. c[7] = 0xa0; /* obsolete device bits */
  546. c[15] = 1<<2; /* srst */
  547. l = pc->m->list;
  548. l->flags = Lclear | Lreset | 0x5;
  549. l->len = 0;
  550. l->ctab = PCIWADDR(t);
  551. l->ctabhi = 0;
  552. if(ahciwait(pc, 500) == -1){
  553. dprint("first command in comreset fails\n");
  554. return -1;
  555. }
  556. microdelay(250);
  557. dreg("comreset ", pc->p);
  558. memset(c, 0, 0x20);
  559. c[0] = 0x27;
  560. c[1] = 0x00;
  561. c[7] = 0xa0; /* obsolete device bits */
  562. l = pc->m->list;
  563. l->flags = Lwrite | 0x5;
  564. l->len = 0;
  565. l->ctab = PCIWADDR(t);
  566. l->ctabhi = 0;
  567. if(ahciwait(pc, 150) == -1){
  568. dprint("second command in comreset fails\n");
  569. return -1;
  570. }
  571. dreg("comreset ", pc->p);
  572. return 0;
  573. }
  574. static int
  575. ahciidle(Aport *port)
  576. {
  577. ulong *p, i, r;
  578. p = &port->cmd;
  579. if((*p & Arun) == 0)
  580. return 0;
  581. *p &= ~Ast;
  582. r = 0;
  583. for(i = 0; i < 500; i += 25){
  584. if((*p & Acr) == 0)
  585. goto stop;
  586. asleep(25);
  587. }
  588. r = -1;
  589. stop:
  590. if((*p & Afre) == 0)
  591. return r;
  592. *p &= ~Afre;
  593. for(i = 0; i < 500; i += 25){
  594. if((*p & Afre) == 0)
  595. return 0;
  596. asleep(25);
  597. }
  598. return -1;
  599. }
  600. /*
  601. * § 6.2.2.1 first part; comreset handled by reset disk.
  602. * - remainder is handled by configdisk.
  603. * - ahcirecover is a quick recovery from a failed command.
  604. */
  605. static int
  606. ahciswreset(Aportc *pc)
  607. {
  608. int i;
  609. i = ahciidle(pc->p);
  610. pc->p->cmd |= Afre;
  611. if(i == -1)
  612. return -1;
  613. if(pc->p->task & (ASdrq|ASbsy))
  614. return -1;
  615. return 0;
  616. }
  617. static int
  618. ahcirecover(Aportc *pc)
  619. {
  620. ahciswreset(pc);
  621. pc->p->cmd |= Ast;
  622. if(setudmamode(pc, 5) == -1)
  623. return -1;
  624. return 0;
  625. }
  626. static void*
  627. malign(int size, int align)
  628. {
  629. void *v;
  630. v = xspanalloc(size, align, 0);
  631. memset(v, 0, size);
  632. return v;
  633. }
  634. static void
  635. setupfis(Afis *f)
  636. {
  637. f->base = malign(0x100, 0x100);
  638. f->d = f->base + 0;
  639. f->p = f->base + 0x20;
  640. f->r = f->base + 0x40;
  641. f->u = f->base + 0x60;
  642. f->devicebits = (ulong*)(f->base + 0x58);
  643. }
  644. static void
  645. ahciwakeup(Aport *p)
  646. {
  647. ushort s;
  648. s = p->sstatus;
  649. if((s & 0xF00) != 0x600)
  650. return;
  651. if((s & 7) != 1){ /* not (device, no phy) */
  652. iprint("ahci: slumbering drive unwakeable %ux\n", s);
  653. return;
  654. }
  655. p->sctl = 3*Aipm | 0*Aspd | Adet;
  656. delay(1);
  657. p->sctl &= ~7;
  658. // iprint("ahci: wake %ux -> %ux\n", s, p->sstatus);
  659. }
  660. static int
  661. ahciconfigdrive(Ahba *h, Aportc *c, int mode)
  662. {
  663. Aportm *m;
  664. Aport *p;
  665. p = c->p;
  666. m = c->m;
  667. if(m->list == 0){
  668. setupfis(&m->fis);
  669. m->list = malign(sizeof *m->list, 1024);
  670. m->ctab = malign(sizeof *m->ctab, 128);
  671. }
  672. if(p->sstatus & 3 && h->cap & Hsss){
  673. /* device connected & staggered spin-up */
  674. dprint("configdrive: spinning up ... [%lux]\n", p->sstatus);
  675. p->cmd |= Apod|Asud;
  676. asleep(1400);
  677. }
  678. p->serror = SerrAll;
  679. p->list = PCIWADDR(m->list);
  680. p->listhi = 0;
  681. p->fis = PCIWADDR(m->fis.base);
  682. p->fishi = 0;
  683. p->cmd |= Afre|Ast;
  684. if((p->sstatus & 0xF0F) == 0x601) /* drive coming up in slumbering? */
  685. ahciwakeup(p);
  686. /* disable power managment sequence from book. */
  687. p->sctl = (3*Aipm) | (mode*Aspd) | 0*Adet;
  688. p->cmd &= ~Aalpe;
  689. p->ie = IEM;
  690. return 0;
  691. }
  692. static int
  693. ahcienable(Ahba *h)
  694. {
  695. h->ghc |= Hie;
  696. return 0;
  697. }
  698. static int
  699. ahcidisable(Ahba *h)
  700. {
  701. h->ghc &= ~Hie;
  702. return 0;
  703. }
  704. static int
  705. countbits(ulong u)
  706. {
  707. int i, n;
  708. n = 0;
  709. for(i = 0; i < 32; i++)
  710. if(u & (1<<i))
  711. n++;
  712. return n;
  713. }
  714. static int
  715. ahciconf(Ctlr *ctlr)
  716. {
  717. Ahba *h;
  718. ulong u;
  719. h = ctlr->hba = (Ahba*)ctlr->mmio;
  720. u = h->cap;
  721. if((u&Hsam) == 0)
  722. h->ghc |= Hae;
  723. print("#S/sd%c: ahci %s port %#p: sss %ld ncs %ld coal %ld "
  724. "mports %ld led %ld clo %ld ems %ld\n",
  725. ctlr->sdev->idno, tname[ctlr->type], h,
  726. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1,
  727. (u>>24) & 1, (u>>6) & 1);
  728. return countbits(h->pi);
  729. }
  730. static int
  731. ahcihbareset(Ahba *h)
  732. {
  733. int wait;
  734. h->ghc |= 1;
  735. for(wait = 0; wait < 1000; wait += 100){
  736. if(h->ghc == 0)
  737. return 0;
  738. delay(100);
  739. }
  740. return -1;
  741. }
  742. static void
  743. idmove(char *p, ushort *a, int n)
  744. {
  745. int i;
  746. char *op, *e;
  747. op = p;
  748. for(i = 0; i < n/2; i++){
  749. *p++ = a[i] >> 8;
  750. *p++ = a[i];
  751. }
  752. *p = 0;
  753. while(p > op && *--p == ' ')
  754. *p = 0;
  755. e = p;
  756. p = op;
  757. while(*p == ' ')
  758. p++;
  759. memmove(op, p, n - (e - p));
  760. }
  761. static int
  762. identify(Drive *d)
  763. {
  764. ushort *id;
  765. vlong osectors, s;
  766. uchar oserial[21];
  767. SDunit *u;
  768. id = d->info;
  769. s = ahciidentify(&d->portc, id);
  770. if(s == -1){
  771. d->state = Derror;
  772. return -1;
  773. }
  774. osectors = d->sectors;
  775. memmove(oserial, d->serial, sizeof d->serial);
  776. d->sectors = s;
  777. d->smartrs = 0;
  778. idmove(d->serial, id+10, 20);
  779. idmove(d->firmware, id+23, 8);
  780. idmove(d->model, id+27, 40);
  781. u = d->unit;
  782. memset(u->inquiry, 0, sizeof u->inquiry);
  783. u->inquiry[2] = 2;
  784. u->inquiry[3] = 2;
  785. u->inquiry[4] = sizeof u->inquiry - 4;
  786. memmove(u->inquiry+8, d->model, 40);
  787. if(osectors != s && memcmp(oserial, d->serial, sizeof oserial) != 0){
  788. d->mediachange = 1;
  789. u->sectors = 0;
  790. }
  791. return 0;
  792. }
  793. static void
  794. clearci(Aport *p)
  795. {
  796. if(p->cmd & Ast) {
  797. p->cmd &= ~Ast;
  798. p->cmd |= Ast;
  799. }
  800. }
  801. static void
  802. updatedrive(Drive *d)
  803. {
  804. ulong cause, serr, s0, pr, ewake;
  805. char *name;
  806. Aport *p;
  807. static ulong last;
  808. pr = 1;
  809. ewake = 0;
  810. p = d->port;
  811. cause = p->isr;
  812. serr = p->serror;
  813. p->isr = cause;
  814. name = "??";
  815. if(d->unit && d->unit->name)
  816. name = d->unit->name;
  817. if(p->ci == 0){
  818. d->portm.flag |= Fdone;
  819. wakeup(&d->portm);
  820. pr = 0;
  821. }else if(cause & Adps)
  822. pr = 0;
  823. if(cause & Ifatal){
  824. ewake = 1;
  825. dprint("Fatal\n");
  826. }
  827. if(cause & Adhrs){
  828. if(p->task & 33){
  829. dprint("Adhrs cause %lux serr %lux task %lux\n",
  830. cause, serr, p->task);
  831. d->portm.flag |= Ferror;
  832. ewake = 1;
  833. }
  834. pr = 0;
  835. }
  836. if(p->task & 1 && last != cause)
  837. dprint("err ca %lux serr %lux task %lux sstat %lux\n",
  838. cause, serr, p->task, p->sstatus);
  839. if(pr)
  840. dprint("%s: upd %lux ta %lux\n", name, cause, p->task);
  841. if(cause & (Aprcs|Aifs)){
  842. s0 = d->state;
  843. switch(p->sstatus & 7){
  844. case 0: /* no device */
  845. d->state = Dmissing;
  846. break;
  847. case 1: /* device but no phy comm. */
  848. if((p->sstatus & 0xF00) == 0x600)
  849. d->state = Dnew; /* slumbering */
  850. else
  851. d->state = Derror;
  852. break;
  853. case 3: /* device & phy comm. estab. */
  854. /* power mgnt crap for suprise removal */
  855. p->ie |= Aprcs|Apcs; /* is this required? */
  856. d->state = Dreset;
  857. break;
  858. case 4: /* phy off-line */
  859. d->state = Doffline;
  860. break;
  861. }
  862. dprint("%s: %s → %s [Apcrs] %lux\n", name, diskstates[s0],
  863. diskstates[d->state], p->sstatus);
  864. /* print pulled message here. */
  865. if(s0 == Dready && d->state != Dready)
  866. idprint("%s: pulled\n", name);
  867. if(d->state != Dready)
  868. d->portm.flag |= Ferror;
  869. ewake = 1;
  870. }
  871. p->serror = serr;
  872. if(ewake){
  873. clearci(p);
  874. wakeup(&d->portm);
  875. }
  876. last = cause;
  877. }
  878. static void
  879. pstatus(Drive *d, ulong s)
  880. {
  881. /*
  882. * bogus code because the first interrupt is currently dropped.
  883. * likely my fault. serror is maybe cleared at the wrong time.
  884. */
  885. switch(s){
  886. case 0: /* no device */
  887. d->state = Dmissing;
  888. break;
  889. case 1: /* device but no phy. comm. */
  890. break;
  891. case 2: /* should this be missing? need testcase. */
  892. dprint("pstatus 2\n");
  893. /* fallthrough */
  894. case 3: /* device & phy. comm. */
  895. d->wait = 0;
  896. d->state = Dnew;
  897. break;
  898. case 4: /* offline */
  899. d->state = Doffline;
  900. break;
  901. case 6: /* ? not sure this makes sense. TODO */
  902. d->state = Dnew;
  903. break;
  904. }
  905. }
  906. static int
  907. configdrive(Drive *d)
  908. {
  909. if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1)
  910. return -1;
  911. ilock(d);
  912. pstatus(d, d->port->sstatus & 7);
  913. iunlock(d);
  914. return 0;
  915. }
  916. static void
  917. resetdisk(Drive *d)
  918. {
  919. uint state, det, stat;
  920. Aport *p;
  921. p = d->port;
  922. det = p->sctl & 7;
  923. stat = p->sstatus & 7;
  924. state = (p->cmd>>28) & 0xf;
  925. dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat);
  926. ilock(d);
  927. state = d->state;
  928. if(d->state != Dready || d->state != Dnew)
  929. d->portm.flag |= Ferror;
  930. clearci(p); /* satisfy sleep condition. */
  931. wakeup(&d->portm);
  932. if(stat != 3){ /* device absent or phy not communicating? */
  933. d->state = Dportreset;
  934. iunlock(d);
  935. return;
  936. }
  937. d->state = Derror;
  938. iunlock(d);
  939. qlock(&d->portm);
  940. if(p->cmd&Ast && ahciswreset(&d->portc) == -1){
  941. ilock(d);
  942. d->state = Dportreset; /* get a bigger stick. */
  943. iunlock(d);
  944. } else {
  945. ilock(d);
  946. d->state = Dmissing;
  947. iunlock(d);
  948. configdrive(d);
  949. }
  950. dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]);
  951. qunlock(&d->portm);
  952. }
  953. static int
  954. newdrive(Drive *d)
  955. {
  956. char *name, *s;
  957. Aportc *c;
  958. Aportm *m;
  959. c = &d->portc;
  960. m = &d->portm;
  961. name = d->unit->name;
  962. if(name == 0)
  963. name = "??";
  964. if(d->port->task == 0x80)
  965. return -1;
  966. qlock(c->m);
  967. if(setudmamode(c, 5) == -1){
  968. dprint("%s: can't set udma mode\n", name);
  969. goto lose;
  970. }
  971. if(identify(d) == -1){
  972. dprint("%s: identify failure\n", name);
  973. goto lose;
  974. }
  975. if(m->feat & Dpower && setfeatures(c, 0x85) == -1){
  976. m->feat &= ~Dpower;
  977. if(ahcirecover(c) == -1)
  978. goto lose;
  979. }
  980. ilock(d);
  981. d->state = Dready;
  982. iunlock(d);
  983. qunlock(c->m);
  984. s = "";
  985. if(m->feat & Dllba)
  986. s = "L";
  987. idprint("%s: %sLBA %,lld sectors\n", d->unit->name, s, d->sectors);
  988. idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial,
  989. d->mediachange? "[mediachange]": "");
  990. return 0;
  991. lose:
  992. idprint("%s: can't be initialized\n", d->unit->name);
  993. ilock(d);
  994. d->state = Dnull;
  995. iunlock(d);
  996. qunlock(c->m);
  997. return -1;
  998. }
  999. enum {
  1000. Nms = 256,
  1001. Mphywait = 2*1024/Nms - 1,
  1002. Midwait = 16*1024/Nms - 1,
  1003. Mcomrwait = 64*1024/Nms - 1,
  1004. };
  1005. static void
  1006. westerndigitalhung(Drive *d)
  1007. {
  1008. if((d->portm.feat&Datapi) == 0 && d->active && TK2MS(d->intick) > 5000){
  1009. dprint("%s: drive hung; resetting [%lux] ci %lx\n",
  1010. d->unit->name, d->port->task, d->port->ci);
  1011. d->state = Dreset;
  1012. }
  1013. }
  1014. static ushort olds[NCtlr*NCtlrdrv];
  1015. static int
  1016. doportreset(Drive *d)
  1017. {
  1018. int i;
  1019. i = -1;
  1020. qlock(&d->portm);
  1021. if(ahciportreset(&d->portc) == -1)
  1022. dprint("ahciportreset fails\n");
  1023. else
  1024. i = 0;
  1025. qunlock(&d->portm);
  1026. dprint("portreset → %s [task %lux]\n",
  1027. diskstates[d->state], d->port->task);
  1028. return i;
  1029. }
  1030. /* drive must be locked */
  1031. static void
  1032. statechange(Drive *d)
  1033. {
  1034. switch(d->state){
  1035. case Dnull:
  1036. case Doffline:
  1037. if(d->unit->sectors != 0){
  1038. d->sectors = 0;
  1039. d->mediachange = 1;
  1040. }
  1041. /* fallthrough */
  1042. case Dready:
  1043. d->wait = 0;
  1044. break;
  1045. }
  1046. }
  1047. static void
  1048. checkdrive(Drive *d, int i)
  1049. {
  1050. ushort s;
  1051. char *name;
  1052. ilock(d);
  1053. name = d->unit->name;
  1054. s = d->port->sstatus;
  1055. if(s)
  1056. d->lastseen = MACHP(0)->ticks;
  1057. if(s != olds[i]){
  1058. dprint("%s: status: %04ux -> %04ux: %s\n",
  1059. name, olds[i], s, diskstates[d->state]);
  1060. olds[i] = s;
  1061. d->wait = 0;
  1062. }
  1063. westerndigitalhung(d);
  1064. switch(d->state){
  1065. case Dnull:
  1066. case Dready:
  1067. break;
  1068. case Dmissing:
  1069. case Dnew:
  1070. switch(s & 0x107){
  1071. case 1: /* no device (pm), device but no phy. comm. */
  1072. ahciwakeup(d->port);
  1073. /* fall through */
  1074. case 0: /* no device */
  1075. break;
  1076. default:
  1077. dprint("%s: unknown status %04ux\n", name, s);
  1078. /* fall through */
  1079. case 0x100: /* active, no device */
  1080. if(++d->wait&Mphywait)
  1081. break;
  1082. reset:
  1083. if(++d->mode > DMsataii)
  1084. d->mode = 0;
  1085. if(d->mode == DMsatai){ /* we tried everything */
  1086. d->state = Dportreset;
  1087. goto portreset;
  1088. }
  1089. dprint("%s: reset; new mode %s\n", name,
  1090. modename[d->mode]);
  1091. iunlock(d);
  1092. resetdisk(d);
  1093. ilock(d);
  1094. break;
  1095. case 0x103: /* active, device, phy. comm. */
  1096. if((++d->wait&Midwait) == 0){
  1097. dprint("%s: slow reset %04ux task=%lux; %d\n",
  1098. name, s, d->port->task, d->wait);
  1099. goto reset;
  1100. }
  1101. s = (uchar)d->port->task;
  1102. if(s == 0x7f || ((d->port->sig >> 16) != 0xeb14 &&
  1103. (s & ~0x17) != (1<<6)))
  1104. break;
  1105. iunlock(d);
  1106. newdrive(d);
  1107. ilock(d);
  1108. break;
  1109. }
  1110. break;
  1111. case Doffline:
  1112. if(d->wait++ & Mcomrwait)
  1113. break;
  1114. /* fallthrough */
  1115. case Derror:
  1116. case Dreset:
  1117. dprint("%s: reset [%s]: mode %d; status %04ux\n",
  1118. name, diskstates[d->state], d->mode, s);
  1119. iunlock(d);
  1120. resetdisk(d);
  1121. ilock(d);
  1122. break;
  1123. case Dportreset:
  1124. portreset:
  1125. if(d->wait++ & 0xff && (s & 0x100) == 0)
  1126. break;
  1127. /* device is active */
  1128. dprint("%s: portreset [%s]: mode %d; status %04ux\n",
  1129. name, diskstates[d->state], d->mode, s);
  1130. d->portm.flag |= Ferror;
  1131. clearci(d->port);
  1132. wakeup(&d->portm);
  1133. if((s & 7) == 0){ /* no device */
  1134. d->state = Dmissing;
  1135. break;
  1136. }
  1137. iunlock(d);
  1138. doportreset(d);
  1139. ilock(d);
  1140. break;
  1141. }
  1142. statechange(d);
  1143. iunlock(d);
  1144. }
  1145. static void
  1146. satakproc(void*)
  1147. {
  1148. int i;
  1149. for(;;){
  1150. tsleep(&up->sleep, return0, 0, Nms);
  1151. for(i = 0; i < niadrive; i++)
  1152. checkdrive(iadrive[i], i);
  1153. }
  1154. }
  1155. static void
  1156. iainterrupt(Ureg*, void *a)
  1157. {
  1158. int i;
  1159. ulong cause, m;
  1160. Ctlr *c;
  1161. Drive *d;
  1162. c = a;
  1163. ilock(c);
  1164. cause = c->hba->isr;
  1165. for(i = 0; i < c->mport; i++){
  1166. m = 1 << i;
  1167. if((cause & m) == 0)
  1168. continue;
  1169. d = c->rawdrive + i;
  1170. ilock(d);
  1171. if(d->port->isr && c->hba->pi & m)
  1172. updatedrive(d);
  1173. c->hba->isr = m;
  1174. iunlock(d);
  1175. }
  1176. iunlock(c);
  1177. }
  1178. static int
  1179. iaverify(SDunit *u)
  1180. {
  1181. Ctlr *c;
  1182. Drive *d;
  1183. c = u->dev->ctlr;
  1184. d = c->drive[u->subno];
  1185. ilock(c);
  1186. ilock(d);
  1187. d->unit = u;
  1188. iunlock(d);
  1189. iunlock(c);
  1190. checkdrive(d, d->driveno); /* c->d0 + d->driveno */
  1191. return 1;
  1192. }
  1193. static int
  1194. iaenable(SDev *s)
  1195. {
  1196. char name[32];
  1197. Ctlr *c;
  1198. static int once;
  1199. c = s->ctlr;
  1200. ilock(c);
  1201. if(!c->enabled) {
  1202. if(once == 0) {
  1203. once = 1;
  1204. kproc("iasata", satakproc, 0);
  1205. }
  1206. if(c->ndrive == 0)
  1207. panic("iaenable: zero s->ctlr->ndrive");
  1208. pcisetbme(c->pci);
  1209. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1210. intrenable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1211. /* supposed to squelch leftover interrupts here. */
  1212. ahcienable(c->hba);
  1213. c->enabled = 1;
  1214. }
  1215. iunlock(c);
  1216. return 1;
  1217. }
  1218. static int
  1219. iadisable(SDev *s)
  1220. {
  1221. char name[32];
  1222. Ctlr *c;
  1223. c = s->ctlr;
  1224. ilock(c);
  1225. ahcidisable(c->hba);
  1226. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1227. intrdisable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1228. c->enabled = 0;
  1229. iunlock(c);
  1230. return 1;
  1231. }
  1232. static int
  1233. iaonline(SDunit *unit)
  1234. {
  1235. int r;
  1236. Ctlr *c;
  1237. Drive *d;
  1238. c = unit->dev->ctlr;
  1239. d = c->drive[unit->subno];
  1240. r = 0;
  1241. if(d->portm.feat & Datapi && d->mediachange){
  1242. r = scsionline(unit);
  1243. if(r > 0)
  1244. d->mediachange = 0;
  1245. return r;
  1246. }
  1247. ilock(d);
  1248. if(d->mediachange){
  1249. r = 2;
  1250. d->mediachange = 0;
  1251. /* devsd resets this after online is called; why? */
  1252. unit->sectors = d->sectors;
  1253. unit->secsize = 512;
  1254. } else if(d->state == Dready)
  1255. r = 1;
  1256. iunlock(d);
  1257. return r;
  1258. }
  1259. /* returns locked list! */
  1260. static Alist*
  1261. ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba)
  1262. {
  1263. uchar *c, acmd, dir, llba;
  1264. Alist *l;
  1265. Actab *t;
  1266. Aprdt *p;
  1267. static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35, };
  1268. dir = *cmd != 0x28;
  1269. llba = m->feat&Dllba? 1: 0;
  1270. acmd = tab[dir][llba];
  1271. qlock(m);
  1272. l = m->list;
  1273. t = m->ctab;
  1274. c = t->cfis;
  1275. c[0] = 0x27;
  1276. c[1] = 0x80;
  1277. c[2] = acmd;
  1278. c[3] = 0;
  1279. c[4] = lba; /* sector lba low 7:0 */
  1280. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1281. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1282. c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */
  1283. if(llba == 0)
  1284. c[7] |= (lba>>24) & 7;
  1285. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1286. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1287. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1288. c[11] = 0; /* features (exp); */
  1289. c[12] = n; /* sector count */
  1290. c[13] = n >> 8; /* sector count (exp) */
  1291. c[14] = 0; /* r */
  1292. c[15] = 0; /* control */
  1293. *(ulong*)(c + 16) = 0;
  1294. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1295. if(dir == Write)
  1296. l->flags |= Lwrite;
  1297. l->len = 0;
  1298. l->ctab = PCIWADDR(t);
  1299. l->ctabhi = 0;
  1300. p = &t->prdt;
  1301. p->dba = PCIWADDR(data);
  1302. p->dbahi = 0;
  1303. p->count = 1<<31 | (512*n - 2) | 1;
  1304. return l;
  1305. }
  1306. static Alist*
  1307. ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n)
  1308. {
  1309. int fill, len;
  1310. uchar *c;
  1311. Alist *l;
  1312. Actab *t;
  1313. Aprdt *p;
  1314. qlock(m);
  1315. l = m->list;
  1316. t = m->ctab;
  1317. c = t->cfis;
  1318. fill = m->feat&Datapi16? 16: 12;
  1319. if((len = r->clen) > fill)
  1320. len = fill;
  1321. memmove(t->atapi, r->cmd, len);
  1322. memset(t->atapi+len, 0, fill-len);
  1323. c[0] = 0x27;
  1324. c[1] = 0x80;
  1325. c[2] = 0xa0;
  1326. if(n != 0)
  1327. c[3] = 1; /* dma */
  1328. else
  1329. c[3] = 0; /* features (exp); */
  1330. c[4] = 0; /* sector lba low 7:0 */
  1331. c[5] = n; /* cylinder low lba mid 15:8 */
  1332. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1333. c[7] = 0xa0; /* obsolete device bits */
  1334. *(ulong*)(c + 8) = 0;
  1335. *(ulong*)(c + 12) = 0;
  1336. *(ulong*)(c + 16) = 0;
  1337. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1338. if(r->write != 0 && data)
  1339. l->flags |= Lwrite;
  1340. l->len = 0;
  1341. l->ctab = PCIWADDR(t);
  1342. l->ctabhi = 0;
  1343. if(data == 0)
  1344. return l;
  1345. p = &t->prdt;
  1346. p->dba = PCIWADDR(data);
  1347. p->dbahi = 0;
  1348. p->count = 1<<31 | (n - 2) | 1;
  1349. return l;
  1350. }
  1351. static int
  1352. waitready(Drive *d)
  1353. {
  1354. ulong s, i, δ;
  1355. for(i = 0; i < 15000; i += 250){
  1356. if(d->state == Dreset || d->state == Dportreset ||
  1357. d->state == Dnew)
  1358. return 1;
  1359. δ = MACHP(0)->ticks - d->lastseen;
  1360. if(d->state == Dnull || δ > 10*1000)
  1361. return -1;
  1362. ilock(d);
  1363. s = d->port->sstatus;
  1364. iunlock(d);
  1365. if((s & 0x700) == 0 && δ > 1500)
  1366. return -1; /* no detect */
  1367. if(d->state == Dready && (s & 7) == 3)
  1368. return 0; /* ready, present & phy. comm. */
  1369. esleep(250);
  1370. }
  1371. print("%s: not responding; offline\n", d->unit->name);
  1372. ilock(d);
  1373. d->state = Doffline;
  1374. iunlock(d);
  1375. return -1;
  1376. }
  1377. static int
  1378. lockready(Drive *d)
  1379. {
  1380. int i;
  1381. qlock(&d->portm);
  1382. while ((i = waitready(d)) == 1) {
  1383. qunlock(&d->portm);
  1384. esleep(1);
  1385. qlock(&d->portm);
  1386. }
  1387. return i;
  1388. }
  1389. static int
  1390. flushcache(Drive *d)
  1391. {
  1392. int i;
  1393. i = -1;
  1394. if(lockready(d) == 0)
  1395. i = ahciflushcache(&d->portc);
  1396. qunlock(&d->portm);
  1397. return i;
  1398. }
  1399. static int
  1400. iariopkt(SDreq *r, Drive *d)
  1401. {
  1402. int n, count, try, max, flag, task;
  1403. char *name;
  1404. uchar *cmd, *data;
  1405. Aport *p;
  1406. Asleep as;
  1407. cmd = r->cmd;
  1408. name = d->unit->name;
  1409. p = d->port;
  1410. aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write],
  1411. r->dlen, r->data);
  1412. if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1413. return sdmodesense(r, cmd, d->info, sizeof d->info);
  1414. r->rlen = 0;
  1415. count = r->dlen;
  1416. max = 65536;
  1417. try = 0;
  1418. retry:
  1419. data = r->data;
  1420. n = count;
  1421. if(n > max)
  1422. n = max;
  1423. ahcibuildpkt(&d->portm, r, data, n);
  1424. switch(waitready(d)){
  1425. case -1:
  1426. qunlock(&d->portm);
  1427. return SDeio;
  1428. case 1:
  1429. qunlock(&d->portm);
  1430. esleep(1);
  1431. goto retry;
  1432. }
  1433. ilock(d);
  1434. d->portm.flag = 0;
  1435. iunlock(d);
  1436. p->ci = 1;
  1437. as.p = p;
  1438. as.i = 1;
  1439. d->intick = MACHP(0)->ticks;
  1440. d->active++;
  1441. while(waserror())
  1442. ;
  1443. sleep(&d->portm, ahciclear, &as);
  1444. poperror();
  1445. d->active--;
  1446. ilock(d);
  1447. flag = d->portm.flag;
  1448. task = d->port->task;
  1449. iunlock(d);
  1450. if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){
  1451. d->port->ci = 0;
  1452. ahcirecover(&d->portc);
  1453. task = d->port->task;
  1454. flag &= ~Fdone; /* either an error or do-over */
  1455. }
  1456. qunlock(&d->portm);
  1457. if(flag == 0){
  1458. if(++try == 10){
  1459. print("%s: bad disk\n", name);
  1460. r->status = SDcheck;
  1461. return SDcheck;
  1462. }
  1463. print("%s: retry\n", name);
  1464. goto retry;
  1465. }
  1466. if(flag & Ferror){
  1467. if((task&Eidnf) == 0)
  1468. print("%s: i/o error %ux\n", name, task);
  1469. r->status = SDcheck;
  1470. return SDcheck;
  1471. }
  1472. data += n;
  1473. r->rlen = data - (uchar*)r->data;
  1474. r->status = SDok;
  1475. return SDok;
  1476. }
  1477. static int
  1478. iario(SDreq *r)
  1479. {
  1480. int i, n, count, try, max, flag, task;
  1481. vlong lba;
  1482. char *name;
  1483. uchar *cmd, *data;
  1484. Aport *p;
  1485. Asleep as;
  1486. Ctlr *c;
  1487. Drive *d;
  1488. SDunit *unit;
  1489. unit = r->unit;
  1490. c = unit->dev->ctlr;
  1491. d = c->drive[unit->subno];
  1492. if(d->portm.feat & Datapi)
  1493. return iariopkt(r, d);
  1494. cmd = r->cmd;
  1495. name = d->unit->name;
  1496. p = d->port;
  1497. if(r->cmd[0] == 0x35 || r->cmd[0] == 0x91){
  1498. if(flushcache(d) == 0)
  1499. return sdsetsense(r, SDok, 0, 0, 0);
  1500. return sdsetsense(r, SDcheck, 3, 0xc, 2);
  1501. }
  1502. if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){
  1503. r->status = i;
  1504. return i;
  1505. }
  1506. if(*cmd != 0x28 && *cmd != 0x2a){
  1507. print("%s: bad cmd 0x%.2ux\n", name, cmd[0]);
  1508. r->status = SDcheck;
  1509. return SDcheck;
  1510. }
  1511. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1512. count = cmd[7]<<8 | cmd[8];
  1513. if(r->data == nil)
  1514. return SDok;
  1515. if(r->dlen < count * unit->secsize)
  1516. count = r->dlen / unit->secsize;
  1517. max = 128;
  1518. try = 0;
  1519. retry:
  1520. data = r->data;
  1521. while(count > 0){
  1522. n = count;
  1523. if(n > max)
  1524. n = max;
  1525. ahcibuild(&d->portm, cmd, data, n, lba);
  1526. switch(waitready(d)){
  1527. case -1:
  1528. qunlock(&d->portm);
  1529. return SDeio;
  1530. case 1:
  1531. qunlock(&d->portm);
  1532. esleep(1);
  1533. goto retry;
  1534. }
  1535. ilock(d);
  1536. d->portm.flag = 0;
  1537. iunlock(d);
  1538. p->ci = 1;
  1539. as.p = p;
  1540. as.i = 1;
  1541. d->intick = MACHP(0)->ticks;
  1542. d->active++;
  1543. while(waserror())
  1544. ;
  1545. sleep(&d->portm, ahciclear, &as);
  1546. poperror();
  1547. d->active--;
  1548. ilock(d);
  1549. flag = d->portm.flag;
  1550. task = d->port->task;
  1551. iunlock(d);
  1552. if(task & (Efatal<<8) ||
  1553. task & (ASbsy|ASdrq) && d->state == Dready){
  1554. d->port->ci = 0;
  1555. ahcirecover(&d->portc);
  1556. task = d->port->task;
  1557. }
  1558. qunlock(&d->portm);
  1559. if(flag == 0){
  1560. if(++try == 10){
  1561. print("%s: bad disk\n", name);
  1562. r->status = SDeio;
  1563. return SDeio;
  1564. }
  1565. iprint("%s: retry %lld\n", name, lba);
  1566. goto retry;
  1567. }
  1568. if(flag & Ferror){
  1569. iprint("%s: i/o error %ux @%,lld\n", name, task, lba);
  1570. r->status = SDeio;
  1571. return SDeio;
  1572. }
  1573. count -= n;
  1574. lba += n;
  1575. data += n * unit->secsize;
  1576. }
  1577. r->rlen = data - (uchar*)r->data;
  1578. r->status = SDok;
  1579. return SDok;
  1580. }
  1581. /*
  1582. * configure drives 0-5 as ahci sata (c.f. errata)
  1583. */
  1584. static int
  1585. iaahcimode(Pcidev *p)
  1586. {
  1587. dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91), pcicfgr8(p, 92),
  1588. pcicfgr8(p, 93));
  1589. pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */
  1590. // pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */
  1591. return 0;
  1592. }
  1593. static void
  1594. iasetupahci(Ctlr *c)
  1595. {
  1596. /* disable cmd block decoding. */
  1597. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1598. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1599. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1600. c->lmmio[0xc/4] = (1 << 6) - 1; /* 5 ports. (supposedly ro pi reg.) */
  1601. /* enable ahci mode; from ich9 datasheet */
  1602. pcicfgw16(c->pci, 0x90, 1<<6 | 1<<5);
  1603. }
  1604. static int
  1605. didtype(Pcidev *p)
  1606. {
  1607. switch(p->vid){
  1608. case 0x8086:
  1609. if((p->did & 0xfffc) == 0x2680)
  1610. return Tesb;
  1611. /* 0x27c4 is the intel 82801 in compatibility (not sata) mode */
  1612. if ((p->did & 0xfeff) == 0x2829 || /* ich8 */
  1613. (p->did & 0xfffe) == 0x2922 || /* ich9 */
  1614. (p->did & 0xfffe) == 0x27c4 /* || p->did == 0x27c0 */) /* 82801g[bh]m? */
  1615. return Tich;
  1616. break;
  1617. case 0x1002:
  1618. if(p->did == 0x4380)
  1619. return Tsb600;
  1620. break;
  1621. }
  1622. if(p->ccrb == Pcibcstore && p->ccru == 6 && p->ccrp == 1)
  1623. return Tunk;
  1624. return -1;
  1625. }
  1626. static SDev*
  1627. iapnp(void)
  1628. {
  1629. int i, n, nunit, type;
  1630. ulong io;
  1631. Ctlr *c;
  1632. Drive *d;
  1633. Pcidev *p;
  1634. SDev *head, *tail, *s;
  1635. static int done;
  1636. if(done++)
  1637. return nil;
  1638. memset(olds, 0xff, sizeof olds);
  1639. p = nil;
  1640. head = tail = nil;
  1641. loop:
  1642. while((p = pcimatch(p, 0, 0)) != nil){
  1643. type = didtype(p);
  1644. if (type == -1 || p->mem[Abar].bar == 0)
  1645. continue;
  1646. if(niactlr == NCtlr){
  1647. print("%spnp: too many controllers\n", tname[type]);
  1648. break;
  1649. }
  1650. c = iactlr + niactlr;
  1651. s = sdevs + niactlr;
  1652. memset(c, 0, sizeof *c);
  1653. memset(s, 0, sizeof *s);
  1654. io = p->mem[Abar].bar & ~0xf;
  1655. c->mmio = vmap(io, p->mem[Abar].size);
  1656. if(c->mmio == 0){
  1657. print("%s: address 0x%luX in use did=%x\n",
  1658. Tname(c), io, p->did);
  1659. continue;
  1660. }
  1661. c->lmmio = (ulong*)c->mmio;
  1662. c->pci = p;
  1663. c->type = type;
  1664. s->ifc = &sdiahciifc;
  1665. s->idno = 'E' + niactlr;
  1666. s->ctlr = c;
  1667. c->sdev = s;
  1668. if(Intel(c) && p->did != 0x2681)
  1669. iasetupahci(c);
  1670. nunit = ahciconf(c);
  1671. // ahcihbareset((Ahba*)c->mmio);
  1672. if(Intel(c) && iaahcimode(p) == -1)
  1673. break;
  1674. if(nunit < 1){
  1675. vunmap(c->mmio, p->mem[Abar].size);
  1676. continue;
  1677. }
  1678. c->ndrive = s->nunit = nunit;
  1679. c->mport = c->hba->cap & ((1<<5)-1);
  1680. i = (c->hba->cap >> 21) & 1;
  1681. print("#S/sd%c: %s: sata-%s with %d ports\n", s->idno,
  1682. Tname(c), "I\0II" + i*2, nunit);
  1683. /* map the drives -- they don't all need to be enabled. */
  1684. memset(c->rawdrive, 0, sizeof c->rawdrive);
  1685. n = 0;
  1686. for(i = 0; i < NCtlrdrv; i++) {
  1687. d = c->rawdrive + i;
  1688. d->portno = i;
  1689. d->driveno = -1;
  1690. d->sectors = 0;
  1691. d->ctlr = c;
  1692. if((c->hba->pi & (1<<i)) == 0)
  1693. continue;
  1694. d->port = (Aport*)(c->mmio + 0x80*i + 0x100);
  1695. d->portc.p = d->port;
  1696. d->portc.m = &d->portm;
  1697. d->driveno = n++;
  1698. c->drive[d->driveno] = d;
  1699. iadrive[niadrive + d->driveno] = d;
  1700. }
  1701. for(i = 0; i < n; i++)
  1702. if(ahciidle(c->drive[i]->port) == -1){
  1703. dprint("%s: port %d wedged; abort\n",
  1704. Tname(c), i);
  1705. goto loop;
  1706. }
  1707. for(i = 0; i < n; i++){
  1708. c->drive[i]->mode = DMsatai;
  1709. configdrive(c->drive[i]);
  1710. }
  1711. niadrive += n;
  1712. niactlr++;
  1713. if(head)
  1714. tail->next = s;
  1715. else
  1716. head = s;
  1717. tail = s;
  1718. }
  1719. return head;
  1720. }
  1721. static char* smarttab[] = {
  1722. "unset",
  1723. "error",
  1724. "threshold exceeded",
  1725. "normal"
  1726. };
  1727. static char *
  1728. pflag(char *s, char *e, uchar f)
  1729. {
  1730. uchar i;
  1731. for(i = 0; i < 8; i++)
  1732. if(f & (1 << i))
  1733. s = seprint(s, e, "%s ", flagname[i]);
  1734. return seprint(s, e, "\n");
  1735. }
  1736. static int
  1737. iarctl(SDunit *u, char *p, int l)
  1738. {
  1739. char buf[32];
  1740. char *e, *op;
  1741. Aport *o;
  1742. Ctlr *c;
  1743. Drive *d;
  1744. if((c = u->dev->ctlr) == nil)
  1745. return 0;
  1746. d = c->drive[u->subno];
  1747. o = d->port;
  1748. e = p+l;
  1749. op = p;
  1750. if(d->state == Dready){
  1751. p = seprint(p, e, "model\t%s\n", d->model);
  1752. p = seprint(p, e, "serial\t%s\n", d->serial);
  1753. p = seprint(p, e, "firm\t%s\n", d->firmware);
  1754. if(d->smartrs == 0xff)
  1755. p = seprint(p, e, "smart\tenable error\n");
  1756. else if(d->smartrs == 0)
  1757. p = seprint(p, e, "smart\tdisabled\n");
  1758. else
  1759. p = seprint(p, e, "smart\t%s\n",
  1760. smarttab[d->portm.smart]);
  1761. p = seprint(p, e, "flag\t");
  1762. p = pflag(p, e, d->portm.feat);
  1763. }else
  1764. p = seprint(p, e, "no disk present [%s]\n", diskstates[d->state]);
  1765. serrstr(o->serror, buf, buf + sizeof buf - 1);
  1766. p = seprint(p, e, "reg\ttask %lux cmd %lux serr %lux %s ci %lux is %lux; "
  1767. "sig %lux sstatus %04lux\n", o->task, o->cmd, o->serror, buf,
  1768. o->ci, o->isr, o->sig, o->sstatus);
  1769. p = seprint(p, e, "geometry %llud 512\n", d->sectors);
  1770. return p - op;
  1771. }
  1772. static void
  1773. runflushcache(Drive *d)
  1774. {
  1775. long t0;
  1776. t0 = MACHP(0)->ticks;
  1777. if(flushcache(d) != 0)
  1778. error(Eio);
  1779. dprint("flush in %ldms\n", MACHP(0)->ticks - t0);
  1780. }
  1781. static void
  1782. forcemode(Drive *d, char *mode)
  1783. {
  1784. int i;
  1785. for(i = 0; i < nelem(modename); i++)
  1786. if(strcmp(mode, modename[i]) == 0)
  1787. break;
  1788. if(i == nelem(modename))
  1789. i = 0;
  1790. ilock(d);
  1791. d->mode = i;
  1792. iunlock(d);
  1793. }
  1794. static void
  1795. runsmartable(Drive *d, int i)
  1796. {
  1797. if(waserror()){
  1798. qunlock(&d->portm);
  1799. d->smartrs = 0;
  1800. nexterror();
  1801. }
  1802. if(lockready(d) == -1)
  1803. error(Eio);
  1804. d->smartrs = smart(&d->portc, i);
  1805. d->portm.smart = 0;
  1806. qunlock(&d->portm);
  1807. poperror();
  1808. }
  1809. static void
  1810. forcestate(Drive *d, char *state)
  1811. {
  1812. int i;
  1813. for(i = 0; i < nelem(diskstates); i++)
  1814. if(strcmp(state, diskstates[i]) == 0)
  1815. break;
  1816. if(i == nelem(diskstates))
  1817. error(Ebadctl);
  1818. ilock(d);
  1819. d->state = i;
  1820. iunlock(d);
  1821. }
  1822. static int
  1823. iawctl(SDunit *u, Cmdbuf *cmd)
  1824. {
  1825. char **f;
  1826. Ctlr *c;
  1827. Drive *d;
  1828. uint i;
  1829. c = u->dev->ctlr;
  1830. d = c->drive[u->subno];
  1831. f = cmd->f;
  1832. if(strcmp(f[0], "flushcache") == 0)
  1833. runflushcache(d);
  1834. else if(strcmp(f[0], "identify") == 0){
  1835. i = strtoul(f[1]? f[1]: "0", 0, 0);
  1836. if(i > 0xff)
  1837. i = 0;
  1838. dprint("%04d %ux\n", i, d->info[i]);
  1839. }else if(strcmp(f[0], "mode") == 0)
  1840. forcemode(d, f[1]? f[1]: "satai");
  1841. else if(strcmp(f[0], "nop") == 0){
  1842. if((d->portm.feat & Dnop) == 0){
  1843. cmderror(cmd, "no drive support");
  1844. return -1;
  1845. }
  1846. if(waserror()){
  1847. qunlock(&d->portm);
  1848. nexterror();
  1849. }
  1850. if(lockready(d) == -1)
  1851. error(Eio);
  1852. nop(&d->portc);
  1853. qunlock(&d->portm);
  1854. poperror();
  1855. }else if(strcmp(f[0], "reset") == 0)
  1856. forcestate(d, "reset");
  1857. else if(strcmp(f[0], "smart") == 0){
  1858. if(d->smartrs == 0){
  1859. cmderror(cmd, "smart not enabled");
  1860. return -1;
  1861. }
  1862. if(waserror()){
  1863. qunlock(&d->portm);
  1864. d->smartrs = 0;
  1865. nexterror();
  1866. }
  1867. if(lockready(d) == -1)
  1868. error(Eio);
  1869. d->portm.smart = 2 + smartrs(&d->portc);
  1870. qunlock(&d->portm);
  1871. poperror();
  1872. }else if(strcmp(f[0], "smartdisable") == 0)
  1873. runsmartable(d, 1);
  1874. else if(strcmp(f[0], "smartenable") == 0)
  1875. runsmartable(d, 0);
  1876. else if(strcmp(f[0], "state") == 0)
  1877. forcestate(d, f[1]? f[1]: "null");
  1878. else{
  1879. cmderror(cmd, Ebadctl);
  1880. return -1;
  1881. }
  1882. return 0;
  1883. }
  1884. static char *
  1885. portr(char *p, char *e, uint x)
  1886. {
  1887. int i, a;
  1888. p[0] = 0;
  1889. a = -1;
  1890. for(i = 0; i < 32; i++){
  1891. if((x & (1<<i)) == 0){
  1892. if(a != -1 && i - 1 != a)
  1893. p = seprint(p, e, "-%d", i - 1);
  1894. a = -1;
  1895. continue;
  1896. }
  1897. if(a == -1){
  1898. if(i > 0)
  1899. p = seprint(p, e, ", ");
  1900. p = seprint(p, e, "%d", a = i);
  1901. }
  1902. }
  1903. if(a != -1 && i - 1 != a)
  1904. p = seprint(p, e, "-%d", i - 1);
  1905. return p;
  1906. }
  1907. /* must emit exactly one line per controller (sd(3)) */
  1908. static char*
  1909. iartopctl(SDev *sdev, char *p, char *e)
  1910. {
  1911. ulong cap;
  1912. char pr[25];
  1913. Ahba *hba;
  1914. Ctlr *ctlr;
  1915. #define has(x, str) if(cap & (x)) p = seprint(p, e, "%s ", (str))
  1916. ctlr = sdev->ctlr;
  1917. hba = ctlr->hba;
  1918. p = seprint(p, e, "sd%c ahci port %#p: ", sdev->idno, hba);
  1919. cap = hba->cap;
  1920. has(Hs64a, "64a");
  1921. has(Hsalp, "alp");
  1922. has(Hsam, "am");
  1923. has(Hsclo, "clo");
  1924. has(Hcccs, "coal");
  1925. has(Hems, "ems");
  1926. has(Hsal, "led");
  1927. has(Hsmps, "mps");
  1928. has(Hsncq, "ncq");
  1929. has(Hssntf, "ntf");
  1930. has(Hspm, "pm");
  1931. has(Hpsc, "pslum");
  1932. has(Hssc, "slum");
  1933. has(Hsss, "ss");
  1934. has(Hsxs, "sxs");
  1935. portr(pr, pr + sizeof pr, hba->pi);
  1936. return seprint(p, e,
  1937. "iss %ld ncs %ld np %ld; ghc %lux isr %lux pi %lux %s ver %lux\n",
  1938. (cap>>20) & 0xf, (cap>>8) & 0x1f, 1 + (cap & 0x1f),
  1939. hba->ghc, hba->isr, hba->pi, pr, hba->ver);
  1940. #undef has
  1941. }
  1942. static int
  1943. iawtopctl(SDev *, Cmdbuf *cmd)
  1944. {
  1945. int *v;
  1946. char **f;
  1947. f = cmd->f;
  1948. v = 0;
  1949. if (f[0] == nil)
  1950. return 0;
  1951. if(strcmp(f[0], "debug") == 0)
  1952. v = &debug;
  1953. else if(strcmp(f[0], "idprint") == 0)
  1954. v = &prid;
  1955. else if(strcmp(f[0], "aprint") == 0)
  1956. v = &datapi;
  1957. else
  1958. cmderror(cmd, Ebadctl);
  1959. switch(cmd->nf){
  1960. default:
  1961. cmderror(cmd, Ebadarg);
  1962. case 1:
  1963. *v ^= 1;
  1964. break;
  1965. case 2:
  1966. if(f[1])
  1967. *v = strcmp(f[1], "on") == 0;
  1968. else
  1969. *v ^= 1;
  1970. break;
  1971. }
  1972. return 0;
  1973. }
  1974. SDifc sdiahciifc = {
  1975. "iahci",
  1976. iapnp,
  1977. nil, /* legacy */
  1978. iaenable,
  1979. iadisable,
  1980. iaverify,
  1981. iaonline,
  1982. iario,
  1983. iarctl,
  1984. iawctl,
  1985. scsibio,
  1986. nil, /* probe */
  1987. nil, /* clear */
  1988. iartopctl,
  1989. iawtopctl,
  1990. };