vgamach64xx.c 27 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "../port/error.h"
  8. #define Image IMAGE
  9. #include <draw.h>
  10. #include <memdraw.h>
  11. #include <cursor.h>
  12. #include "screen.h"
  13. char Eunsupportedformat[] = "unsupported video format";
  14. char Enotconfigured[] = "device not configured";
  15. #define SCALE_ZERO_EXTEND 0x0
  16. #define SCALE_DYNAMIC 0x1
  17. #define SCALE_RED_TEMP_6500K 0x0
  18. #define SCALE_RED_TEMP_9800K 0x2
  19. #define SCALE_HORZ_BLEND 0x0
  20. #define SCALE_HORZ_REP 0x4
  21. #define SCALE_VERT_BLEND 0x0
  22. #define SCALE_VERT_REP 0x8
  23. #define SCALE_BANDWIDTH_NORMAL 0x0
  24. #define SCALE_BANDWIDTH_EXCEEDED 0x4000000
  25. #define SCALE_BANDWIDTH_RESET 0x4000000
  26. #define SCALE_CLK_ACTIVITY 0x0
  27. #define SCALE_CLK_CONTINUOUS 0x20000000
  28. #define OVERLAY_DISABLE 0x0
  29. #define OVERLAY_ENABLE 0x40000000
  30. #define SCALE_DISABLE 0x0
  31. #define SCALE_ENABLE 0x80000000
  32. #define SCALER_FRAME_READ_MODE_FULL 0x0
  33. #define SCALER_BUF_MODE_SINGLE 0x0
  34. #define SCALER_BUF_MODE_DOUBLE 0x40000
  35. #define SCALER_BUF_NEXT_0 0x0
  36. #define SCALER_BUF_NEXT_1 0x80000
  37. #define SCALER_BUF_STATUS_0 0x0
  38. #define SCALER_BUF_STATUS_1 0x100000
  39. #define OVERLAY_MIX_G_CMP 0x0
  40. #define OVERLAY_MIX_ALWAYS_G 0x100
  41. #define OVERLAY_MIX_ALWAYS_V 0x200
  42. #define OVERLAY_MIX_NOT_G 0x300
  43. #define OVERLAY_MIX_NOT_V 0x400
  44. #define OVERLAY_MIX_G_XOR_V 0x500
  45. #define OVERLAY_MIX_NOT_G_XOR_V 0x600
  46. #define OVERLAY_MIX_V_CMP 0x700
  47. #define OVERLAY_MIX_NOT_G_OR_NOT_V 0x800
  48. #define OVERLAY_MIX_G_OR_NOT_V 0x900
  49. #define OVERLAY_MIX_NOT_G_OR_V 0xA00
  50. #define OVERLAY_MIX_G_OR_V 0xB00
  51. #define OVERLAY_MIX_G_AND_V 0xC00
  52. #define OVERLAY_MIX_NOT_G_AND_V 0xD00
  53. #define OVERLAY_MIX_G_AND_NOT_V 0xE00
  54. #define OVERLAY_MIX_NOT_G_AND_NOT_V 0xF00
  55. #define OVERLAY_EXCLUSIVE_NORMAL 0x0
  56. #define OVERLAY_EXCLUSIVE_V_ONLY 0x80000000
  57. #define VIDEO_IN_8BPP 0x2
  58. #define VIDEO_IN_16BPP 0x4
  59. #define VIDEO_IN_32BPP 0x6
  60. #define VIDEO_IN_VYUY422 0xB /*16 bpp */
  61. #define VIDEO_IN_YVYU422 0xC /* 16 bpp */
  62. #define SCALE_IN_15BPP 0x30000 /* aRGB 1555 */
  63. #define SCALE_IN_16BPP 0x40000 /* RGB 565 */
  64. #define SCALE_IN_32BPP 0x60000 /* aRGB 8888 */
  65. #define SCALE_IN_YUV9 0x90000 /* planar */
  66. #define SCALE_IN_YUV12 0xA0000 /* planar */
  67. #define SCALE_IN_VYUY422 0xB0000 /* 16 bpp */
  68. #define SCALE_IN_YVYU422 0xC0000 /* 16 bpp */
  69. #define HOST_YUV_APERTURE_UPPER 0x0
  70. #define HOST_YUV_APERTURE_LOWER 0x20000000
  71. #define HOST_MEM_MODE_Y 0x40000000
  72. #define HOST_MEM_MODE_U 0x80000000
  73. #define HOST_MEM_MODE_V 0xC0000000
  74. #define HOST_MEM_MODE_NORMAL HOST_YUV_APERTURE_UPPER
  75. static Chan *ovl_chan; /* Channel of controlling process */
  76. static int ovl_width; /* Width of input overlay buffer */
  77. static int ovl_height; /* Height of input overlay buffer */
  78. static int ovl_format; /* Overlay format */
  79. static ulong ovl_fib; /* Frame in bytes */
  80. enum {
  81. VTGTB1S1 = 0x01, /* Asic description for VTB1S1 and GTB1S1. */
  82. VT4GTIIC = 0x3A, /* asic descr for VT4 and RAGE IIC */
  83. GTB1U1 = 0x19, /* Asic description for GTB1U1. */
  84. GTB1S2 = 0x41, /* Asic description for GTB1S2. */
  85. GTB2U1 = 0x1A,
  86. GTB2U2 = 0x5A,
  87. GTB2U3 = 0x9A,
  88. GTIIIC1U1 = 0x1B, /* 3D RAGE PRO asic descrp. */
  89. GTIIIC1U2 = 0x5B, /* 3D RAGE PRO asic descrp. */
  90. GTIIIC2U1 = 0x1C, /* 3D RAGE PRO asic descrp. */
  91. GTIIIC2U2 = 0x5C, /* 3D RAGE PRO asic descrp. */
  92. GTIIIC2U3 = 0x7C, /* 3D RAGE PRO asic descrp. */
  93. GTBC = 0x3A, /* 3D RAGE IIC asic descrp. */
  94. LTPRO = 0x9C, /* 3D RAGE LT PRO */
  95. };
  96. /*
  97. * ATI Mach64(CT|ET|G*|V*|L*).
  98. */
  99. typedef struct Mach64types Mach64types;
  100. struct Mach64types {
  101. ushort m64_id; /* Chip ID */
  102. int m64_vtgt; /* Is this a VT or GT chipset? */
  103. ulong m64_ovlclock; /* Max. overlay clock frequency */
  104. int m64_pro; /* Is this a PRO? */
  105. };
  106. static ulong mach64refclock;
  107. static Mach64types *mach64type;
  108. static int mach64revb; /* Revision B or greater? */
  109. static ulong mach64overlay; /* Overlay buffer */
  110. static Mach64types mach64s[] = {
  111. ('C'<<8)|'T', 0, 1350000, /*?*/ 0, /* 4354: CT */
  112. ('E'<<8)|'T', 0, 1350000, /*?*/ 0, /* 4554: ET */
  113. ('G'<<8)|'B', 1, 1250000, 1, /* 4742: 264GT PRO */
  114. ('G'<<8)|'D', 1, 1250000, 1, /* 4744: 264GT PRO */
  115. ('G'<<8)|'I', 1, 1250000, 1, /* 4749: 264GT PRO */
  116. ('G'<<8)|'M', 0, 1350000, 0, /* 474D: Rage XL */
  117. ('G'<<8)|'P', 1, 1250000, 1, /* 4750: 264GT PRO */
  118. ('G'<<8)|'Q', 1, 1250000, 1, /* 4751: 264GT PRO */
  119. ('G'<<8)|'R', 1, 1250000, 1, /* 4752: */
  120. ('G'<<8)|'T', 1, 800000, 0, /* 4754: 264GT[B] */
  121. ('G'<<8)|'U', 1, 1000000, 0, /* 4755: 264GT DVD */
  122. ('G'<<8)|'V', 1, 1000000, 0, /* 4756: Rage2C */
  123. ('G'<<8)|'Z', 1, 1000000, 0, /* 475A: Rage2C */
  124. ('V'<<8)|'T', 1, 800000, 0, /* 5654: 264VT/GT/VTB */
  125. ('V'<<8)|'U', 1, 800000, 0, /* 5655: 264VT3 */
  126. ('V'<<8)|'V', 1, 1000000, 0, /* 5656: 264VT4 */
  127. ('L'<<8)|'B', 0, 1350000, 1, /* 4C42: Rage LTPro AGP */
  128. ('L'<<8)|'I', 0, 1350000, 0, /* 4C49: Rage LTPro AGP */
  129. ('L'<<8)|'M', 0, 1350000, 0, /* 4C4D: Rage Mobility */
  130. ('L'<<8)|'P', 0, 1350000, 1, /* 4C50: 264LT PRO */
  131. };
  132. static int hwfill(VGAscr*, Rectangle, ulong);
  133. static int hwscroll(VGAscr*, Rectangle, Rectangle);
  134. static void initengine(VGAscr*);
  135. static Pcidev*
  136. mach64xxpci(void)
  137. {
  138. Pcidev *p;
  139. int i;
  140. if((p = pcimatch(nil, 0x1002, 0)) == nil)
  141. return nil;
  142. for (i = 0; i != nelem(mach64s); i++)
  143. if (mach64s[i].m64_id == p->did) {
  144. mach64type = &mach64s[i];
  145. return p;
  146. }
  147. return nil;
  148. }
  149. static void
  150. mach64xxenable(VGAscr* scr)
  151. {
  152. Pcidev *p;
  153. if(scr->io)
  154. return;
  155. if(p = mach64xxpci()){
  156. scr->id = p->did;
  157. scr->pci = p;
  158. /*
  159. * The CT doesn't always have the I/O base address
  160. * in the PCI base registers. There is a way to find
  161. * it via the vendor-specific PCI config space but
  162. * this will do for now.
  163. */
  164. scr->io = p->mem[1].bar & ~0x03;
  165. if(scr->io == 0)
  166. scr->io = 0x2EC;
  167. }
  168. }
  169. static void
  170. mach64xxlinear(VGAscr* scr, int size, int)
  171. {
  172. vgalinearpci(scr);
  173. if(scr->paddr == 0)
  174. return;
  175. scr->mmio = (ulong*)((uchar*)scr->vaddr+size-1024);
  176. addvgaseg("mach64mmio", scr->paddr+size-BY2PG, BY2PG);
  177. addvgaseg("mach64screen", scr->paddr, scr->apsize);
  178. }
  179. enum {
  180. CrtcOffPitch = 0x05,
  181. CrtcGenCtl = 0x07,
  182. CurClr0 = 0x0B, /* I/O Select */
  183. CurClr1 = 0x0C,
  184. CurOffset = 0x0D,
  185. CurHVposn = 0x0E,
  186. CurHVoff = 0x0F,
  187. BusCntl = 0x13,
  188. GenTestCntl = 0x19,
  189. CrtcHsyncDis = 0x04,
  190. CrtcVsyncDis = 0x08,
  191. ContextMask = 0x100, /* not accessible via I/O */
  192. FifoStat,
  193. GuiStat,
  194. DpFrgdClr,
  195. DpBkgdClr,
  196. DpWriteMask,
  197. DpMix,
  198. DpPixWidth,
  199. DpSrc,
  200. ClrCmpCntl,
  201. GuiTrajCntl,
  202. ScLeftRight,
  203. ScTopBottom,
  204. DstOffPitch,
  205. DstYX,
  206. DstHeightWidth,
  207. DstCntl,
  208. DstHeight,
  209. DstBresErr,
  210. DstBresInc,
  211. DstBresDec,
  212. SrcCntl,
  213. SrcHeight1Width1,
  214. SrcHeight2Width2,
  215. SrcYX,
  216. SrcWidth1,
  217. SrcYXstart,
  218. HostCntl,
  219. PatReg0,
  220. PatReg1,
  221. PatCntl,
  222. ScBottom,
  223. ScLeft,
  224. ScRight,
  225. ScTop,
  226. ClrCmpClr,
  227. ClrCmpMask,
  228. DpChainMask,
  229. SrcOffPitch,
  230. LcdIndex,
  231. LcdData,
  232. ClockCntl,
  233. OverlayScaleCntl,
  234. ConfigChipId,
  235. Buf0Pitch,
  236. ScalerBuf0Pitch,
  237. CaptureConfig,
  238. OverlayKeyCntl,
  239. ScalerColourCntl,
  240. ScalerHCoef0,
  241. ScalerHCoef1,
  242. ScalerHCoef2,
  243. ScalerHCoef3,
  244. ScalerHCoef4,
  245. VideoFormat,
  246. Buf0Offset,
  247. ScalerBuf0Offset,
  248. CrtcGenCntl,
  249. OverlayScaleInc,
  250. OverlayYX,
  251. OverlayYXEnd,
  252. ScalerHeightWidth,
  253. HTotalDisp,
  254. VTotalDisp,
  255. };
  256. enum {
  257. LCD_ConfigPanel = 0,
  258. LCD_GenCtrl,
  259. LCD_DstnCntl,
  260. LCD_HfbPitchAddr,
  261. LCD_HorzStretch,
  262. LCD_VertStretch,
  263. LCD_ExtVertStretch,
  264. LCD_LtGio,
  265. LCD_PowerMngmnt,
  266. LCD_ZvgPio,
  267. Nlcd,
  268. };
  269. #define Bank1 (-0x100) /* 1KB */
  270. static int mmoffset[] = {
  271. [HTotalDisp] 0x00,
  272. [VTotalDisp] 0x02,
  273. [CrtcOffPitch] 0x05,
  274. [CrtcGenCntl] 0x07,
  275. [CurClr0] 0x18,
  276. [CurClr1] 0x19,
  277. [CurOffset] 0x1A,
  278. [CurHVposn] 0x1B,
  279. [CurHVoff] 0x1C,
  280. [ClockCntl] 0x24,
  281. [BusCntl] 0x28,
  282. [LcdIndex] 0x29,
  283. [LcdData] 0x2A,
  284. [GenTestCntl] 0x34,
  285. [ConfigChipId] 0x38,
  286. [DstOffPitch] 0x40,
  287. [DstYX] 0x43,
  288. [DstHeight] 0x45,
  289. [DstHeightWidth] 0x46,
  290. [DstBresErr] 0x49,
  291. [DstBresInc] 0x4A,
  292. [DstBresDec] 0x4B,
  293. [DstCntl] 0x4C,
  294. [SrcOffPitch] 0x60,
  295. [SrcYX] 0x63,
  296. [SrcWidth1] 0x64,
  297. [SrcYXstart] 0x69,
  298. [SrcHeight1Width1] 0x66,
  299. [SrcHeight2Width2] 0x6C,
  300. [SrcCntl] 0x6D,
  301. [HostCntl] 0x90,
  302. [PatReg0] 0xA0,
  303. [PatReg1] 0xA1,
  304. [PatCntl] 0xA2,
  305. [ScLeft] 0xA8,
  306. [ScRight] 0xA9,
  307. [ScLeftRight] 0xAA,
  308. [ScTop] 0xAB,
  309. [ScBottom] 0xAC,
  310. [ScTopBottom] 0xAD,
  311. [DpBkgdClr] 0xB0,
  312. [DpFrgdClr] 0xB1,
  313. [DpWriteMask] 0xB2,
  314. [DpChainMask] 0xB3,
  315. [DpPixWidth] 0xB4,
  316. [DpMix] 0xB5,
  317. [DpSrc] 0xB6,
  318. [ClrCmpClr] 0xC0,
  319. [ClrCmpMask] 0xC1,
  320. [ClrCmpCntl] 0xC2,
  321. [FifoStat] 0xC4,
  322. [ContextMask] 0xC8,
  323. [GuiTrajCntl] 0xCC,
  324. [GuiStat] 0xCE,
  325. /* Bank1 */
  326. [OverlayYX] Bank1 + 0x00,
  327. [OverlayYXEnd] Bank1 + 0x01,
  328. [OverlayKeyCntl] Bank1 + 0x06,
  329. [OverlayScaleInc] Bank1 + 0x08,
  330. [OverlayScaleCntl] Bank1 + 0x09,
  331. [ScalerHeightWidth] Bank1 + 0x0A,
  332. [ScalerBuf0Offset] Bank1 + 0x0D,
  333. [ScalerBuf0Pitch] Bank1 + 0x0F,
  334. [VideoFormat] Bank1 + 0x12,
  335. [CaptureConfig] Bank1 + 0x14,
  336. [Buf0Offset] Bank1 + 0x20,
  337. [Buf0Pitch] Bank1 + 0x23,
  338. [ScalerColourCntl] Bank1 + 0x54,
  339. [ScalerHCoef0] Bank1 + 0x55,
  340. [ScalerHCoef1] Bank1 + 0x56,
  341. [ScalerHCoef2] Bank1 + 0x57,
  342. [ScalerHCoef3] Bank1 + 0x58,
  343. [ScalerHCoef4] Bank1 + 0x59,
  344. };
  345. static ulong
  346. ior32(VGAscr* scr, int r)
  347. {
  348. if(scr->io == 0x2EC || scr->io == 0x1C8)
  349. return inl((r<<10)+scr->io);
  350. if(r >= 0x100 && scr->mmio != nil)
  351. return scr->mmio[mmoffset[r]];
  352. return inl((mmoffset[r]<<2)+scr->io);
  353. }
  354. static void
  355. iow32(VGAscr* scr, int r, ulong l)
  356. {
  357. if(scr->io == 0x2EC || scr->io == 0x1C8)
  358. outl(((r)<<10)+scr->io, l);
  359. else if(r >= 0x100 && scr->mmio != nil)
  360. scr->mmio[mmoffset[r]] = l;
  361. else
  362. outl((mmoffset[r]<<2)+scr->io, l);
  363. }
  364. static ulong
  365. lcdr32(VGAscr *scr, ulong r)
  366. {
  367. ulong or;
  368. or = ior32(scr, LcdIndex);
  369. iow32(scr, LcdIndex, (or&~0x0F) | (r&0x0F));
  370. return ior32(scr, LcdData);
  371. }
  372. static void
  373. lcdw32(VGAscr *scr, ulong r, ulong v)
  374. {
  375. ulong or;
  376. or = ior32(scr, LcdIndex);
  377. iow32(scr, LcdIndex, (or&~0x0F) | (r&0x0F));
  378. iow32(scr, LcdData, v);
  379. }
  380. static void
  381. mach64xxcurdisable(VGAscr* scr)
  382. {
  383. ulong r;
  384. r = ior32(scr, GenTestCntl);
  385. iow32(scr, GenTestCntl, r & ~0x80);
  386. }
  387. static void
  388. mach64xxcurload(VGAscr* scr, Cursor* curs)
  389. {
  390. uchar *p;
  391. int i, y;
  392. ulong c, s, m, r;
  393. /*
  394. * Disable the cursor.
  395. */
  396. r = ior32(scr, GenTestCntl);
  397. iow32(scr, GenTestCntl, r & ~0x80);
  398. p = scr->vaddr;
  399. p += scr->storage;
  400. /*
  401. * Initialise the 64x64 cursor RAM array.
  402. * The cursor mode gives the following truth table:
  403. * p1 p0 colour
  404. * 0 0 Cursor Colour 0
  405. * 0 1 Cursor Colour 1
  406. * 1 0 Transparent
  407. * 1 1 Complement
  408. * Put the cursor into the top-right of the 64x64 array.
  409. */
  410. for(y = 0; y < 16; y++){
  411. for(i = 0; i < (64-16)/8; i++){
  412. *p++ = 0xAA;
  413. *p++ = 0xAA;
  414. }
  415. c = (curs->clr[2*y]<<8)|curs->clr[y*2 + 1];
  416. s = (curs->set[2*y]<<8)|curs->set[y*2 + 1];
  417. m = 0x00000000;
  418. for(i = 0; i < 16; i++){
  419. if(s & (1<<(15-i)))
  420. m |= 0x01<<(2*i);
  421. else if(c & (1<<(15-i))){
  422. /* nothing to do */
  423. }
  424. else
  425. m |= 0x02<<(2*i);
  426. }
  427. *p++ = m;
  428. *p++ = m>>8;
  429. *p++ = m>>16;
  430. *p++ = m>>24;
  431. }
  432. memset(p, 0xAA, (64-16)*16);
  433. /*
  434. * Set the cursor hotpoint and enable the cursor.
  435. */
  436. scr->offset = curs->offset;
  437. iow32(scr, GenTestCntl, 0x80|r);
  438. }
  439. static int
  440. ptalmostinrect(Point p, Rectangle r)
  441. {
  442. return p.x>=r.min.x && p.x<=r.max.x &&
  443. p.y>=r.min.y && p.y<=r.max.y;
  444. }
  445. /*
  446. * If necessary, translate the rectangle physr
  447. * some multiple of [dx dy] so that it includes p.
  448. * Return 1 if the rectangle changed.
  449. */
  450. static int
  451. screenpan(Point p, Rectangle *physr, int dx, int dy)
  452. {
  453. int d;
  454. if(ptalmostinrect(p, *physr))
  455. return 0;
  456. if(p.y < physr->min.y){
  457. d = physr->min.y - (p.y&~(dy-1));
  458. physr->min.y -= d;
  459. physr->max.y -= d;
  460. }
  461. if(p.y > physr->max.y){
  462. d = ((p.y+dy-1)&~(dy-1)) - physr->max.y;
  463. physr->min.y += d;
  464. physr->max.y += d;
  465. }
  466. if(p.x < physr->min.x){
  467. d = physr->min.x - (p.x&~(dx-1));
  468. physr->min.x -= d;
  469. physr->max.x -= d;
  470. }
  471. if(p.x > physr->max.x){
  472. d = ((p.x+dx-1)&~(dx-1)) - physr->max.x;
  473. physr->min.x += d;
  474. physr->max.x += d;
  475. }
  476. return 1;
  477. }
  478. static int
  479. mach64xxcurmove(VGAscr* scr, Point p)
  480. {
  481. int x, xo, y, yo;
  482. int dx;
  483. ulong off, pitch;
  484. /*
  485. * If the point we want to display is outside the current
  486. * screen rectangle, pan the screen to display it.
  487. *
  488. * We have to move in 64-bit chunks.
  489. */
  490. if(scr->gscreen->depth == 24)
  491. dx = (64*3)/24;
  492. else
  493. dx = 64 / scr->gscreen->depth;
  494. if(panning && screenpan(p, &physgscreenr, dx, 1)){
  495. off = (physgscreenr.min.y*Dx(scr->gscreen->r)+physgscreenr.min.x)/dx;
  496. pitch = Dx(scr->gscreen->r)/8;
  497. iow32(scr, CrtcOffPitch, (pitch<<22)|off);
  498. }
  499. p.x -= physgscreenr.min.x;
  500. p.y -= physgscreenr.min.y;
  501. /*
  502. * Mustn't position the cursor offscreen even partially,
  503. * or it disappears. Therefore, if x or y is -ve, adjust the
  504. * cursor presets instead. If y is negative also have to
  505. * adjust the starting offset.
  506. */
  507. if((x = p.x+scr->offset.x) < 0){
  508. xo = x;
  509. x = 0;
  510. }
  511. else
  512. xo = 0;
  513. if((y = p.y+scr->offset.y) < 0){
  514. yo = y;
  515. y = 0;
  516. }
  517. else
  518. yo = 0;
  519. iow32(scr, CurHVoff, ((64-16-yo)<<16)|(64-16-xo));
  520. iow32(scr, CurOffset, scr->storage/8 + (-yo*2));
  521. iow32(scr, CurHVposn, (y<<16)|x);
  522. return 0;
  523. }
  524. static void
  525. mach64xxcurenable(VGAscr* scr)
  526. {
  527. ulong r, storage;
  528. mach64xxenable(scr);
  529. if(scr->io == 0)
  530. return;
  531. r = ior32(scr, GenTestCntl);
  532. iow32(scr, GenTestCntl, r & ~0x80);
  533. iow32(scr, CurClr0, (Pwhite<<24)|(Pwhite<<16)|(Pwhite<<8)|Pwhite);
  534. iow32(scr, CurClr1, (Pblack<<24)|(Pblack<<16)|(Pblack<<8)|Pblack);
  535. /*
  536. * Find a place for the cursor data in display memory.
  537. * Must be 64-bit aligned.
  538. */
  539. storage = (scr->gscreen->width*BY2WD*scr->gscreen->r.max.y+7)/8;
  540. iow32(scr, CurOffset, storage);
  541. scr->storage = storage*8;
  542. /*
  543. * Cursor goes in the top right corner of the 64x64 array
  544. * so the horizontal and vertical presets are 64-16.
  545. */
  546. iow32(scr, CurHVposn, (0<<16)|0);
  547. iow32(scr, CurHVoff, ((64-16)<<16)|(64-16));
  548. /*
  549. * Load, locate and enable the 64x64 cursor.
  550. */
  551. mach64xxcurload(scr, &arrow);
  552. mach64xxcurmove(scr, ZP);
  553. iow32(scr, GenTestCntl, 0x80|r);
  554. }
  555. static void
  556. waitforfifo(VGAscr *scr, int entries)
  557. {
  558. int x;
  559. x = 0;
  560. while((ior32(scr, FifoStat)&0xFF) > (0x8000>>entries) && x++ < 1000000)
  561. ;
  562. if(x >= 1000000)
  563. iprint("fifo %d stat %#.8lux %#.8lux scrio %#.8lux mmio %#p scr %#p pc %#p\n", entries, ior32(scr, FifoStat), scr->mmio[mmoffset[FifoStat]], scr->io, scr->mmio, scr, getcallerpc(&scr));
  564. }
  565. static void
  566. waitforidle(VGAscr *scr)
  567. {
  568. int x;
  569. waitforfifo(scr, 16);
  570. x = 0;
  571. while((ior32(scr, GuiStat)&1) && x++ < 1000000)
  572. ;
  573. if(x >= 1000000)
  574. iprint("idle stat %#.8lux %#.8lux scrio %#.8lux mmio %#p scr %#p pc %#p\n", ior32(scr, GuiStat), scr->mmio[mmoffset[GuiStat]], scr->io, scr->mmio, scr, getcallerpc(&scr));
  575. }
  576. static void
  577. resetengine(VGAscr *scr)
  578. {
  579. ulong x;
  580. x = ior32(scr, GenTestCntl);
  581. iow32(scr, GenTestCntl, x&~0x100);
  582. iow32(scr, GenTestCntl, x|0x100);
  583. iow32(scr, BusCntl, ior32(scr, BusCntl)|0x00A00000);
  584. }
  585. static void
  586. init_overlayclock(VGAscr *scr)
  587. {
  588. uchar *cc, save, pll_ref_div, pll_vclk_cntl, vclk_post_div,
  589. vclk_fb_div, ecp_div;
  590. int i;
  591. ulong dotclock;
  592. /* Taken from GLX */
  593. /* Get monitor dotclock, check for Overlay Scaler clock limit */
  594. cc = (uchar *)&scr->mmio[mmoffset[ClockCntl]];
  595. save = cc[1]; i = cc[0] & 3;
  596. cc[1] = 2<<2; pll_ref_div = cc[2];
  597. cc[1] = 5<<2; pll_vclk_cntl = cc[2];
  598. cc[1] = 6<<2; vclk_post_div = (cc[2]>>(i+i)) & 3;
  599. cc[1] = (7+i)<<2; vclk_fb_div = cc[2];
  600. dotclock = 2 * mach64refclock * vclk_fb_div /
  601. (pll_ref_div * (1 << vclk_post_div));
  602. /* ecp_div: 0=dotclock, 1=dotclock/2, 2=dotclock/4 */
  603. ecp_div = dotclock / mach64type->m64_ovlclock;
  604. if (ecp_div>2) ecp_div = 2;
  605. /* Force a scaler clock factor of 1 if refclock *
  606. * is unknown (VCLK_SRC not PLLVCLK) */
  607. if ((pll_vclk_cntl & 0x03) != 0x03)
  608. ecp_div = 0;
  609. if ((pll_vclk_cntl & 0x30) != ecp_div<<4) {
  610. cc[1] = (5<<2)|2;
  611. cc[2] = (pll_vclk_cntl&0xCF) | (ecp_div<<4);
  612. }
  613. /* Restore PLL Register Index */
  614. cc[1] = save;
  615. }
  616. static void
  617. initengine(VGAscr *scr)
  618. {
  619. ulong pitch;
  620. uchar *bios;
  621. ushort table;
  622. pitch = Dx(scr->gscreen->r)/8;
  623. if(scr->gscreen->depth == 24)
  624. pitch *= 3;
  625. resetengine(scr);
  626. waitforfifo(scr, 14);
  627. iow32(scr, ContextMask, ~0);
  628. iow32(scr, DstOffPitch, pitch<<22);
  629. iow32(scr, DstYX, 0);
  630. iow32(scr, DstHeight, 0);
  631. iow32(scr, DstBresErr, 0);
  632. iow32(scr, DstBresInc, 0);
  633. iow32(scr, DstBresDec, 0);
  634. iow32(scr, DstCntl, 0x23);
  635. iow32(scr, SrcOffPitch, pitch<<22);
  636. iow32(scr, SrcYX, 0);
  637. iow32(scr, SrcHeight1Width1, 1);
  638. iow32(scr, SrcYXstart, 0);
  639. iow32(scr, SrcHeight2Width2, 1);
  640. iow32(scr, SrcCntl, 0x01);
  641. waitforfifo(scr, 13);
  642. iow32(scr, HostCntl, 0);
  643. iow32(scr, PatReg0, 0);
  644. iow32(scr, PatReg1, 0);
  645. iow32(scr, PatCntl, 0);
  646. iow32(scr, ScLeft, 0);
  647. iow32(scr, ScTop, 0);
  648. iow32(scr, ScBottom, 0xFFFF);
  649. iow32(scr, ScRight, 0xFFFF);
  650. iow32(scr, DpBkgdClr, 0);
  651. iow32(scr, DpFrgdClr, ~0);
  652. iow32(scr, DpWriteMask, ~0);
  653. iow32(scr, DpMix, 0x70003);
  654. iow32(scr, DpSrc, 0x00010100);
  655. waitforfifo(scr, 3);
  656. iow32(scr, ClrCmpClr, 0);
  657. iow32(scr, ClrCmpMask, ~0);
  658. iow32(scr, ClrCmpCntl, 0);
  659. waitforfifo(scr, 2);
  660. switch(scr->gscreen->depth){
  661. case 8:
  662. case 24: /* [sic] */
  663. iow32(scr, DpPixWidth, 0x00020202);
  664. iow32(scr, DpChainMask, 0x8080);
  665. break;
  666. case 16:
  667. iow32(scr, DpPixWidth, 0x00040404);
  668. iow32(scr, DpChainMask, 0x8410);
  669. break;
  670. case 32:
  671. iow32(scr, DpPixWidth, 0x00060606);
  672. iow32(scr, DpChainMask, 0x8080);
  673. break;
  674. }
  675. /* Get the base freq from the BIOS */
  676. bios = kaddr(0xC000);
  677. table = *(ushort *)(bios + 0x48);
  678. table = *(ushort *)(bios + table + 0x10);
  679. switch (*(ushort *)(bios + table + 0x08)) {
  680. case 2700:
  681. mach64refclock = 270000;
  682. break;
  683. case 2863:
  684. case 2864:
  685. mach64refclock = 286363;
  686. break;
  687. case 2950:
  688. mach64refclock = 294989;
  689. break;
  690. case 1432:
  691. default:
  692. mach64refclock = 143181;
  693. break ;
  694. }
  695. /* Figure out which revision this chip is */
  696. switch ((scr->mmio[mmoffset[ConfigChipId]] >> 24) & 0xFF) {
  697. case VTGTB1S1:
  698. case GTB1U1:
  699. case GTB1S2:
  700. case GTB2U1:
  701. case GTB2U2:
  702. case GTB2U3:
  703. case GTBC:
  704. case GTIIIC1U1:
  705. case GTIIIC1U2:
  706. case GTIIIC2U1:
  707. case GTIIIC2U2:
  708. case GTIIIC2U3:
  709. case LTPRO:
  710. mach64revb = 1;
  711. break;
  712. default:
  713. mach64revb = 0;
  714. break;
  715. }
  716. waitforidle(scr);
  717. }
  718. static int
  719. mach64hwfill(VGAscr *scr, Rectangle r, ulong sval)
  720. {
  721. ulong pitch;
  722. ulong ctl;
  723. if(drawdebug)
  724. iprint("hwfill %R val %lux...\n", r, sval);
  725. /* shouldn't happen */
  726. if(scr->io == 0x2EC || scr->io == 0x1C8 || scr->io == 0)
  727. return 0;
  728. pitch = Dx(scr->gscreen->r)/8;
  729. ctl = 1|2; /* left-to-right, top-to-bottom */
  730. if(scr->gscreen->depth == 24){
  731. r.min.x *= 3;
  732. r.max.x *= 3;
  733. pitch *= 3;
  734. ctl |= (1<<7)|(((r.min.x/4)%6)<<8);
  735. }
  736. waitforfifo(scr, 11);
  737. iow32(scr, DpFrgdClr, sval);
  738. iow32(scr, DpWriteMask, 0xFFFFFFFF);
  739. iow32(scr, DpMix, 0x00070003);
  740. iow32(scr, DpSrc, 0x00000111);
  741. iow32(scr, ClrCmpCntl, 0x00000000);
  742. iow32(scr, ScLeftRight, 0x1FFF0000);
  743. iow32(scr, ScTopBottom, 0x1FFF0000);
  744. iow32(scr, DstOffPitch, pitch<<22);
  745. iow32(scr, DstCntl, ctl);
  746. iow32(scr, DstYX, (r.min.x<<16)|r.min.y);
  747. iow32(scr, DstHeightWidth, (Dx(r)<<16)|Dy(r));
  748. waitforidle(scr);
  749. return 1;
  750. }
  751. static int
  752. mach64hwscroll(VGAscr *scr, Rectangle r, Rectangle sr)
  753. {
  754. ulong pitch;
  755. Point dp, sp;
  756. ulong ctl;
  757. int dx, dy;
  758. dx = Dx(r);
  759. dy = Dy(r);
  760. pitch = Dx(scr->gscreen->r)/8;
  761. if(scr->gscreen->depth == 24){
  762. dx *= 3;
  763. pitch *= 3;
  764. r.min.x *= 3;
  765. sr.min.x *= 3;
  766. }
  767. ctl = 0;
  768. if(r.min.x <= sr.min.x){
  769. ctl |= 1;
  770. dp.x = r.min.x;
  771. sp.x = sr.min.x;
  772. }else{
  773. dp.x = r.min.x+dx-1;
  774. sp.x = sr.min.x+dx-1;
  775. }
  776. if(r.min.y <= sr.min.y){
  777. ctl |= 2;
  778. dp.y = r.min.y;
  779. sp.y = sr.min.y;
  780. }else{
  781. dp.y = r.min.y+dy-1;
  782. sp.y = sr.min.y+dy-1;
  783. }
  784. if(scr->gscreen->depth == 24)
  785. ctl |= (1<<7)|(((dp.x/4)%6)<<8);
  786. waitforfifo(scr, 6);
  787. iow32(scr, ScLeftRight, 0x1FFF0000);
  788. iow32(scr, ScTopBottom, 0x1FFF0000);
  789. iow32(scr, DpWriteMask, 0xFFFFFFFF);
  790. iow32(scr, DpMix, 0x00070003);
  791. iow32(scr, DpSrc, 0x00000300);
  792. iow32(scr, ClrCmpCntl, 0x00000000);
  793. waitforfifo(scr, 8);
  794. iow32(scr, SrcOffPitch, pitch<<22);
  795. iow32(scr, SrcCntl, 0x00000000);
  796. iow32(scr, SrcYX, (sp.x<<16)|sp.y);
  797. iow32(scr, SrcWidth1, dx);
  798. iow32(scr, DstOffPitch, pitch<<22);
  799. iow32(scr, DstCntl, ctl);
  800. iow32(scr, DstYX, (dp.x<<16)|dp.y);
  801. iow32(scr, DstHeightWidth, (dx<<16)|dy);
  802. waitforidle(scr);
  803. return 1;
  804. }
  805. /*
  806. * This should work, but doesn't.
  807. * It messes up the screen timings for some reason.
  808. */
  809. static void
  810. mach64blank(VGAscr *scr, int blank)
  811. {
  812. ulong ctl;
  813. ctl = ior32(scr, CrtcGenCtl) & ~(CrtcHsyncDis|CrtcVsyncDis);
  814. if(blank)
  815. ctl |= CrtcHsyncDis|CrtcVsyncDis;
  816. iow32(scr, CrtcGenCtl, ctl);
  817. }
  818. /*
  819. * We squirrel away whether the LCD and/or CRT were
  820. * on when we were called to blank the screen, and
  821. * restore the old state. If we are called to blank the
  822. * screen when it is already blank, we don't update the state.
  823. * Such a call sequence should not happen, though.
  824. *
  825. * We could try forcing the chip into power management
  826. * mode instead, but I'm not sure how that would interact
  827. * with screen updates going on while the screen is blanked.
  828. */
  829. static void
  830. mach64lcdblank(VGAscr *scr, int blank)
  831. {
  832. static int crtlcd;
  833. ulong x;
  834. if(blank) {
  835. x = lcdr32(scr, LCD_GenCtrl);
  836. if(x & 3) {
  837. crtlcd = x & 3;
  838. lcdw32(scr, LCD_GenCtrl, x&~3);
  839. }
  840. } else {
  841. if(crtlcd == 0)
  842. crtlcd = 2; /* lcd only */
  843. x = lcdr32(scr, LCD_GenCtrl);
  844. lcdw32(scr, LCD_GenCtrl, x | crtlcd);
  845. }
  846. }
  847. static void
  848. mach64xxdrawinit(VGAscr *scr)
  849. {
  850. if(scr->io > 0x2FF){
  851. initengine(scr);
  852. scr->fill = mach64hwfill;
  853. scr->scroll = mach64hwscroll;
  854. }
  855. /* scr->blank = mach64blank; */
  856. switch(scr->id){
  857. default:
  858. break;
  859. case ('L'<<8)|'B': /* 4C42: Rage 3D LTPro */
  860. case ('L'<<8)|'I': /* 4C49: Rage 3D LTPro */
  861. case ('L'<<8)|'M': /* 4C4D: Rage Mobility */
  862. case ('L'<<8)|'P': /* 4C50: Rage 3D LTPro */
  863. scr->blank = mach64lcdblank;
  864. hwblank = 1;
  865. break;
  866. }
  867. }
  868. static void
  869. ovl_configure(VGAscr *scr, Chan *c, char **field)
  870. {
  871. int w, h;
  872. char *format;
  873. w = (int)strtol(field[1], nil, 0);
  874. h = (int)strtol(field[2], nil, 0);
  875. format = field[3];
  876. if (c != ovl_chan)
  877. error(Einuse);
  878. if (strcmp(format, "YUYV"))
  879. error(Eunsupportedformat);
  880. ovl_width = w;
  881. ovl_height = h;
  882. ovl_fib = w * h * sizeof(ushort);
  883. waitforidle(scr);
  884. scr->mmio[mmoffset[BusCntl]] |= 0x08000000; /* Enable regblock 1 */
  885. scr->mmio[mmoffset[OverlayScaleCntl]] =
  886. SCALE_ZERO_EXTEND|SCALE_RED_TEMP_6500K|
  887. SCALE_HORZ_BLEND|SCALE_VERT_BLEND;
  888. scr->mmio[mmoffset[!mach64revb? Buf0Pitch: ScalerBuf0Pitch]] = w;
  889. scr->mmio[mmoffset[CaptureConfig]] =
  890. SCALER_FRAME_READ_MODE_FULL|
  891. SCALER_BUF_MODE_SINGLE|
  892. SCALER_BUF_NEXT_0;
  893. scr->mmio[mmoffset[OverlayKeyCntl]] = !mach64revb?
  894. OVERLAY_MIX_ALWAYS_V|(OVERLAY_EXCLUSIVE_NORMAL << 28):
  895. 0x011;
  896. if (mach64type->m64_pro) {
  897. waitforfifo(scr, 6);
  898. /* set the scaler co-efficient registers */
  899. scr->mmio[mmoffset[ScalerColourCntl]] =
  900. (0x00) | (0x10 << 8) | (0x10 << 16);
  901. scr->mmio[mmoffset[ScalerHCoef0]] =
  902. (0x00) | (0x20 << 8);
  903. scr->mmio[mmoffset[ScalerHCoef1]] =
  904. (0x0D) | (0x20 << 8) | (0x06 << 16) | (0x0D << 24);
  905. scr->mmio[mmoffset[ScalerHCoef2]] =
  906. (0x0D) | (0x1C << 8) | (0x0A << 16) | (0x0D << 24);
  907. scr->mmio[mmoffset[ScalerHCoef3]] =
  908. (0x0C) | (0x1A << 8) | (0x0E << 16) | (0x0C << 24);
  909. scr->mmio[mmoffset[ScalerHCoef4]] =
  910. (0x0C) | (0x14 << 8) | (0x14 << 16) | (0x0C << 24);
  911. }
  912. waitforfifo(scr, 3);
  913. scr->mmio[mmoffset[VideoFormat]] = SCALE_IN_YVYU422 |
  914. (!mach64revb? 0xC: 0);
  915. if (mach64overlay == 0)
  916. mach64overlay = scr->storage + 64 * 64 * sizeof(uchar);
  917. scr->mmio[mmoffset[!mach64revb? Buf0Offset: ScalerBuf0Offset]] =
  918. mach64overlay;
  919. }
  920. static void
  921. ovl_enable(VGAscr *scr, Chan *c, char **field)
  922. {
  923. int x, y, w, h;
  924. long h_inc, v_inc;
  925. x = (int)strtol(field[1], nil, 0);
  926. y = (int)strtol(field[2], nil, 0);
  927. w = (int)strtol(field[3], nil, 0);
  928. h = (int)strtol(field[4], nil, 0);
  929. if (x < 0 || x + w > physgscreenr.max.x ||
  930. y < 0 || y + h > physgscreenr.max.y)
  931. error(Ebadarg);
  932. if (c != ovl_chan)
  933. error(Einuse);
  934. if (scr->mmio[mmoffset[CrtcGenCntl]] & 1) { /* double scan enable */
  935. y *= 2;
  936. h *= 2;
  937. }
  938. waitforfifo(scr, 2);
  939. scr->mmio[mmoffset[OverlayYX]] =
  940. ((x & 0xFFFF) << 16) | (y & 0xFFFF);
  941. scr->mmio[mmoffset[OverlayYXEnd]] =
  942. (((x + w) & 0xFFFF) << 16) | ((y + h) & 0xFFFF);
  943. h_inc = (ovl_width << 12) / (w >> 1); /* ??? */
  944. v_inc = (ovl_height << 12) / h;
  945. waitforfifo(scr, 2);
  946. scr->mmio[mmoffset[OverlayScaleInc]] =
  947. ((h_inc & 0xFFFF) << 16) | (v_inc & 0xFFFF);
  948. scr->mmio[mmoffset[ScalerHeightWidth]] =
  949. ((ovl_width & 0xFFFF) << 16) | (ovl_height & 0xFFFF);
  950. waitforidle(scr);
  951. scr->mmio[mmoffset[OverlayScaleCntl]] |=
  952. (SCALE_ENABLE|OVERLAY_ENABLE);
  953. }
  954. static void
  955. ovl_status(VGAscr *scr, Chan *, char **field)
  956. {
  957. pprint("%s: %s %.4uX, VT/GT %s, PRO %s, ovlclock %d, rev B %s, refclock %ld\n",
  958. scr->dev->name, field[0], mach64type->m64_id,
  959. mach64type->m64_vtgt? "yes": "no",
  960. mach64type->m64_pro? "yes": "no",
  961. mach64type->m64_ovlclock,
  962. mach64revb? "yes": "no",
  963. mach64refclock);
  964. pprint("%s: storage @%.8luX, aperture @%8.ulX, ovl buf @%.8ulX\n",
  965. scr->dev->name, scr->storage, scr->paddr,
  966. mach64overlay);
  967. }
  968. static void
  969. ovl_openctl(VGAscr *, Chan *c, char **)
  970. {
  971. if (ovl_chan)
  972. error(Einuse);
  973. ovl_chan = c;
  974. }
  975. static void
  976. ovl_closectl(VGAscr *scr, Chan *c, char **)
  977. {
  978. if (c != ovl_chan) return;
  979. waitforidle(scr);
  980. scr->mmio[mmoffset[OverlayScaleCntl]] &=
  981. ~(SCALE_ENABLE|OVERLAY_ENABLE);
  982. ovl_chan = nil;
  983. ovl_width = ovl_height = ovl_fib = 0;
  984. }
  985. enum
  986. {
  987. CMclosectl,
  988. CMconfigure,
  989. CMenable,
  990. CMopenctl,
  991. CMstatus,
  992. };
  993. static void (*ovl_cmds[])(VGAscr *, Chan *, char **) =
  994. {
  995. [CMclosectl] ovl_closectl,
  996. [CMconfigure] ovl_configure,
  997. [CMenable] ovl_enable,
  998. [CMopenctl] ovl_openctl,
  999. [CMstatus] ovl_status,
  1000. };
  1001. static Cmdtab mach64xxcmd[] =
  1002. {
  1003. CMclosectl, "closectl", 1,
  1004. CMconfigure, "configure", 4,
  1005. CMenable, "enable", 5,
  1006. CMopenctl, "openctl", 1,
  1007. CMstatus, "status", 1,
  1008. };
  1009. static void
  1010. mach64xxovlctl(VGAscr *scr, Chan *c, void *a, int n)
  1011. {
  1012. Cmdbuf *cb;
  1013. Cmdtab *ct;
  1014. if(!mach64type->m64_vtgt)
  1015. error(Enodev);
  1016. if(!scr->overlayinit){
  1017. scr->overlayinit = 1;
  1018. init_overlayclock(scr);
  1019. }
  1020. cb = parsecmd(a, n);
  1021. if(waserror()){
  1022. free(cb);
  1023. nexterror();
  1024. }
  1025. ct = lookupcmd(cb, mach64xxcmd, nelem(mach64xxcmd));
  1026. ovl_cmds[ct->index](scr, c, cb->f);
  1027. poperror();
  1028. free(cb);
  1029. }
  1030. static int
  1031. mach64xxovlwrite(VGAscr *scr, void *a, int len, vlong offs)
  1032. {
  1033. uchar *src;
  1034. int _len;
  1035. if (ovl_chan == nil) return len; /* Acts as a /dev/null */
  1036. /* Calculate the destination address */
  1037. _len = len;
  1038. src = (uchar *)a;
  1039. while (len > 0) {
  1040. ulong _offs;
  1041. int nb;
  1042. _offs = (ulong)(offs % ovl_fib);
  1043. nb = (_offs + len > ovl_fib)? ovl_fib - _offs: len;
  1044. memmove((uchar *)scr->vaddr + mach64overlay + _offs,
  1045. src, nb);
  1046. offs += nb;
  1047. src += nb;
  1048. len -= nb;
  1049. }
  1050. return _len;
  1051. }
  1052. VGAdev vgamach64xxdev = {
  1053. "mach64xx",
  1054. mach64xxenable, /* enable */
  1055. 0, /* disable */
  1056. 0, /* page */
  1057. mach64xxlinear, /* linear */
  1058. mach64xxdrawinit, /* drawinit */
  1059. 0,
  1060. mach64xxovlctl, /* overlay control */
  1061. mach64xxovlwrite, /* write the overlay */
  1062. };
  1063. VGAcur vgamach64xxcur = {
  1064. "mach64xxhwgc",
  1065. mach64xxcurenable, /* enable */
  1066. mach64xxcurdisable, /* disable */
  1067. mach64xxcurload, /* load */
  1068. mach64xxcurmove, /* move */
  1069. 1 /* doespanning */
  1070. };