pci.c 20 KB

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  1. /*
  2. * PCI support code.
  3. * To do:
  4. * initialise bridge mappings if the PCI BIOS didn't.
  5. */
  6. #include "u.h"
  7. #include "lib.h"
  8. #include "mem.h"
  9. #include "dat.h"
  10. #include "fns.h"
  11. #include "io.h"
  12. #include "error.h"
  13. enum { /* configuration mechanism #1 */
  14. PciADDR = 0xCF8, /* CONFIG_ADDRESS */
  15. PciDATA = 0xCFC, /* CONFIG_DATA */
  16. /* configuration mechanism #2 */
  17. PciCSE = 0xCF8, /* configuration space enable */
  18. PciFORWARD = 0xCFA, /* which bus */
  19. MaxFNO = 7,
  20. MaxUBN = 255,
  21. };
  22. enum
  23. { /* command register */
  24. IOen = (1<<0),
  25. MEMen = (1<<1),
  26. MASen = (1<<2),
  27. MemWrInv = (1<<4),
  28. PErrEn = (1<<6),
  29. SErrEn = (1<<8),
  30. };
  31. static Lock pcicfglock;
  32. static Lock pcicfginitlock;
  33. static int pcicfgmode = -1;
  34. static int pcimaxbno = 7;
  35. static int pcimaxdno;
  36. static Pcidev* pciroot;
  37. static Pcidev* pcilist;
  38. static Pcidev* pcitail;
  39. static int pcicfgrw32(int, int, int, int);
  40. static int pcicfgrw8(int, int, int, int);
  41. ulong
  42. pcibarsize(Pcidev *p, int rno)
  43. {
  44. ulong v, size;
  45. v = pcicfgrw32(p->tbdf, rno, 0, 1);
  46. pcicfgrw32(p->tbdf, rno, 0xFFFFFFF0, 0);
  47. size = pcicfgrw32(p->tbdf, rno, 0, 1);
  48. if(v & 1)
  49. size |= 0xFFFF0000;
  50. pcicfgrw32(p->tbdf, rno, v, 0);
  51. return -(size & ~0x0F);
  52. }
  53. /* side effect: if a video controller is seen, set vga non-zero */
  54. int
  55. pciscan(int bno, Pcidev** list)
  56. {
  57. Pcidev *p, *head, *tail;
  58. int dno, fno, i, hdt, l, maxfno, maxubn, rno, sbn, tbdf, ubn;
  59. maxubn = bno;
  60. head = nil;
  61. tail = nil;
  62. for(dno = 0; dno <= pcimaxdno; dno++){
  63. maxfno = 0;
  64. for(fno = 0; fno <= maxfno; fno++){
  65. /*
  66. * For this possible device, form the
  67. * bus+device+function triplet needed to address it
  68. * and try to read the vendor and device ID.
  69. * If successful, allocate a device struct and
  70. * start to fill it in with some useful information
  71. * from the device's configuration space.
  72. */
  73. tbdf = MKBUS(BusPCI, bno, dno, fno);
  74. l = pcicfgrw32(tbdf, PciVID, 0, 1);
  75. if(l == 0xFFFFFFFF || l == 0)
  76. continue;
  77. p = malloc(sizeof(*p));
  78. p->tbdf = tbdf;
  79. p->vid = l;
  80. p->did = l>>16;
  81. if(pcilist != nil)
  82. pcitail->list = p;
  83. else
  84. pcilist = p;
  85. pcitail = p;
  86. p->rid = pcicfgr8(p, PciRID);
  87. p->ccrp = pcicfgr8(p, PciCCRp);
  88. p->ccru = pcicfgr8(p, PciCCRu);
  89. p->ccrb = pcicfgr8(p, PciCCRb);
  90. p->pcr = pcicfgr32(p, PciPCR);
  91. p->intl = pcicfgr8(p, PciINTL);
  92. /*
  93. * If the device is a multi-function device adjust the
  94. * loop count so all possible functions are checked.
  95. */
  96. hdt = pcicfgr8(p, PciHDT);
  97. if(hdt & 0x80)
  98. maxfno = MaxFNO;
  99. /*
  100. * If appropriate, read the base address registers
  101. * and work out the sizes.
  102. */
  103. switch(p->ccrb){
  104. case 0x03: /* display controller */
  105. vga = 1;
  106. /* fall through */
  107. case 0x01: /* mass storage controller */
  108. case 0x02: /* network controller */
  109. case 0x04: /* multimedia device */
  110. case 0x07: /* simple comm. controllers */
  111. case 0x08: /* base system peripherals */
  112. case 0x09: /* input devices */
  113. case 0x0A: /* docking stations */
  114. case 0x0B: /* processors */
  115. case 0x0C: /* serial bus controllers */
  116. if((hdt & 0x7F) != 0)
  117. break;
  118. rno = PciBAR0 - 4;
  119. for(i = 0; i < nelem(p->mem); i++){
  120. rno += 4;
  121. p->mem[i].bar = pcicfgr32(p, rno);
  122. p->mem[i].size = pcibarsize(p, rno);
  123. }
  124. break;
  125. case 0x00:
  126. case 0x05: /* memory controller */
  127. case 0x06: /* bridge device */
  128. default:
  129. break;
  130. }
  131. if(head != nil)
  132. tail->link = p;
  133. else
  134. head = p;
  135. tail = p;
  136. }
  137. }
  138. *list = head;
  139. for(p = head; p != nil; p = p->link){
  140. /*
  141. * Find PCI-PCI and PCI-Cardbus bridges
  142. * and recursively descend the tree.
  143. */
  144. if(p->ccrb != 0x06 || p->ccru != 0x04)
  145. continue;
  146. /*
  147. * If the secondary or subordinate bus number is not
  148. * initialised try to do what the PCI BIOS should have
  149. * done and fill in the numbers as the tree is descended.
  150. * On the way down the subordinate bus number is set to
  151. * the maximum as it's not known how many buses are behind
  152. * this one; the final value is set on the way back up.
  153. */
  154. ubn = pcicfgr8(p, PciUBN);
  155. sbn = pcicfgr8(p, PciSBN);
  156. if(sbn == 0 || ubn == 0){
  157. sbn = maxubn+1;
  158. /*
  159. * Make sure memory, I/O and master enables are
  160. * off, set the primary, secondary and subordinate
  161. * bus numbers and clear the secondary status before
  162. * attempting to scan the secondary bus.
  163. *
  164. * Initialisation of the bridge should be done here.
  165. */
  166. pcicfgw32(p, PciPCR, 0xFFFF0000);
  167. l = (MaxUBN<<16)|(sbn<<8)|bno;
  168. pcicfgw32(p, PciPBN, l);
  169. pcicfgw16(p, PciSPSR, 0xFFFF);
  170. maxubn = pciscan(sbn, &p->bridge);
  171. l = (maxubn<<16)|(sbn<<8)|bno;
  172. pcicfgw32(p, PciPBN, l);
  173. }
  174. else{
  175. /*
  176. * You can't go back.
  177. * This shouldn't be possible, but the
  178. * Iwill DK8-HTX seems to have subordinate
  179. * bus numbers which get smaller on the
  180. * way down. Need to look more closely at
  181. * this.
  182. */
  183. if(ubn > maxubn)
  184. maxubn = ubn;
  185. pciscan(sbn, &p->bridge);
  186. }
  187. }
  188. return maxubn;
  189. }
  190. static uchar
  191. null_link(Pcidev *, uchar )
  192. {
  193. return 0;
  194. }
  195. static void
  196. null_init(Pcidev *, uchar , uchar )
  197. {
  198. }
  199. static uchar
  200. pIIx_link(Pcidev *router, uchar link)
  201. {
  202. uchar pirq;
  203. /* link should be 0x60, 0x61, 0x62, 0x63 */
  204. pirq = pcicfgr8(router, link);
  205. return (pirq < 16)? pirq: 0;
  206. }
  207. static void
  208. pIIx_init(Pcidev *router, uchar link, uchar irq)
  209. {
  210. pcicfgw8(router, link, irq);
  211. }
  212. static uchar
  213. via_link(Pcidev *router, uchar link)
  214. {
  215. uchar pirq;
  216. /* link should be 1, 2, 3, 5 */
  217. pirq = (link < 6)? pcicfgr8(router, 0x55 + (link>>1)): 0;
  218. return (link & 1)? (pirq >> 4): (pirq & 15);
  219. }
  220. static void
  221. via_init(Pcidev *router, uchar link, uchar irq)
  222. {
  223. uchar pirq;
  224. pirq = pcicfgr8(router, 0x55 + (link >> 1));
  225. pirq &= (link & 1)? 0x0f: 0xf0;
  226. pirq |= (link & 1)? (irq << 4): (irq & 15);
  227. pcicfgw8(router, 0x55 + (link>>1), pirq);
  228. }
  229. static uchar
  230. opti_link(Pcidev *router, uchar link)
  231. {
  232. uchar pirq = 0;
  233. /* link should be 0x02, 0x12, 0x22, 0x32 */
  234. if ((link & 0xcf) == 0x02)
  235. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  236. return (link & 0x10)? (pirq >> 4): (pirq & 15);
  237. }
  238. static void
  239. opti_init(Pcidev *router, uchar link, uchar irq)
  240. {
  241. uchar pirq;
  242. pirq = pcicfgr8(router, 0xb8 + (link >> 5));
  243. pirq &= (link & 0x10)? 0x0f : 0xf0;
  244. pirq |= (link & 0x10)? (irq << 4): (irq & 15);
  245. pcicfgw8(router, 0xb8 + (link >> 5), pirq);
  246. }
  247. static uchar
  248. ali_link(Pcidev *router, uchar link)
  249. {
  250. /* No, you're not dreaming */
  251. static const uchar map[] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
  252. uchar pirq;
  253. /* link should be 0x01..0x08 */
  254. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  255. return (link & 1)? map[pirq&15]: map[pirq>>4];
  256. }
  257. static void
  258. ali_init(Pcidev *router, uchar link, uchar irq)
  259. {
  260. /* Inverse of map in ali_link */
  261. static const uchar map[] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
  262. uchar pirq;
  263. pirq = pcicfgr8(router, 0x48 + ((link-1)>>1));
  264. pirq &= (link & 1)? 0x0f: 0xf0;
  265. pirq |= (link & 1)? (map[irq] << 4): (map[irq] & 15);
  266. pcicfgw8(router, 0x48 + ((link-1)>>1), pirq);
  267. }
  268. static uchar
  269. cyrix_link(Pcidev *router, uchar link)
  270. {
  271. uchar pirq;
  272. /* link should be 1, 2, 3, 4 */
  273. pirq = pcicfgr8(router, 0x5c + ((link-1)>>1));
  274. return ((link & 1)? pirq >> 4: pirq & 15);
  275. }
  276. static void
  277. cyrix_init(Pcidev *router, uchar link, uchar irq)
  278. {
  279. uchar pirq;
  280. pirq = pcicfgr8(router, 0x5c + (link>>1));
  281. pirq &= (link & 1)? 0x0f: 0xf0;
  282. pirq |= (link & 1)? (irq << 4): (irq & 15);
  283. pcicfgw8(router, 0x5c + (link>>1), pirq);
  284. }
  285. typedef struct {
  286. ushort sb_vid, sb_did;
  287. uchar (*sb_translate)(Pcidev *, uchar);
  288. void (*sb_initialize)(Pcidev *, uchar, uchar);
  289. } bridge_t;
  290. static bridge_t southbridges[] = {
  291. { 0x8086, 0x122e, pIIx_link, pIIx_init }, // Intel 82371FB
  292. { 0x8086, 0x1234, pIIx_link, pIIx_init }, // Intel 82371MX
  293. { 0x8086, 0x7000, pIIx_link, pIIx_init }, // Intel 82371SB
  294. { 0x8086, 0x7110, pIIx_link, pIIx_init }, // Intel 82371AB
  295. { 0x8086, 0x7198, pIIx_link, pIIx_init }, // Intel 82443MX (fn 1)
  296. { 0x8086, 0x2410, pIIx_link, pIIx_init }, // Intel 82801AA
  297. { 0x8086, 0x2420, pIIx_link, pIIx_init }, // Intel 82801AB
  298. { 0x8086, 0x2440, pIIx_link, pIIx_init }, // Intel 82801BA
  299. { 0x8086, 0x244c, pIIx_link, pIIx_init }, // Intel 82801BAM
  300. { 0x8086, 0x2480, pIIx_link, pIIx_init }, // Intel 82801CA
  301. { 0x8086, 0x248c, pIIx_link, pIIx_init }, // Intel 82801CAM
  302. { 0x8086, 0x24c0, pIIx_link, pIIx_init }, // Intel 82801DBL
  303. { 0x8086, 0x24cc, pIIx_link, pIIx_init }, // Intel 82801DBM
  304. { 0x8086, 0x24d0, pIIx_link, pIIx_init }, // Intel 82801EB
  305. { 0x8086, 0x2640, pIIx_link, pIIx_init }, // Intel 82801FB
  306. { 0x8086, 0x27b8, pIIx_link, pIIx_init }, // Intel 82801GB
  307. { 0x8086, 0x27b9, pIIx_link, pIIx_init }, // Intel 82801GBM
  308. { 0x1106, 0x0586, via_link, via_init }, // Viatech 82C586
  309. { 0x1106, 0x0596, via_link, via_init }, // Viatech 82C596
  310. { 0x1106, 0x0686, via_link, via_init }, // Viatech 82C686
  311. { 0x1106, 0x3227, via_link, via_init }, // Viatech VT8237
  312. { 0x1045, 0xc700, opti_link, opti_init }, // Opti 82C700
  313. { 0x10b9, 0x1533, ali_link, ali_init }, // Al M1533
  314. { 0x1039, 0x0008, pIIx_link, pIIx_init }, // SI 503
  315. { 0x1039, 0x0496, pIIx_link, pIIx_init }, // SI 496
  316. { 0x1078, 0x0100, cyrix_link, cyrix_init }, // Cyrix 5530 Legacy
  317. { 0x1002, 0x4377, nil, nil }, // ATI Radeon Xpress 200M
  318. { 0x1002, 0x4372, nil, nil }, // ATI SB400
  319. { 0x1022, 0x746B, nil, nil }, // AMD 8111
  320. { 0x10DE, 0x00D1, nil, nil }, // NVIDIA nForce 3
  321. { 0x10DE, 0x00E0, nil, nil }, // NVIDIA nForce 3 250 Series
  322. { 0x10DE, 0x00E1, nil, nil }, // NVIDIA nForce 3 250 Series
  323. { 0x1166, 0x0200, nil, nil }, // ServerWorks ServerSet III LE
  324. };
  325. typedef struct {
  326. uchar e_bus; // Pci bus number
  327. uchar e_dev; // Pci device number
  328. uchar e_maps[12]; // Avoid structs! Link and mask.
  329. uchar e_slot; // Add-in/built-in slot
  330. uchar e_reserved;
  331. } slot_t;
  332. typedef struct {
  333. uchar rt_signature[4]; // Routing table signature
  334. uchar rt_version[2]; // Version number
  335. uchar rt_size[2]; // Total table size
  336. uchar rt_bus; // Interrupt router bus number
  337. uchar rt_devfn; // Router's devfunc
  338. uchar rt_pciirqs[2]; // Exclusive PCI irqs
  339. uchar rt_compat[4]; // Compatible PCI interrupt router
  340. uchar rt_miniport[4]; // Miniport data
  341. uchar rt_reserved[11];
  342. uchar rt_checksum;
  343. } router_t;
  344. static ushort pciirqs; // Exclusive PCI irqs
  345. static bridge_t *southbridge; // Which southbridge to use.
  346. static void
  347. pcirouting(void)
  348. {
  349. uchar *p, pin, irq;
  350. ulong tbdf, vdid;
  351. ushort vid, did;
  352. router_t *r;
  353. slot_t *e;
  354. int size, i, fn;
  355. Pcidev *sbpci, *pci;
  356. // Peek in the BIOS
  357. for (p = (uchar *)KADDR(0xf0000); p < (uchar *)KADDR(0xfffff); p += 16)
  358. if (p[0] == '$' && p[1] == 'P' && p[2] == 'I' && p[3] == 'R')
  359. break;
  360. if (p >= (uchar *)KADDR(0xfffff))
  361. return;
  362. r = (router_t *)p;
  363. // print("PCI interrupt routing table version %d.%d at %.6uX\n",
  364. // r->rt_version[0], r->rt_version[1], (ulong)r & 0xfffff);
  365. tbdf = (BusPCI << 24)|(r->rt_bus << 16)|(r->rt_devfn << 8);
  366. vdid = pcicfgrw32(tbdf, PciVID, 0, 1);
  367. vid = vdid;
  368. did = vdid >> 16;
  369. for (i = 0; i != nelem(southbridges); i++)
  370. if (vid == southbridges[i].sb_vid && did == southbridges[i].sb_did)
  371. break;
  372. if (i == nelem(southbridges)) {
  373. print("pcirouting: South bridge %.4uX, %.4uX not found\n", vid, did);
  374. return;
  375. }
  376. southbridge = &southbridges[i];
  377. if ((sbpci = pcimatch(nil, vid, did)) == nil) {
  378. print("pcirouting: Cannot match south bridge %.4uX, %.4uX\n",
  379. vid, did);
  380. return;
  381. }
  382. pciirqs = (r->rt_pciirqs[1] << 8)|r->rt_pciirqs[0];
  383. size = (r->rt_size[1] << 8)|r->rt_size[0];
  384. for (e = (slot_t *)&r[1]; (uchar *)e < p + size; e++) {
  385. // print("%.2uX/%.2uX %.2uX: ", e->e_bus, e->e_dev, e->e_slot);
  386. // for (i = 0; i != 4; i++) {
  387. // uchar *m = &e->e_maps[i * 3];
  388. // print("[%d] %.2uX %.4uX ",
  389. // i, m[0], (m[2] << 8)|m[1]);
  390. // }
  391. // print("\n");
  392. for (fn = 0; fn != 8; fn++) {
  393. uchar *m;
  394. // Retrieve the did and vid through the devfn before
  395. // obtaining the Pcidev structure.
  396. tbdf = (BusPCI << 24)|(e->e_bus << 16)|((e->e_dev | fn) << 8);
  397. vdid = pcicfgrw32(tbdf, PciVID, 0, 1);
  398. if (vdid == 0xFFFFFFFF || vdid == 0)
  399. continue;
  400. vid = vdid;
  401. did = vdid >> 16;
  402. pci = nil;
  403. while ((pci = pcimatch(pci, vid, did)) != nil) {
  404. if (pci->intl != 0 && pci->intl != 0xFF)
  405. continue;
  406. pin = pcicfgr8(pci, PciINTP);
  407. if (pin == 0 || pin == 0xff)
  408. continue;
  409. m = &e->e_maps[(pin - 1) * 3];
  410. irq = southbridge->sb_translate(sbpci, m[0]);
  411. if (irq) {
  412. print("pcirouting: %.4uX/%.4uX at pin %d irq %d\n",
  413. vid, did, pin, irq);
  414. pcicfgw8(pci, PciINTL, irq);
  415. pci->intl = irq;
  416. }
  417. }
  418. }
  419. }
  420. }
  421. static void
  422. pcicfginit(void)
  423. {
  424. char *p;
  425. int bno, n;
  426. Pcidev **list;
  427. lock(&pcicfginitlock);
  428. if(pcicfgmode != -1)
  429. goto out;
  430. /*
  431. * Try to determine which PCI configuration mode is implemented.
  432. * Mode2 uses a byte at 0xCF8 and another at 0xCFA; Mode1 uses
  433. * a DWORD at 0xCF8 and another at 0xCFC and will pass through
  434. * any non-DWORD accesses as normal I/O cycles. There shouldn't be
  435. * a device behind these addresses so if Mode1 accesses fail try
  436. * for Mode2 (Mode2 is deprecated).
  437. */
  438. /*
  439. * Bits [30:24] of PciADDR must be 0,
  440. * according to the spec.
  441. */
  442. n = inl(PciADDR);
  443. if(!(n & 0x7FF00000)){
  444. outl(PciADDR, 0x80000000);
  445. outb(PciADDR+3, 0);
  446. if(inl(PciADDR) & 0x80000000){
  447. pcicfgmode = 1;
  448. pcimaxdno = 31;
  449. }
  450. }
  451. outl(PciADDR, n);
  452. if(pcicfgmode < 0){
  453. /*
  454. * The 'key' part of PciCSE should be 0.
  455. */
  456. n = inb(PciCSE);
  457. if(!(n & 0xF0)){
  458. outb(PciCSE, 0x0E);
  459. if(inb(PciCSE) == 0x0E){
  460. pcicfgmode = 2;
  461. pcimaxdno = 15;
  462. }
  463. }
  464. outb(PciCSE, n);
  465. }
  466. if(pcicfgmode < 0)
  467. goto out;
  468. if(p = getconf("*pcimaxbno"))
  469. pcimaxbno = strtoul(p, 0, 0);
  470. if(p = getconf("*pcimaxdno"))
  471. pcimaxdno = strtoul(p, 0, 0);
  472. list = &pciroot;
  473. for(bno = 0; bno <= pcimaxbno; bno++) {
  474. bno = pciscan(bno, list);
  475. while(*list)
  476. list = &(*list)->link;
  477. }
  478. pcirouting();
  479. out:
  480. unlock(&pcicfginitlock);
  481. if(getconf("*pcihinv"))
  482. pcihinv(nil);
  483. }
  484. static int
  485. pcicfgrw8(int tbdf, int rno, int data, int read)
  486. {
  487. int o, type, x;
  488. if(pcicfgmode == -1)
  489. pcicfginit();
  490. if(BUSBNO(tbdf))
  491. type = 0x01;
  492. else
  493. type = 0x00;
  494. x = -1;
  495. if(BUSDNO(tbdf) > pcimaxdno)
  496. return x;
  497. lock(&pcicfglock);
  498. switch(pcicfgmode){
  499. case 1:
  500. o = rno & 0x03;
  501. rno &= ~0x03;
  502. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  503. if(read)
  504. x = inb(PciDATA+o);
  505. else
  506. outb(PciDATA+o, data);
  507. outl(PciADDR, 0);
  508. break;
  509. case 2:
  510. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  511. outb(PciFORWARD, BUSBNO(tbdf));
  512. if(read)
  513. x = inb((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  514. else
  515. outb((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  516. outb(PciCSE, 0);
  517. break;
  518. }
  519. unlock(&pcicfglock);
  520. return x;
  521. }
  522. int
  523. pcicfgr8(Pcidev* pcidev, int rno)
  524. {
  525. return pcicfgrw8(pcidev->tbdf, rno, 0, 1);
  526. }
  527. void
  528. pcicfgw8(Pcidev* pcidev, int rno, int data)
  529. {
  530. pcicfgrw8(pcidev->tbdf, rno, data, 0);
  531. }
  532. static int
  533. pcicfgrw16(int tbdf, int rno, int data, int read)
  534. {
  535. int o, type, x;
  536. if(pcicfgmode == -1)
  537. pcicfginit();
  538. if(BUSBNO(tbdf))
  539. type = 0x01;
  540. else
  541. type = 0x00;
  542. x = -1;
  543. if(BUSDNO(tbdf) > pcimaxdno)
  544. return x;
  545. lock(&pcicfglock);
  546. switch(pcicfgmode){
  547. case 1:
  548. o = rno & 0x02;
  549. rno &= ~0x03;
  550. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  551. if(read)
  552. x = ins(PciDATA+o);
  553. else
  554. outs(PciDATA+o, data);
  555. outl(PciADDR, 0);
  556. break;
  557. case 2:
  558. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  559. outb(PciFORWARD, BUSBNO(tbdf));
  560. if(read)
  561. x = ins((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  562. else
  563. outs((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  564. outb(PciCSE, 0);
  565. break;
  566. }
  567. unlock(&pcicfglock);
  568. return x;
  569. }
  570. int
  571. pcicfgr16(Pcidev* pcidev, int rno)
  572. {
  573. return pcicfgrw16(pcidev->tbdf, rno, 0, 1);
  574. }
  575. void
  576. pcicfgw16(Pcidev* pcidev, int rno, int data)
  577. {
  578. pcicfgrw16(pcidev->tbdf, rno, data, 0);
  579. }
  580. static int
  581. pcicfgrw32(int tbdf, int rno, int data, int read)
  582. {
  583. int type, x;
  584. if(pcicfgmode == -1)
  585. pcicfginit();
  586. if(BUSBNO(tbdf))
  587. type = 0x01;
  588. else
  589. type = 0x00;
  590. x = -1;
  591. if(BUSDNO(tbdf) > pcimaxdno)
  592. return x;
  593. lock(&pcicfglock);
  594. switch(pcicfgmode){
  595. case 1:
  596. rno &= ~0x03;
  597. outl(PciADDR, 0x80000000|BUSBDF(tbdf)|rno|type);
  598. if(read)
  599. x = inl(PciDATA);
  600. else
  601. outl(PciDATA, data);
  602. outl(PciADDR, 0);
  603. break;
  604. case 2:
  605. outb(PciCSE, 0x80|(BUSFNO(tbdf)<<1));
  606. outb(PciFORWARD, BUSBNO(tbdf));
  607. if(read)
  608. x = inl((0xC000|(BUSDNO(tbdf)<<8)) + rno);
  609. else
  610. outl((0xC000|(BUSDNO(tbdf)<<8)) + rno, data);
  611. outb(PciCSE, 0);
  612. break;
  613. }
  614. unlock(&pcicfglock);
  615. return x;
  616. }
  617. int
  618. pcicfgr32(Pcidev* pcidev, int rno)
  619. {
  620. return pcicfgrw32(pcidev->tbdf, rno, 0, 1);
  621. }
  622. void
  623. pcicfgw32(Pcidev* pcidev, int rno, int data)
  624. {
  625. pcicfgrw32(pcidev->tbdf, rno, data, 0);
  626. }
  627. Pcidev*
  628. pcimatch(Pcidev* prev, int vid, int did)
  629. {
  630. if(pcicfgmode == -1)
  631. pcicfginit();
  632. if(prev == nil)
  633. prev = pcilist;
  634. else
  635. prev = prev->list;
  636. while(prev != nil) {
  637. if((vid == 0 || prev->vid == vid)
  638. && (did == 0 || prev->did == did))
  639. break;
  640. prev = prev->list;
  641. }
  642. return prev;
  643. }
  644. uchar
  645. pciipin(Pcidev *pci, uchar pin)
  646. {
  647. if (pci == nil)
  648. pci = pcilist;
  649. while (pci) {
  650. uchar intl;
  651. if (pcicfgr8(pci, PciINTP) == pin && pci->intl != 0 && pci->intl != 0xff)
  652. return pci->intl;
  653. if (pci->bridge && (intl = pciipin(pci->bridge, pin)) != 0)
  654. return intl;
  655. pci = pci->list;
  656. }
  657. return 0;
  658. }
  659. static ushort
  660. pciimask(Pcidev *pci)
  661. {
  662. ushort imask;
  663. imask = 0;
  664. while (pci) {
  665. if (pcicfgr8(pci, PciINTP) && pci->intl < 16)
  666. imask |= 1 << pci->intl;
  667. if (pci->bridge)
  668. imask |= pciimask(pci->bridge);
  669. pci = pci->list;
  670. }
  671. return imask;
  672. }
  673. uchar
  674. pciintl(Pcidev *pci)
  675. {
  676. ushort imask;
  677. int i;
  678. if (pci == nil)
  679. pci = pcilist;
  680. imask = pciimask(pci) | 1;
  681. for (i = 0; i != 16; i++)
  682. if ((imask & (1 << i)) == 0)
  683. return i;
  684. return 0;
  685. }
  686. void
  687. pcihinv(Pcidev* p)
  688. {
  689. int i;
  690. Pcidev *t;
  691. if(pcicfgmode == -1)
  692. pcicfginit();
  693. if(p == nil) {
  694. p = pciroot;
  695. print("bus dev type vid did intl memory\n");
  696. }
  697. for(t = p; t != nil; t = t->link) {
  698. print("%d %2d/%d %.2ux %.2ux %.2ux %.4ux %.4ux %3d ",
  699. BUSBNO(t->tbdf), BUSDNO(t->tbdf), BUSFNO(t->tbdf),
  700. t->ccrb, t->ccru, t->ccrp, t->vid, t->did, t->intl);
  701. for(i = 0; i < nelem(p->mem); i++) {
  702. if(t->mem[i].size == 0)
  703. continue;
  704. print("%d:%.8lux %d ", i,
  705. t->mem[i].bar, t->mem[i].size);
  706. }
  707. print("\n");
  708. }
  709. while(p != nil) {
  710. if(p->bridge != nil)
  711. pcihinv(p->bridge);
  712. p = p->link;
  713. }
  714. }
  715. void
  716. pcireset(void)
  717. {
  718. Pcidev *p;
  719. int pcr;
  720. if(pcicfgmode == -1)
  721. pcicfginit();
  722. for(p = pcilist; p != nil; p = p->list){
  723. pcr = pcicfgr16(p, PciPSR);
  724. pcicfgw16(p, PciPSR, pcr & ~0x04);
  725. }
  726. }
  727. void
  728. pcisetioe(Pcidev* p)
  729. {
  730. p->pcr |= IOen;
  731. pcicfgw16(p, PciPCR, p->pcr);
  732. }
  733. void
  734. pciclrioe(Pcidev* p)
  735. {
  736. p->pcr &= ~IOen;
  737. pcicfgw16(p, PciPCR, p->pcr);
  738. }
  739. void
  740. pcisetbme(Pcidev* p)
  741. {
  742. p->pcr |= MASen;
  743. pcicfgw16(p, PciPCR, p->pcr);
  744. }
  745. void
  746. pciclrbme(Pcidev* p)
  747. {
  748. p->pcr &= ~MASen;
  749. pcicfgw16(p, PciPCR, p->pcr);
  750. }
  751. void
  752. pcisetmwi(Pcidev* p)
  753. {
  754. p->pcr |= MemWrInv;
  755. pcicfgw16(p, PciPCR, p->pcr);
  756. }
  757. void
  758. pciclrmwi(Pcidev* p)
  759. {
  760. p->pcr &= ~MemWrInv;
  761. pcicfgw16(p, PciPCR, p->pcr);
  762. }
  763. static int
  764. pcigetpmrb(Pcidev* p)
  765. {
  766. int ptr;
  767. if(p->pmrb != 0)
  768. return p->pmrb;
  769. p->pmrb = -1;
  770. /*
  771. * If there are no extended capabilities implemented,
  772. * (bit 4 in the status register) assume there's no standard
  773. * power management method.
  774. * Find the capabilities pointer based on PCI header type.
  775. */
  776. if(!(pcicfgr16(p, PciPSR) & 0x0010))
  777. return -1;
  778. switch(pcicfgr8(p, PciHDT)){
  779. default:
  780. return -1;
  781. case 0: /* all other */
  782. case 1: /* PCI to PCI bridge */
  783. ptr = 0x34;
  784. break;
  785. case 2: /* CardBus bridge */
  786. ptr = 0x14;
  787. break;
  788. }
  789. ptr = pcicfgr32(p, ptr);
  790. while(ptr != 0){
  791. /*
  792. * Check for validity.
  793. * Can't be in standard header and must be double
  794. * word aligned.
  795. */
  796. if(ptr < 0x40 || (ptr & ~0xFC))
  797. return -1;
  798. if(pcicfgr8(p, ptr) == 0x01){
  799. p->pmrb = ptr;
  800. return ptr;
  801. }
  802. ptr = pcicfgr8(p, ptr+1);
  803. }
  804. return -1;
  805. }
  806. int
  807. pcigetpms(Pcidev* p)
  808. {
  809. int pmcsr, ptr;
  810. if((ptr = pcigetpmrb(p)) == -1)
  811. return -1;
  812. /*
  813. * Power Management Register Block:
  814. * offset 0: Capability ID
  815. * 1: next item pointer
  816. * 2: capabilities
  817. * 4: control/status
  818. * 6: bridge support extensions
  819. * 7: data
  820. */
  821. pmcsr = pcicfgr16(p, ptr+4);
  822. return pmcsr & 0x0003;
  823. }
  824. int
  825. pcisetpms(Pcidev* p, int state)
  826. {
  827. int ostate, pmc, pmcsr, ptr;
  828. if((ptr = pcigetpmrb(p)) == -1)
  829. return -1;
  830. pmc = pcicfgr16(p, ptr+2);
  831. pmcsr = pcicfgr16(p, ptr+4);
  832. ostate = pmcsr & 0x0003;
  833. pmcsr &= ~0x0003;
  834. switch(state){
  835. default:
  836. return -1;
  837. case 0:
  838. break;
  839. case 1:
  840. if(!(pmc & 0x0200))
  841. return -1;
  842. break;
  843. case 2:
  844. if(!(pmc & 0x0400))
  845. return -1;
  846. break;
  847. case 3:
  848. break;
  849. }
  850. pmcsr |= state;
  851. pcicfgw16(p, ptr+4, pmcsr);
  852. return ostate;
  853. }