uartaxp.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930
  1. /*
  2. * Avanstar Xp pci uart driver
  3. */
  4. #include "u.h"
  5. #include "../port/lib.h"
  6. #include "mem.h"
  7. #include "dat.h"
  8. #include "fns.h"
  9. #include "io.h"
  10. #include "../port/error.h"
  11. #include "uartaxp.i"
  12. typedef struct Cc Cc;
  13. typedef struct Ccb Ccb;
  14. typedef struct Ctlr Ctlr;
  15. typedef struct Gcb Gcb;
  16. /*
  17. * Global Control Block.
  18. * Service Request fields must be accessed using XCHG.
  19. */
  20. struct Gcb {
  21. u16int gcw; /* Global Command Word */
  22. u16int gsw; /* Global Status Word */
  23. u16int gsr; /* Global Service Request */
  24. u16int abs; /* Available Buffer Space */
  25. u16int bt; /* Board Type */
  26. u16int cpv; /* Control Program Version */
  27. u16int ccbn; /* Ccb count */
  28. u16int ccboff; /* Ccb offset */
  29. u16int ccbsz; /* Ccb size */
  30. u16int gcw2; /* Global Command Word 2 */
  31. u16int gsw2; /* Global Status Word 2 */
  32. u16int esr; /* Error Service Request */
  33. u16int isr; /* Input Service Request */
  34. u16int osr; /* Output Service Request */
  35. u16int msr; /* Modem Service Request */
  36. u16int csr; /* Command Service Request */
  37. };
  38. /*
  39. * Channel Control Block.
  40. */
  41. struct Ccb {
  42. u16int br; /* Baud Rate */
  43. u16int df; /* Data Format */
  44. u16int lp; /* Line Protocol */
  45. u16int ibs; /* Input Buffer Size */
  46. u16int obs; /* Output Buffer Size */
  47. u16int ibtr; /* Ib Trigger Rate */
  48. u16int oblw; /* Ob Low Watermark */
  49. u8int ixon[2]; /* IXON characters */
  50. u16int ibhw; /* Ib High Watermark */
  51. u16int iblw; /* Ib Low Watermark */
  52. u16int cc; /* Channel Command */
  53. u16int cs; /* Channel Status */
  54. u16int ibsa; /* Ib Start Addr */
  55. u16int ibea; /* Ib Ending Addr */
  56. u16int obsa; /* Ob Start Addr */
  57. u16int obea; /* Ob Ending Addr */
  58. u16int ibwp; /* Ib write pointer (RO) */
  59. u16int ibrp; /* Ib read pointer (R/W) */
  60. u16int obwp; /* Ob write pointer (R/W) */
  61. u16int obrp; /* Ob read pointer (RO) */
  62. u16int ces; /* Communication Error Status */
  63. u16int bcp; /* Bad Character Pointer */
  64. u16int mc; /* Modem Control */
  65. u16int ms; /* Modem Status */
  66. u16int bs; /* Blocking Status */
  67. u16int crf; /* Character Received Flag */
  68. u8int ixoff[2]; /* IXOFF characters */
  69. u16int cs2; /* Channel Status 2 */
  70. u8int sec[2]; /* Strip/Error Characters */
  71. };
  72. enum { /* br */
  73. Br76800 = 0xFF00,
  74. Br115200 = 0xFF01,
  75. };
  76. enum { /* df */
  77. Db5 = 0x0000, /* Data Bits - 5 bits/byte */
  78. Db6 = 0x0001, /* 6 bits/byte */
  79. Db7 = 0x0002, /* 7 bits/byte */
  80. Db8 = 0x0003, /* 8 bits/byte */
  81. DbMASK = 0x0003,
  82. Sb1 = 0x0000, /* 1 Stop Bit */
  83. Sb2 = 0x0004, /* 2 Stop Bit */
  84. SbMASK = 0x0004,
  85. Np = 0x0000, /* No Parity */
  86. Op = 0x0008, /* Odd Parity */
  87. Ep = 0x0010, /* Even Parity */
  88. Mp = 0x0020, /* Mark Parity */
  89. Sp = 0x0030, /* Space Parity */
  90. PMASK = 0x0038,
  91. Cmn = 0x0000, /* Channel Mode Normal */
  92. Cme = 0x0040, /* CM Echo */
  93. Cmll = 0x0080, /* CM Local Loopback */
  94. Cmrl = 0x00C0, /* CM Remote Loopback */
  95. };
  96. enum { /* lp */
  97. Ixon = 0x0001, /* Obey IXON/IXOFF */
  98. Ixany = 0x0002, /* Any character retarts Tx */
  99. Ixgen = 0x0004, /* Generate IXON/IXOFF */
  100. Cts = 0x0008, /* CTS controls Tx */
  101. Dtr = 0x0010, /* Rx controls DTR */
  102. ½d = 0x0020, /* RTS off during Tx */
  103. Rts = 0x0040, /* generate RTS */
  104. Emcs = 0x0080, /* Enable Modem Control */
  105. Ecs = 0x1000, /* Enable Character Stripping */
  106. Eia422 = 0x2000, /* EIA422 */
  107. };
  108. enum { /* cc */
  109. Ccu = 0x0001, /* Configure Channel and UART */
  110. Cco = 0x0002, /* Configure Channel Only */
  111. Fib = 0x0004, /* Flush Input Buffer */
  112. Fob = 0x0008, /* Flush Output Buffer */
  113. Er = 0x0010, /* Enable Receiver */
  114. Dr = 0x0020, /* Disable Receiver */
  115. Et = 0x0040, /* Enable Transmitter */
  116. Dt = 0x0080, /* Disable Transmitter */
  117. };
  118. enum { /* ces */
  119. Oe = 0x0001, /* Overrun Error */
  120. Pe = 0x0002, /* Parity Error */
  121. Fe = 0x0004, /* Framing Error */
  122. Br = 0x0008, /* Break Received */
  123. };
  124. enum { /* mc */
  125. Adtr = 0x0001, /* Assert DTR */
  126. Arts = 0x0002, /* Assert RTS */
  127. Ab = 0x0010, /* Assert BREAK */
  128. };
  129. enum { /* ms */
  130. Scts = 0x0001, /* Status od CTS */
  131. Sdsr = 0x0002, /* Status of DSR */
  132. Sri = 0x0004, /* Status of RI */
  133. Sdcd = 0x0008, /* Status of DCD */
  134. };
  135. enum { /* bs */
  136. Rd = 0x0001, /* Receiver Disabled */
  137. Td = 0x0002, /* Transmitter Disabled */
  138. Tbxoff = 0x0004, /* Tx Blocked by XOFF */
  139. Tbcts = 0x0008, /* Tx Blocked by CTS */
  140. Rbxoff = 0x0010, /* Rx Blocked by XOFF */
  141. Rbrts = 0x0020, /* Rx Blocked by RTS */
  142. };
  143. enum { /* Local Configuration */
  144. Range = 0x00,
  145. Remap = 0x04,
  146. Region = 0x18,
  147. Mb0 = 0x40, /* Mailbox 0 */
  148. Ldb = 0x60, /* PCI to Local Doorbell */
  149. Pdb = 0x64, /* Local to PCI Doorbell */
  150. Ics = 0x68, /* Interrupt Control/Status */
  151. Mcc = 0x6C, /* Misc. Command and Control */
  152. };
  153. enum { /* Mb0 */
  154. Edcc = 1, /* exec. downloaded code cmd */
  155. Aic = 0x10, /* adapter init'zed correctly */
  156. Cpr = 1ul << 31, /* control program ready */
  157. };
  158. enum { /* Mcc */
  159. Rcr = 1ul << 29, /* reload config. reg.s */
  160. Asr = 1ul << 30, /* pci adapter sw reset */
  161. Lis = 1ul << 31, /* local init status */
  162. };
  163. typedef struct Cc Cc;
  164. typedef struct Ccb Ccb;
  165. typedef struct Ctlr Ctlr;
  166. /*
  167. * Channel Control, one per uart.
  168. * Devuart communicates via the PhysUart functions with
  169. * a Uart* argument. Uart.regs is filled in by this driver
  170. * to point to a Cc, and Cc.ctlr points to the Axp board
  171. * controller.
  172. */
  173. struct Cc {
  174. int uartno;
  175. Ccb* ccb;
  176. Ctlr* ctlr;
  177. Rendez;
  178. Uart;
  179. };
  180. typedef struct Ctlr {
  181. char* name;
  182. Pcidev* pcidev;
  183. int ctlrno;
  184. Ctlr* next;
  185. u32int* reg;
  186. uchar* mem;
  187. Gcb* gcb;
  188. int im;
  189. Cc cc[16];
  190. } Ctlr;
  191. #define csr32r(c, r) (*((c)->reg+((r)/4)))
  192. #define csr32w(c, r, v) (*((c)->reg+((r)/4)) = (v))
  193. static Ctlr* axpctlrhead;
  194. static Ctlr* axpctlrtail;
  195. extern PhysUart axpphysuart;
  196. static int
  197. axpccdone(void* ccb)
  198. {
  199. return !((Ccb*)ccb)->cc;
  200. }
  201. static void
  202. axpcc(Cc* cc, int cmd)
  203. {
  204. Ccb *ccb;
  205. int timeo;
  206. u16int cs;
  207. ccb = cc->ccb;
  208. ccb->cc = cmd;
  209. if(!cc->ctlr->im){
  210. for(timeo = 0; timeo < 1000000; timeo++){
  211. if(!ccb->cc)
  212. break;
  213. microdelay(1);
  214. }
  215. }
  216. else
  217. tsleep(cc, axpccdone, ccb, 1000);
  218. cs = ccb->cs;
  219. if(ccb->cc || cs){
  220. print("%s: cmd %#ux didn't terminate: %#ux %#ux\n",
  221. cc->name, cmd, ccb->cc, cs);
  222. if(cc->ctlr->im)
  223. error(Eio);
  224. }
  225. }
  226. static long
  227. axpstatus(Uart* uart, void* buf, long n, long offset)
  228. {
  229. char *p;
  230. Ccb *ccb;
  231. u16int bs, fstat, ms;
  232. ccb = ((Cc*)(uart->regs))->ccb;
  233. p = malloc(READSTR);
  234. bs = ccb->bs;
  235. fstat = ccb->df;
  236. ms = ccb->ms;
  237. snprint(p, READSTR,
  238. "b%d c%d d%d e%d l%d m%d p%c r%d s%d i%d\n"
  239. "dev(%d) type(%d) framing(%d) overruns(%d) "
  240. "berr(%d) serr(%d)%s%s%s%s\n",
  241. uart->baud,
  242. uart->hup_dcd,
  243. ms & Sdsr,
  244. uart->hup_dsr,
  245. (fstat & DbMASK) + 5,
  246. 0,
  247. (fstat & PMASK) ? ((fstat & Ep) == Ep? 'e': 'o'): 'n',
  248. (bs & Rbrts) ? 1 : 0,
  249. (fstat & Sb2) ? 2 : 1,
  250. 0,
  251. uart->dev,
  252. uart->type,
  253. uart->ferr,
  254. uart->oerr,
  255. uart->berr,
  256. uart->serr,
  257. (ms & Scts) ? " cts" : "",
  258. (ms & Sdsr) ? " dsr" : "",
  259. (ms & Sdcd) ? " dcd" : "",
  260. (ms & Sri) ? " ring" : ""
  261. );
  262. n = readstr(offset, buf, n, p);
  263. free(p);
  264. return n;
  265. }
  266. static void
  267. axpfifo(Uart*, int)
  268. {
  269. }
  270. static void
  271. axpdtr(Uart* uart, int on)
  272. {
  273. Ccb *ccb;
  274. u16int mc;
  275. ccb = ((Cc*)(uart->regs))->ccb;
  276. mc = ccb->mc;
  277. if(on)
  278. mc |= Adtr;
  279. else
  280. mc &= ~Adtr;
  281. ccb->mc = mc;
  282. }
  283. static void
  284. axprts(Uart* uart, int on)
  285. {
  286. Ccb *ccb;
  287. u16int mc;
  288. ccb = ((Cc*)(uart->regs))->ccb;
  289. mc = ccb->mc;
  290. if(on)
  291. mc |= Arts;
  292. else
  293. mc &= ~Arts;
  294. ccb->mc = mc;
  295. }
  296. static void
  297. axpmodemctl(Uart* uart, int on)
  298. {
  299. Ccb *ccb;
  300. u16int lp;
  301. ccb = ((Cc*)(uart->regs))->ccb;
  302. ilock(&uart->tlock);
  303. lp = ccb->lp;
  304. if(on){
  305. lp |= Cts|Rts;
  306. lp &= ~Emcs;
  307. uart->cts = ccb->ms & Scts;
  308. }
  309. else{
  310. lp &= ~(Cts|Rts);
  311. lp |= Emcs;
  312. uart->cts = 1;
  313. }
  314. uart->modem = on;
  315. iunlock(&uart->tlock);
  316. ccb->lp = lp;
  317. axpcc(uart->regs, Ccu);
  318. }
  319. static int
  320. axpparity(Uart* uart, int parity)
  321. {
  322. Ccb *ccb;
  323. u16int df;
  324. switch(parity){
  325. default:
  326. return -1;
  327. case 'e':
  328. parity = Ep;
  329. break;
  330. case 'o':
  331. parity = Op;
  332. break;
  333. case 'n':
  334. parity = Np;
  335. break;
  336. }
  337. ccb = ((Cc*)(uart->regs))->ccb;
  338. df = ccb->df & ~PMASK;
  339. ccb->df = df|parity;
  340. axpcc(uart->regs, Ccu);
  341. return 0;
  342. }
  343. static int
  344. axpstop(Uart* uart, int stop)
  345. {
  346. Ccb *ccb;
  347. u16int df;
  348. switch(stop){
  349. default:
  350. return -1;
  351. case 1:
  352. stop = Sb1;
  353. break;
  354. case 2:
  355. stop = Sb2;
  356. break;
  357. }
  358. ccb = ((Cc*)(uart->regs))->ccb;
  359. df = ccb->df & ~SbMASK;
  360. ccb->df = df|stop;
  361. axpcc(uart->regs, Ccu);
  362. return 0;
  363. }
  364. static int
  365. axpbits(Uart* uart, int bits)
  366. {
  367. Ccb *ccb;
  368. u16int df;
  369. bits -= 5;
  370. if(bits < 0 || bits > 3)
  371. return -1;
  372. ccb = ((Cc*)(uart->regs))->ccb;
  373. df = ccb->df & ~DbMASK;
  374. ccb->df = df|bits;
  375. axpcc(uart->regs, Ccu);
  376. return 0;
  377. }
  378. static int
  379. axpbaud(Uart* uart, int baud)
  380. {
  381. Ccb *ccb;
  382. int i, ibtr;
  383. /*
  384. * Set baud rate (high rates are special - only 16 bits).
  385. */
  386. if(baud <= 0)
  387. return -1;
  388. uart->baud = baud;
  389. ccb = ((Cc*)(uart->regs))->ccb;
  390. switch(baud){
  391. default:
  392. ccb->br = baud;
  393. break;
  394. case 76800:
  395. ccb->br = Br76800;
  396. break;
  397. case 115200:
  398. ccb->br = Br115200;
  399. break;
  400. }
  401. /*
  402. * Set trigger level to about 50 per second.
  403. */
  404. ibtr = baud/500;
  405. i = (ccb->ibea - ccb->ibsa)/2;
  406. if(ibtr > i)
  407. ibtr = i;
  408. ccb->ibtr = ibtr;
  409. axpcc(uart->regs, Ccu);
  410. return 0;
  411. }
  412. static void
  413. axpbreak(Uart* uart, int ms)
  414. {
  415. Ccb *ccb;
  416. u16int mc;
  417. /*
  418. * Send a break.
  419. */
  420. if(ms <= 0)
  421. ms = 200;
  422. ccb = ((Cc*)(uart->regs))->ccb;
  423. mc = ccb->mc;
  424. ccb->mc = Ab|mc;
  425. tsleep(&up->sleep, return0, 0, ms);
  426. ccb->mc = mc & ~Ab;
  427. }
  428. static void
  429. axpmc(Cc* cc)
  430. {
  431. int old;
  432. Ccb *ccb;
  433. u16int ms;
  434. ccb = cc->ccb;
  435. ms = ccb->ms;
  436. if(ms & Scts){
  437. ilock(&cc->tlock);
  438. old = cc->cts;
  439. cc->cts = ms & Scts;
  440. if(old == 0 && cc->cts)
  441. cc->ctsbackoff = 2;
  442. iunlock(&cc->tlock);
  443. }
  444. if(ms & Sdsr){
  445. old = ms & Sdsr;
  446. if(cc->hup_dsr && cc->dsr && !old)
  447. cc->dohup = 1;
  448. cc->dsr = old;
  449. }
  450. if(ms & Sdcd){
  451. old = ms & Sdcd;
  452. if(cc->hup_dcd && cc->dcd && !old)
  453. cc->dohup = 1;
  454. cc->dcd = old;
  455. }
  456. }
  457. static void
  458. axpkick(Uart* uart)
  459. {
  460. Cc *cc;
  461. Ccb *ccb;
  462. uchar *ep, *mem, *rp, *wp;
  463. if(uart->cts == 0 || uart->blocked)
  464. return;
  465. cc = uart->regs;
  466. ccb = cc->ccb;
  467. mem = (uchar*)cc->ctlr->gcb;
  468. rp = mem + ccb->obrp;
  469. wp = mem + ccb->obwp;
  470. ep = mem + ccb->obea;
  471. while(wp != rp-1){
  472. if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
  473. break;
  474. if(wp > ep)
  475. wp = mem + ccb->obsa;
  476. *wp++ = *(uart->op++);
  477. ccb->obwp = wp - mem;
  478. }
  479. }
  480. static void
  481. axprecv(Cc* cc)
  482. {
  483. Ccb *ccb;
  484. uchar *ep, *mem, *rp, *wp;
  485. ccb = cc->ccb;
  486. mem = (uchar*)cc->ctlr->gcb;
  487. rp = mem + ccb->ibrp;
  488. wp = mem + ccb->ibwp;
  489. ep = mem + ccb->ibea;
  490. while(rp != wp){
  491. if(rp > ep)
  492. rp = mem + ccb->ibsa;
  493. uartrecv(cc, *rp++);
  494. ccb->ibrp = rp - mem;
  495. }
  496. }
  497. static void
  498. axpinterrupt(Ureg*, void* arg)
  499. {
  500. Cc *cc;
  501. Ctlr *ctlr;
  502. u32int ics;
  503. u16int r, sr;
  504. ctlr = arg;
  505. ics = csr32r(ctlr, Ics);
  506. if(ics & 0x0810C000)
  507. print("%s: unexpected interrupt %#ux\n", ctlr->name, ics);
  508. if(!(ics & 0x00002000))
  509. return;
  510. // while(work to do){
  511. cc = ctlr->cc;
  512. for(sr = xchgw(&ctlr->gcb->isr, 0); sr != 0; sr >>= 1){
  513. if(sr & 0x0001)
  514. axprecv(cc);
  515. cc++;
  516. }
  517. cc = ctlr->cc;
  518. for(sr = xchgw(&ctlr->gcb->osr, 0); sr != 0; sr >>= 1){
  519. if(sr & 0x0001)
  520. uartkick(&cc->Uart);
  521. cc++;
  522. }
  523. cc = ctlr->cc;
  524. for(sr = xchgw(&ctlr->gcb->csr, 0); sr != 0; sr >>= 1){
  525. if(sr & 0x0001)
  526. wakeup(cc);
  527. cc++;
  528. }
  529. cc = ctlr->cc;
  530. for(sr = xchgw(&ctlr->gcb->msr, 0); sr != 0; sr >>= 1){
  531. if(sr & 0x0001)
  532. axpmc(cc);
  533. cc++;
  534. }
  535. cc = ctlr->cc;
  536. for(sr = xchgw(&ctlr->gcb->esr, 0); sr != 0; sr >>= 1){
  537. if(sr & 0x0001){
  538. r = cc->ccb->ms;
  539. if(r & Oe)
  540. cc->oerr++;
  541. if(r & Pe)
  542. cc->perr++;
  543. if(r & Fe)
  544. cc->ferr++;
  545. }
  546. cc++;
  547. }
  548. // }
  549. csr32w(ctlr, Pdb, 1);
  550. ctlr->gcb->gcw2 = 0x0001;
  551. }
  552. static void
  553. axpdisable(Uart* uart)
  554. {
  555. Cc *cc;
  556. u16int lp;
  557. Ctlr *ctlr;
  558. /*
  559. * Turn off DTR and RTS, disable interrupts.
  560. */
  561. (*uart->phys->dtr)(uart, 0);
  562. (*uart->phys->rts)(uart, 0);
  563. cc = uart->regs;
  564. lp = cc->ccb->lp;
  565. cc->ccb->lp = Emcs|lp;
  566. axpcc(cc, Dt|Dr|Fob|Fib|Ccu);
  567. /*
  568. * The Uart is qlocked.
  569. */
  570. ctlr = cc->ctlr;
  571. ctlr->im &= ~(1<<cc->uartno);
  572. if(ctlr->im == 0)
  573. intrdisable(ctlr->pcidev->intl, axpinterrupt, ctlr,
  574. ctlr->pcidev->tbdf, ctlr->name);
  575. }
  576. static void
  577. axpenable(Uart* uart, int ie)
  578. {
  579. Cc *cc;
  580. Ctlr *ctlr;
  581. u16int lp;
  582. cc = uart->regs;
  583. ctlr = cc->ctlr;
  584. /*
  585. * Enable interrupts and turn on DTR and RTS.
  586. * Be careful if this is called to set up a polled serial line
  587. * early on not to try to enable interrupts as interrupt-
  588. * -enabling mechanisms might not be set up yet.
  589. */
  590. if(ie){
  591. /*
  592. * The Uart is qlocked.
  593. */
  594. if(ctlr->im == 0){
  595. intrenable(ctlr->pcidev->intl, axpinterrupt, ctlr,
  596. ctlr->pcidev->tbdf, ctlr->name);
  597. csr32w(ctlr, Ics, 0x00031F00);
  598. csr32w(ctlr, Pdb, 1);
  599. ctlr->gcb->gcw2 = 1;
  600. }
  601. ctlr->im |= 1<<cc->uartno;
  602. }
  603. (*uart->phys->dtr)(uart, 1);
  604. (*uart->phys->rts)(uart, 1);
  605. /*
  606. * Make sure we control RTS, DTR and break.
  607. */
  608. lp = cc->ccb->lp;
  609. cc->ccb->lp = Emcs|lp;
  610. cc->ccb->oblw = 64;
  611. axpcc(cc, Et|Er|Ccu);
  612. }
  613. static void*
  614. axpdealloc(Ctlr* ctlr)
  615. {
  616. int i;
  617. for(i = 0; i < 16; i++){
  618. if(ctlr->cc[i].name != nil)
  619. free(ctlr->cc[i].name);
  620. }
  621. if(ctlr->reg != nil)
  622. vunmap(ctlr->reg, ctlr->pcidev->mem[0].size);
  623. if(ctlr->mem != nil)
  624. vunmap(ctlr->mem, ctlr->pcidev->mem[2].size);
  625. if(ctlr->name != nil)
  626. free(ctlr->name);
  627. free(ctlr);
  628. return nil;
  629. }
  630. static Uart*
  631. axpalloc(int ctlrno, Pcidev* pcidev)
  632. {
  633. Cc *cc;
  634. uchar *p;
  635. Ctlr *ctlr;
  636. void *addr;
  637. char name[64];
  638. u32int bar, r;
  639. int i, n, timeo;
  640. ctlr = malloc(sizeof(Ctlr));
  641. seprint(name, name+sizeof(name), "uartaxp%d", ctlrno);
  642. kstrdup(&ctlr->name, name);
  643. ctlr->pcidev = pcidev;
  644. ctlr->ctlrno = ctlrno;
  645. /*
  646. * Access to runtime registers.
  647. */
  648. bar = pcidev->mem[0].bar;
  649. if((addr = vmap(bar & ~0x0F, pcidev->mem[0].size)) == 0){
  650. print("%s: can't map registers at %#ux\n", ctlr->name, bar);
  651. return axpdealloc(ctlr);
  652. }
  653. ctlr->reg = addr;
  654. print("%s: port 0x%ux irq %d ", ctlr->name, bar, pcidev->intl);
  655. /*
  656. * Local address space 0.
  657. */
  658. bar = pcidev->mem[2].bar;
  659. if((addr = vmap(bar & ~0x0F, pcidev->mem[2].size)) == 0){
  660. print("%s: can't map memory at %#ux\n", ctlr->name, bar);
  661. return axpdealloc(ctlr);
  662. }
  663. ctlr->mem = addr;
  664. ctlr->gcb = (Gcb*)(ctlr->mem+0x10000);
  665. print("mem 0x%ux size %d: ", bar, pcidev->mem[2].size);
  666. /*
  667. * Toggle the software reset and wait for
  668. * the adapter local init status to indicate done.
  669. *
  670. * The two 'delay(100)'s below are important,
  671. * without them the board seems to become confused
  672. * (perhaps it needs some 'quiet time' because the
  673. * timeout loops are not sufficient in themselves).
  674. */
  675. r = csr32r(ctlr, Mcc);
  676. csr32w(ctlr, Mcc, r|Asr);
  677. microdelay(1);
  678. csr32w(ctlr, Mcc, r&~Asr);
  679. delay(100);
  680. for(timeo = 0; timeo < 100000; timeo++){
  681. if(csr32r(ctlr, Mcc) & Lis)
  682. break;
  683. microdelay(1);
  684. }
  685. if(!(csr32r(ctlr, Mcc) & Lis)){
  686. print("%s: couldn't reset\n", ctlr->name);
  687. return axpdealloc(ctlr);
  688. }
  689. print("downloading...");
  690. /*
  691. * Copy the control programme to the card memory.
  692. * The card's i960 control structures live at 0xD000.
  693. */
  694. if(sizeof(uartaxpcp) > 0xD000){
  695. print("%s: control programme too big\n", ctlr->name);
  696. return axpdealloc(ctlr);
  697. }
  698. /* TODO: is this right for more than 1 card? */
  699. csr32w(ctlr, Remap, 0xA0000001);
  700. for(i = 0; i < sizeof(uartaxpcp); i++)
  701. ctlr->mem[i] = uartaxpcp[i];
  702. /*
  703. * Execute downloaded code and wait for it
  704. * to signal ready.
  705. */
  706. csr32w(ctlr, Mb0, Edcc);
  707. delay(100);
  708. /* the manual says to wait for Cpr for 1 second */
  709. for(timeo = 0; timeo < 10000; timeo++){
  710. if(csr32r(ctlr, Mb0) & Cpr)
  711. break;
  712. microdelay(100);
  713. }
  714. if(!(csr32r(ctlr, Mb0) & Cpr)){
  715. print("control programme not ready; Mb0 %#ux\n",
  716. csr32r(ctlr, Mb0));
  717. print("%s: might not be fully seated in its PCI slot\n",
  718. ctlr->name);
  719. return axpdealloc(ctlr);
  720. }
  721. print("\n");
  722. n = ctlr->gcb->ccbn;
  723. if(ctlr->gcb->bt != 0x12 || n > 16){
  724. print("%s: wrong board type %#ux, %d channels\n",
  725. ctlr->name, ctlr->gcb->bt, ctlr->gcb->ccbn);
  726. return axpdealloc(ctlr);
  727. }
  728. p = ((uchar*)ctlr->gcb) + ctlr->gcb->ccboff;
  729. for(i = 0; i < n; i++){
  730. cc = &ctlr->cc[i];
  731. cc->ccb = (Ccb*)p;
  732. p += ctlr->gcb->ccbsz;
  733. cc->uartno = i;
  734. cc->ctlr = ctlr;
  735. cc->regs = cc;
  736. seprint(name, name+sizeof(name), "uartaxp%d%2.2d", ctlrno, i);
  737. kstrdup(&cc->name, name);
  738. cc->freq = 0;
  739. cc->bits = 8;
  740. cc->stop = 1;
  741. cc->parity = 'n';
  742. cc->baud = 9600;
  743. cc->phys = &axpphysuart;
  744. cc->console = 0;
  745. cc->special = 0;
  746. cc->next = &ctlr->cc[i+1];
  747. }
  748. ctlr->cc[n-1].next = nil;
  749. if(axpctlrhead != nil)
  750. axpctlrtail->next = ctlr;
  751. else
  752. axpctlrhead = ctlr;
  753. axpctlrtail = ctlr;
  754. return ctlr->cc;
  755. }
  756. static Uart*
  757. axppnp(void)
  758. {
  759. Pcidev *p;
  760. int ctlrno;
  761. Uart *head, *tail, *uart;
  762. /*
  763. * Loop through all PCI devices looking for simple serial
  764. * controllers (ccrb == 0x07) and configure the ones which
  765. * are familiar.
  766. */
  767. head = tail = nil;
  768. ctlrno = 0;
  769. for(p = pcimatch(nil, 0, 0); p != nil; p = pcimatch(p, 0, 0)){
  770. if(p->ccrb != 0x07)
  771. continue;
  772. switch((p->did<<16)|p->vid){
  773. default:
  774. continue;
  775. case (0x6001<<16)|0x114F: /* AvanstarXp */
  776. if((uart = axpalloc(ctlrno, p)) == nil)
  777. continue;
  778. break;
  779. }
  780. if(head != nil)
  781. tail->next = uart;
  782. else
  783. head = uart;
  784. for(tail = uart; tail->next != nil; tail = tail->next)
  785. ;
  786. ctlrno++;
  787. }
  788. return head;
  789. }
  790. PhysUart axpphysuart = {
  791. .name = "AvanstarXp",
  792. .pnp = axppnp,
  793. .enable = axpenable,
  794. .disable = axpdisable,
  795. .kick = axpkick,
  796. .dobreak = axpbreak,
  797. .baud = axpbaud,
  798. .bits = axpbits,
  799. .stop = axpstop,
  800. .parity = axpparity,
  801. .modemctl = axpmodemctl,
  802. .rts = axprts,
  803. .dtr = axpdtr,
  804. .status = axpstatus,
  805. .fifo = axpfifo,
  806. .getc = nil,
  807. .putc = nil,
  808. };