bitsyreset.s 2.3 KB

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  1. #include "mem.h"
  2. // Bitsy development board uses two banks: KM416S4030C,
  3. // 12 row address bits, 8 col address bits
  4. // Bitsy uses two banks KM416S8030C, 12 row address bits,
  5. // 9 col address bits
  6. // Have to set DRAC0 to 14 row bits or else you only get 8 col bits
  7. // from the formfactor unit configuration registers: 0xF3536257
  8. mdcnfg: // DRAM Configuration Register 10.2.1
  9. WORD 1<<0 | 1<<2 | 0<<3 | 0x5<<4 | 0x3<<8 | 3<<12 | 3<<14
  10. mdrefr0: // DRAM Refresh Control Register 10.2.2
  11. WORD 1<<0 | 0x200<<4 | 1<<21 | 1<<22 | 1 <<31
  12. mdrefr1: // DRAM Refresh Control Register 10.2.2
  13. WORD 1<<0 | 0x200<<4 | 1<<21 | 1<<22
  14. mdrefr2: // DRAM Refresh Control Register 10.2.2
  15. WORD 1<<0 | 0x200<<4 | 1<<20 | 1<<21 | 1<<22
  16. /* MDCAS settings from [1] Table 10-3 (page 10-18) */
  17. waveform0:
  18. WORD 0xAAAAAAA7
  19. waveform1:
  20. WORD 0xAAAAAAAA
  21. waveform2:
  22. WORD 0xAAAAAAAA
  23. delay: // delay without using memory
  24. mov $100, r1 // 200MHz: 100 × (2 instructions @ 5 ns) == 1 ms
  25. l1:
  26. sub $1, r1
  27. bgt l1
  28. sub $1, r0
  29. bgt delay
  30. ret
  31. reset:
  32. mov $INTREGS+4, r0 // turn off interrupts
  33. mov $0, (r0)
  34. // Is this necessary on wakeup?
  35. mov $POWERREGS+14, r0 // set clock speed to 191.7MHz
  36. mov $0xb, (r0)
  37. // This is necessary on hard reset, but not on sleep reset
  38. mov $0x80, r0 // wait ±128 µs
  39. bl delay
  40. /* check to see if we're operating out of DRAM */
  41. bic $0x000000ff, pc, r4
  42. bic $0x0000ff00, r4
  43. bic $0x00ff0000, r4
  44. cmp r4, $PHYSDRAM0
  45. beq dram
  46. dramwakeup:
  47. mov $POWERREGS+0x4, r1 // Clear DH in Power Manager Sleep Status Register
  48. bic $(1<<3), (r1) // DH == DRAM Hold
  49. // This releases nCAS/DQM and nRAS/nSDCS pins to make DRAM exit selfrefresh
  50. /* Set up the DRAM in banks 0 and 1 [1] 10.3 */
  51. mov $MEMCONFREGS, r1
  52. mov mdrefr0, r2 // Turn on K1RUN
  53. mov r2, 0x1c(r1)
  54. mov mdrefr1, r2 // Turn off SLFRSH
  55. mov r2, 0x1c(r1)
  56. mov mdrefr2, r2 // Turn on E1PIN
  57. mov r2, 0x1c(r1)
  58. mov waveform0, r2
  59. mov r2, 0x4(r1)
  60. mov waveform1, r2
  61. mov r2, 0x8(r1)
  62. mov waveform2, r2
  63. mov r2, 0xc(r1)
  64. mov $PHYSDRAM0, r0
  65. mov 0x00(r0), r2 // Eight non-burst read cycles
  66. mov 0x20(r0), r2
  67. mov 0x40(r0), r2
  68. mov 0x60(r0), r2
  69. mov 0x80(r0), r2
  70. mov 0xa0(r0), r2
  71. mov 0xc0(r0), r2
  72. mov 0xe0(r0), r2
  73. mov mdcnfg, r2 // Enable memory banks
  74. mov r2, 0x0(r1)
  75. // Is there any use in turning on EAPD and KAPD in the MDREFR register?
  76. ret
  77. dram: