l.s 11 KB

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  1. #include "mem.h"
  2. /* use of SPRG registers in save/restore */
  3. #define SAVER0 SPRG0
  4. #define SAVER1 SPRG1
  5. #define SAVELR SPRG2
  6. #define SAVEXX SPRG3
  7. /* special instruction definitions */
  8. #define BDNZ BC 16,0,
  9. #define BDNE BC 0,2,
  10. #define TLBIA WORD $((31<<26)|(307<<1))
  11. #define TLBSYNC WORD $((31<<26)|(566<<1))
  12. /* on some models mtmsr doesn't synchronise enough (eg, 603e) */
  13. #define MSRSYNC SYNC; ISYNC
  14. #define UREGSPACE (UREGSIZE+8)
  15. TEXT start(SB), $-4
  16. /*
  17. * setup MSR
  18. * turn off interrupts
  19. * use 0x000 as exception prefix
  20. * enable machine check
  21. */
  22. MOVW MSR, R3
  23. MOVW $(MSR_EE|MSR_IP), R4
  24. ANDN R4, R3
  25. OR $(MSR_ME), R3
  26. ISYNC
  27. MOVW R3, MSR
  28. MSRSYNC
  29. /* except during trap handling, R0 is zero from now on */
  30. MOVW $0, R0
  31. /* setup SB for pre mmu */
  32. MOVW $setSB(SB), R2
  33. MOVW $KZERO, R3
  34. ANDN R3, R2
  35. BL mmuinit0(SB)
  36. /* running with MMU on!! */
  37. /* set R2 to correct value */
  38. MOVW $setSB(SB), R2
  39. /* debugger sets R1 to top of usable memory +1 */
  40. MOVW R1, memsize(SB)
  41. BL kfpinit(SB)
  42. /* set up Mach */
  43. MOVW $mach0(SB), R(MACH)
  44. ADD $(MACHSIZE-8), R(MACH), R1 /* set stack */
  45. MOVW R0, R(USER)
  46. MOVW R0, 0(R(MACH))
  47. BL main(SB)
  48. RETURN /* not reached */
  49. GLOBL mach0(SB), $(MAXMACH*BY2PG)
  50. GLOBL memsize(SB), $4
  51. /*
  52. * on return from this function we will be running in virtual mode.
  53. * We set up the Block Address Translation (BAT) registers thus:
  54. * 1) first 3 BATs are 256M blocks, starting from KZERO->0
  55. * 2) remaining BAT maps last 256M directly
  56. */
  57. TEXT mmuinit0(SB), $0
  58. /* reset all the tlbs */
  59. MOVW $64, R3
  60. MOVW R3, CTR
  61. MOVW $0, R4
  62. tlbloop:
  63. TLBIE R4
  64. ADD $BIT(19), R4
  65. BDNZ tlbloop
  66. TLBSYNC
  67. /* KZERO -> 0 */
  68. MOVW $(KZERO|(0x7ff<<2)|2), R3
  69. MOVW $(PTEVALID|PTEWRITE), R4
  70. MOVW R3, SPR(IBATU(0))
  71. MOVW R4, SPR(IBATL(0))
  72. MOVW R3, SPR(DBATU(0))
  73. MOVW R4, SPR(DBATL(0))
  74. /* KZERO+256M -> 256M */
  75. ADD $(1<<28), R3
  76. ADD $(1<<28), R4
  77. MOVW R3, SPR(IBATU(1))
  78. MOVW R4, SPR(IBATL(1))
  79. MOVW R3, SPR(DBATU(1))
  80. MOVW R4, SPR(DBATL(1))
  81. /* KZERO+512M -> 512M */
  82. ADD $(1<<28), R3
  83. ADD $(1<<28), R4
  84. MOVW R3, SPR(IBATU(2))
  85. MOVW R4, SPR(IBATL(2))
  86. MOVW R3, SPR(DBATU(2))
  87. MOVW R4, SPR(DBATL(2))
  88. /* direct map last block, uncached, (?guarded) */
  89. MOVW $((0xf<<28)|(0x7ff<<2)|2), R3
  90. MOVW $((0xf<<28)|PTE1_I|PTE1_G|PTE1_RW), R4
  91. MOVW R3, SPR(DBATU(3))
  92. MOVW R4, SPR(DBATL(3))
  93. /* IBAT 3 unused */
  94. MOVW R0, SPR(IBATU(3))
  95. MOVW R0, SPR(IBATL(3))
  96. /* enable MMU */
  97. MOVW LR, R3
  98. OR $KZERO, R3
  99. MOVW R3, SPR(SRR0)
  100. MOVW MSR, R4
  101. OR $(MSR_IR|MSR_DR), R4
  102. MOVW R4, SPR(SRR1)
  103. RFI /* resume in kernel mode in caller */
  104. RETURN
  105. TEXT kfpinit(SB), $0
  106. MOVFL $0,FPSCR(7)
  107. MOVFL $0xD,FPSCR(6) /* VE, OE, ZE */
  108. MOVFL $0, FPSCR(5)
  109. MOVFL $0, FPSCR(3)
  110. MOVFL $0, FPSCR(2)
  111. MOVFL $0, FPSCR(1)
  112. MOVFL $0, FPSCR(0)
  113. FMOVD $4503601774854144.0, F27
  114. FMOVD $0.5, F29
  115. FSUB F29, F29, F28
  116. FADD F29, F29, F30
  117. FADD F30, F30, F31
  118. FMOVD F28, F0
  119. FMOVD F28, F1
  120. FMOVD F28, F2
  121. FMOVD F28, F3
  122. FMOVD F28, F4
  123. FMOVD F28, F5
  124. FMOVD F28, F6
  125. FMOVD F28, F7
  126. FMOVD F28, F8
  127. FMOVD F28, F9
  128. FMOVD F28, F10
  129. FMOVD F28, F11
  130. FMOVD F28, F12
  131. FMOVD F28, F13
  132. FMOVD F28, F14
  133. FMOVD F28, F15
  134. FMOVD F28, F16
  135. FMOVD F28, F17
  136. FMOVD F28, F18
  137. FMOVD F28, F19
  138. FMOVD F28, F20
  139. FMOVD F28, F21
  140. FMOVD F28, F22
  141. FMOVD F28, F23
  142. FMOVD F28, F24
  143. FMOVD F28, F25
  144. FMOVD F28, F26
  145. RETURN
  146. TEXT splhi(SB), $0
  147. MOVW LR, R31
  148. MOVW R31, 4(R(MACH)) /* save PC in m->splpc */
  149. MOVW MSR, R3
  150. RLWNM $0, R3, $~MSR_EE, R4
  151. SYNC
  152. MOVW R4, MSR
  153. MSRSYNC
  154. RETURN
  155. TEXT splx(SB), $0
  156. /* fall though */
  157. TEXT splxpc(SB), $0
  158. MOVW LR, R31
  159. MOVW R31, 4(R(MACH)) /* save PC in m->splpc */
  160. MOVW MSR, R4
  161. RLWMI $0, R3, $MSR_EE, R4
  162. SYNC
  163. MOVW R4, MSR
  164. MSRSYNC
  165. RETURN
  166. TEXT spllo(SB), $0
  167. MOVW MSR, R3
  168. OR $MSR_EE, R3, R4
  169. SYNC
  170. MOVW R4, MSR
  171. MSRSYNC
  172. RETURN
  173. TEXT spldone(SB), $0
  174. RETURN
  175. TEXT islo(SB), $0
  176. MOVW MSR, R3
  177. RLWNM $0, R3, $MSR_EE, R3
  178. RETURN
  179. TEXT setlabel(SB), $-4
  180. MOVW LR, R31
  181. MOVW R1, 0(R3)
  182. MOVW R31, 4(R3)
  183. MOVW $0, R3
  184. RETURN
  185. TEXT gotolabel(SB), $-4
  186. MOVW 4(R3), R31
  187. MOVW R31, LR
  188. MOVW 0(R3), R1
  189. MOVW $1, R3
  190. RETURN
  191. TEXT touser(SB), $-4
  192. MOVW $(UTZERO+32), R5 /* header appears in text */
  193. MOVW $(MSR_EE|MSR_PR|MSR_ME|MSR_IR|MSR_DR|MSR_RI), R4
  194. MOVW R4, SPR(SRR1)
  195. MOVW R3, R1
  196. MOVW R5, SPR(SRR0)
  197. RFI
  198. TEXT icflush(SB), $-4 /* icflush(virtaddr, count) */
  199. MOVW n+4(FP), R4
  200. RLWNM $0, R3, $~(CACHELINESZ-1), R5
  201. SUB R5, R3
  202. ADD R3, R4
  203. ADD $(CACHELINESZ-1), R4
  204. SRAW $CACHELINELOG, R4
  205. MOVW R4, CTR
  206. icf0: ICBI (R5)
  207. ADD $CACHELINESZ, R5
  208. BDNZ icf0
  209. ISYNC
  210. RETURN
  211. TEXT dcflush(SB), $-4 /* dcflush(virtaddr, count) */
  212. MOVW n+4(FP), R4
  213. RLWNM $0, R3, $~(CACHELINESZ-1), R5
  214. CMP R4, $0
  215. BLE dcf1
  216. SUB R5, R3
  217. ADD R3, R4
  218. ADD $(CACHELINESZ-1), R4
  219. SRAW $CACHELINELOG, R4
  220. MOVW R4, CTR
  221. dcf0: DCBF (R5)
  222. ADD $CACHELINESZ, R5
  223. BDNZ dcf0
  224. dcf1:
  225. SYNC
  226. RETURN
  227. TEXT tas(SB), $0
  228. SYNC
  229. MOVW R3, R4
  230. MOVW $0xdead,R5
  231. tas1:
  232. DCBF (R4) /* fix for 603x bug */
  233. LWAR (R4), R3
  234. CMP R3, $0
  235. BNE tas0
  236. STWCCC R5, (R4)
  237. BNE tas1
  238. tas0:
  239. SYNC
  240. ISYNC
  241. RETURN
  242. TEXT _xinc(SB),$0 /* void _xinc(long *); */
  243. MOVW R3, R4
  244. xincloop:
  245. DCBF (R4) /* fix for 603x bug */
  246. LWAR (R4), R3
  247. ADD $1, R3
  248. STWCCC R3, (R4)
  249. BNE xincloop
  250. RETURN
  251. TEXT _xdec(SB),$0 /* long _xdec(long *); */
  252. MOVW R3, R4
  253. xdecloop:
  254. DCBF (R4) /* fix for 603x bug */
  255. LWAR (R4), R3
  256. ADD $-1, R3
  257. STWCCC R3, (R4)
  258. BNE xdecloop
  259. RETURN
  260. TEXT cmpswap(SB),$0 /* int cmpswap(long*, long, long) */
  261. MOVW R3, R4 /* addr */
  262. MOVW old+4(FP), R5
  263. MOVW new+8(FP), R6
  264. DCBF (R4) /* fix for 603x bug? */
  265. LWAR (R4), R3
  266. CMP R3, R5
  267. BNE fail
  268. STWCCC R6, (R4)
  269. BNE fail
  270. MOVW $1, R3
  271. RETURN
  272. fail:
  273. MOVW $0, R3
  274. RETURN
  275. TEXT getpvr(SB), $0
  276. MOVW SPR(PVR), R3
  277. RETURN
  278. TEXT getdec(SB), $0
  279. MOVW SPR(DEC), R3
  280. RETURN
  281. TEXT putdec(SB), $0
  282. MOVW R3, SPR(DEC)
  283. RETURN
  284. TEXT getdar(SB), $0
  285. MOVW SPR(DAR), R3
  286. RETURN
  287. TEXT getdsisr(SB), $0
  288. MOVW SPR(DSISR), R3
  289. RETURN
  290. TEXT getmsr(SB), $0
  291. MOVW MSR, R3
  292. RETURN
  293. TEXT putmsr(SB), $0
  294. SYNC
  295. MOVW R3, MSR
  296. MSRSYNC
  297. RETURN
  298. TEXT putsdr1(SB), $0
  299. MOVW R3, SPR(SDR1)
  300. RETURN
  301. TEXT putsr(SB), $0
  302. MOVW 4(FP), R4
  303. MOVW R4, SEG(R3)
  304. RETURN
  305. TEXT gethid0(SB), $0
  306. MOVW SPR(HID0), R3
  307. RETURN
  308. TEXT gethid1(SB), $0
  309. MOVW SPR(HID1), R3
  310. RETURN
  311. TEXT puthid0(SB), $0
  312. MOVW R3, SPR(HID0)
  313. RETURN
  314. TEXT puthid1(SB), $0
  315. MOVW R3, SPR(HID1)
  316. RETURN
  317. TEXT eieio(SB), $0
  318. EIEIO
  319. RETURN
  320. TEXT sync(SB), $0
  321. SYNC
  322. RETURN
  323. TEXT tlbflushall(SB), $0
  324. MOVW $64, R3
  325. MOVW R3, CTR
  326. MOVW $0, R4
  327. tlbflushall0:
  328. TLBIE R4
  329. ADD $BIT(19), R4
  330. BDNZ tlbflushall0
  331. EIEIO
  332. TLBSYNC
  333. SYNC
  334. RETURN
  335. TEXT tlbflush(SB), $0
  336. TLBIE R3
  337. RETURN
  338. TEXT gotopc(SB), $0
  339. MOVW R3, CTR
  340. MOVW LR, R31 /* for trace back */
  341. BR (CTR)
  342. /*
  343. * traps force memory mapping off.
  344. * the following code has been executed at the exception
  345. * vector location
  346. * MOVW R0, SPR(SAVER0)
  347. * MOVW LR, R0
  348. * MOVW R0, SPR(SAVELR)
  349. * bl trapvec(SB)
  350. */
  351. TEXT trapvec(SB), $-4
  352. MOVW LR, R0
  353. MOVW R1, SPR(SAVER1)
  354. MOVW R0, SPR(SAVEXX) /* vector */
  355. /* did we come from user space */
  356. MOVW SPR(SRR1), R0
  357. MOVW CR, R1
  358. MOVW R0, CR
  359. BC 4,17,ktrap
  360. /* switch to kernel stack */
  361. MOVW R1, CR
  362. MOVW R2, R0
  363. MOVW $setSB(SB), R2
  364. RLWNM $0, R2, $~KZERO, R2 /* PADDR(setSB) */
  365. MOVW $mach0(SB), R1 /* m-> */
  366. RLWNM $0, R1, $~KZERO, R1 /* PADDR(m->) */
  367. MOVW 8(R1), R1 /* m->proc */
  368. RLWNM $0, R1, $~KZERO, R1 /* PADDR(m->proc) */
  369. MOVW 8(R1), R1 /* m->proc->kstack */
  370. RLWNM $0, R1, $~KZERO, R1 /* PADDR(m->proc->kstack) */
  371. ADD $(KSTACK-UREGSIZE), R1
  372. MOVW R0, R2
  373. BL saveureg(SB)
  374. BL trap(SB)
  375. BR restoreureg
  376. ktrap:
  377. MOVW R1, CR
  378. MOVW SPR(SAVER1), R1
  379. RLWNM $0, R1, $~KZERO, R1 /* PADDR(R1) */
  380. SUB $UREGSPACE, R1
  381. BL saveureg(SB)
  382. BL trap(SB)
  383. BR restoreureg
  384. /*
  385. * enter with stack set and mapped.
  386. * on return, SB (R2) has been set, and R3 has the Ureg*,
  387. * the MMU has been re-enabled, kernel text and PC are in KSEG,
  388. * R(MACH) has been set, and R0 contains 0.
  389. *
  390. */
  391. TEXT saveureg(SB), $-4
  392. /*
  393. * save state
  394. */
  395. MOVMW R2, 48(R1) /* r2:r31 */
  396. MOVW $setSB(SB), R2
  397. RLWNM $0, R2, $~KZERO, R2 /* PADDR(setSB) */
  398. MOVW $mach0(SB), R(MACH)
  399. RLWNM $0, R(MACH), $~KZERO, R(MACH) /* PADDR(m->) */
  400. MOVW 8(R(MACH)), R(USER)
  401. MOVW $mach0(SB), R(MACH)
  402. MOVW $setSB(SB), R2
  403. MOVW SPR(SAVER1), R4
  404. MOVW R4, 44(R1)
  405. MOVW SPR(SAVER0), R5
  406. MOVW R5, 40(R1)
  407. MOVW CTR, R6
  408. MOVW R6, 36(R1)
  409. MOVW XER, R4
  410. MOVW R4, 32(R1)
  411. MOVW CR, R5
  412. MOVW R5, 28(R1)
  413. MOVW SPR(SAVELR), R6 /* LR */
  414. MOVW R6, 24(R1)
  415. /* pad at 20(R1) */
  416. MOVW SPR(SRR0), R0
  417. MOVW R0, 16(R1) /* old PC */
  418. MOVW SPR(SRR1), R0
  419. MOVW R0, 12(R1) /* old status */
  420. MOVW SPR(SAVEXX), R0
  421. MOVW R0, 8(R1) /* cause/vector */
  422. ADD $8, R1, R3 /* Ureg* */
  423. OR $KZERO, R3 /* fix ureg */
  424. STWCCC R3, (R1) /* break any pending reservations */
  425. MOVW $0, R0 /* compiler/linker expect R0 to be zero */
  426. MOVW MSR, R5
  427. OR $(MSR_IR|MSR_DR|MSR_FP|MSR_RI), R5 /* enable MMU */
  428. MOVW R5, SPR(SRR1)
  429. MOVW LR, R31
  430. OR $KZERO, R31 /* return PC in KSEG0 */
  431. MOVW R31, SPR(SRR0)
  432. OR $KZERO, R1 /* fix stack pointer */
  433. RFI /* returns to trap handler */
  434. /*
  435. * restore state from Ureg and return from trap/interrupt
  436. */
  437. TEXT forkret(SB), $0
  438. BR restoreureg
  439. restoreureg:
  440. MOVMW 48(R1), R2 /* r2:r31 */
  441. /* defer R1 */
  442. MOVW 40(R1), R0
  443. MOVW R0, SPR(SAVER0)
  444. MOVW 36(R1), R0
  445. MOVW R0, CTR
  446. MOVW 32(R1), R0
  447. MOVW R0, XER
  448. MOVW 28(R1), R0
  449. MOVW R0, CR /* CR */
  450. MOVW 24(R1), R0
  451. MOVW R0, LR
  452. /* pad, skip */
  453. MOVW 16(R1), R0
  454. MOVW R0, SPR(SRR0) /* old PC */
  455. MOVW 12(R1), R0
  456. MOVW R0, SPR(SRR1) /* old MSR */
  457. /* cause, skip */
  458. MOVW 44(R1), R1 /* old SP */
  459. MOVW SPR(SAVER0), R0
  460. RFI
  461. TEXT fpsave(SB), $0
  462. FMOVD F0, (0*8)(R3)
  463. FMOVD F1, (1*8)(R3)
  464. FMOVD F2, (2*8)(R3)
  465. FMOVD F3, (3*8)(R3)
  466. FMOVD F4, (4*8)(R3)
  467. FMOVD F5, (5*8)(R3)
  468. FMOVD F6, (6*8)(R3)
  469. FMOVD F7, (7*8)(R3)
  470. FMOVD F8, (8*8)(R3)
  471. FMOVD F9, (9*8)(R3)
  472. FMOVD F10, (10*8)(R3)
  473. FMOVD F11, (11*8)(R3)
  474. FMOVD F12, (12*8)(R3)
  475. FMOVD F13, (13*8)(R3)
  476. FMOVD F14, (14*8)(R3)
  477. FMOVD F15, (15*8)(R3)
  478. FMOVD F16, (16*8)(R3)
  479. FMOVD F17, (17*8)(R3)
  480. FMOVD F18, (18*8)(R3)
  481. FMOVD F19, (19*8)(R3)
  482. FMOVD F20, (20*8)(R3)
  483. FMOVD F21, (21*8)(R3)
  484. FMOVD F22, (22*8)(R3)
  485. FMOVD F23, (23*8)(R3)
  486. FMOVD F24, (24*8)(R3)
  487. FMOVD F25, (25*8)(R3)
  488. FMOVD F26, (26*8)(R3)
  489. FMOVD F27, (27*8)(R3)
  490. FMOVD F28, (28*8)(R3)
  491. FMOVD F29, (29*8)(R3)
  492. FMOVD F30, (30*8)(R3)
  493. FMOVD F31, (31*8)(R3)
  494. MOVFL FPSCR, F0
  495. FMOVD F0, (32*8)(R3)
  496. RETURN
  497. TEXT fprestore(SB), $0
  498. FMOVD (32*8)(R3), F0
  499. MOVFL F0, FPSCR
  500. FMOVD (0*8)(R3), F0
  501. FMOVD (1*8)(R3), F1
  502. FMOVD (2*8)(R3), F2
  503. FMOVD (3*8)(R3), F3
  504. FMOVD (4*8)(R3), F4
  505. FMOVD (5*8)(R3), F5
  506. FMOVD (6*8)(R3), F6
  507. FMOVD (7*8)(R3), F7
  508. FMOVD (8*8)(R3), F8
  509. FMOVD (9*8)(R3), F9
  510. FMOVD (10*8)(R3), F10
  511. FMOVD (11*8)(R3), F11
  512. FMOVD (12*8)(R3), F12
  513. FMOVD (13*8)(R3), F13
  514. FMOVD (14*8)(R3), F14
  515. FMOVD (15*8)(R3), F15
  516. FMOVD (16*8)(R3), F16
  517. FMOVD (17*8)(R3), F17
  518. FMOVD (18*8)(R3), F18
  519. FMOVD (19*8)(R3), F19
  520. FMOVD (20*8)(R3), F20
  521. FMOVD (21*8)(R3), F21
  522. FMOVD (22*8)(R3), F22
  523. FMOVD (23*8)(R3), F23
  524. FMOVD (24*8)(R3), F24
  525. FMOVD (25*8)(R3), F25
  526. FMOVD (26*8)(R3), F26
  527. FMOVD (27*8)(R3), F27
  528. FMOVD (28*8)(R3), F28
  529. FMOVD (29*8)(R3), F29
  530. FMOVD (30*8)(R3), F30
  531. FMOVD (31*8)(R3), F31
  532. RETURN