uartaxp.c 18 KB

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  1. /*
  2. * Avanstar Xp pci uart driver
  3. */
  4. #include "u.h"
  5. #include "../port/lib.h"
  6. #include "mem.h"
  7. #include "dat.h"
  8. #include "fns.h"
  9. #include "io.h"
  10. #include "../port/error.h"
  11. #include "uartaxp.i"
  12. typedef struct Cc Cc;
  13. typedef struct Ccb Ccb;
  14. typedef struct Ctlr Ctlr;
  15. typedef struct Gcb Gcb;
  16. /*
  17. * Global Control Block.
  18. * Service Request fields must be accessed using XCHG.
  19. */
  20. struct Gcb {
  21. u16int gcw; /* Global Command Word */
  22. u16int gsw; /* Global Status Word */
  23. u16int gsr; /* Global Service Request */
  24. u16int abs; /* Available Buffer Space */
  25. u16int bt; /* Board Type */
  26. u16int cpv; /* Control Program Version */
  27. u16int ccbn; /* Ccb count */
  28. u16int ccboff; /* Ccb offset */
  29. u16int ccbsz; /* Ccb size */
  30. u16int gcw2; /* Global Command Word 2 */
  31. u16int gsw2; /* Global Status Word 2 */
  32. u16int esr; /* Error Service Request */
  33. u16int isr; /* Input Service Request */
  34. u16int osr; /* Output Service Request */
  35. u16int msr; /* Modem Service Request */
  36. u16int csr; /* Command Service Request */
  37. };
  38. /*
  39. * Channel Control Block.
  40. */
  41. struct Ccb {
  42. u16int br; /* Baud Rate */
  43. u16int df; /* Data Format */
  44. u16int lp; /* Line Protocol */
  45. u16int ibs; /* Input Buffer Size */
  46. u16int obs; /* Output Buffer Size */
  47. u16int ibtr; /* Ib Trigger Rate */
  48. u16int oblw; /* Ob Low Watermark */
  49. u8int ixon[2]; /* IXON characters */
  50. u16int ibhw; /* Ib High Watermark */
  51. u16int iblw; /* Ib Low Watermark */
  52. u16int cc; /* Channel Command */
  53. u16int cs; /* Channel Status */
  54. u16int ibsa; /* Ib Start Addr */
  55. u16int ibea; /* Ib Ending Addr */
  56. u16int obsa; /* Ob Start Addr */
  57. u16int obea; /* Ob Ending Addr */
  58. u16int ibwp; /* Ib write pointer (RO) */
  59. u16int ibrp; /* Ib read pointer (R/W) */
  60. u16int obwp; /* Ob write pointer (R/W) */
  61. u16int obrp; /* Ob read pointer (RO) */
  62. u16int ces; /* Communication Error Status */
  63. u16int bcp; /* Bad Character Pointer */
  64. u16int mc; /* Modem Control */
  65. u16int ms; /* Modem Status */
  66. u16int bs; /* Blocking Status */
  67. u16int crf; /* Character Received Flag */
  68. u8int ixoff[2]; /* IXOFF characters */
  69. u16int cs2; /* Channel Status 2 */
  70. u8int sec[2]; /* Strip/Error Characters */
  71. };
  72. enum { /* br */
  73. Br76800 = 0xFF00,
  74. Br115200 = 0xFF01,
  75. };
  76. enum { /* df */
  77. Db5 = 0x0000, /* Data Bits - 5 bits/byte */
  78. Db6 = 0x0001, /* 6 bits/byte */
  79. Db7 = 0x0002, /* 7 bits/byte */
  80. Db8 = 0x0003, /* 8 bits/byte */
  81. DbMASK = 0x0003,
  82. Sb1 = 0x0000, /* 1 Stop Bit */
  83. Sb2 = 0x0004, /* 2 Stop Bit */
  84. SbMASK = 0x0004,
  85. Np = 0x0000, /* No Parity */
  86. Op = 0x0008, /* Odd Parity */
  87. Ep = 0x0010, /* Even Parity */
  88. Mp = 0x0020, /* Mark Parity */
  89. Sp = 0x0030, /* Space Parity */
  90. PMASK = 0x0038,
  91. Cmn = 0x0000, /* Channel Mode Normal */
  92. Cme = 0x0040, /* CM Echo */
  93. Cmll = 0x0080, /* CM Local Loopback */
  94. Cmrl = 0x00C0, /* CM Remote Loopback */
  95. };
  96. enum { /* lp */
  97. Ixon = 0x0001, /* Obey IXON/IXOFF */
  98. Ixany = 0x0002, /* Any character retarts Tx */
  99. Ixgen = 0x0004, /* Generate IXON/IXOFF */
  100. Cts = 0x0008, /* CTS controls Tx */
  101. Dtr = 0x0010, /* Rx controls DTR */
  102. ½d = 0x0020, /* RTS off during Tx */
  103. Rts = 0x0040, /* generate RTS */
  104. Emcs = 0x0080, /* Enable Modem Control */
  105. Ecs = 0x1000, /* Enable Character Stripping */
  106. Eia422 = 0x2000, /* EIA422 */
  107. };
  108. enum { /* cc */
  109. Ccu = 0x0001, /* Configure Channel and UART */
  110. Cco = 0x0002, /* Configure Channel Only */
  111. Fib = 0x0004, /* Flush Input Buffer */
  112. Fob = 0x0008, /* Flush Output Buffer */
  113. Er = 0x0010, /* Enable Receiver */
  114. Dr = 0x0020, /* Disable Receiver */
  115. Et = 0x0040, /* Enable Transmitter */
  116. Dt = 0x0080, /* Disable Transmitter */
  117. };
  118. enum { /* ces */
  119. Oe = 0x0001, /* Overrun Error */
  120. Pe = 0x0002, /* Parity Error */
  121. Fe = 0x0004, /* Framing Error */
  122. Br = 0x0008, /* Break Received */
  123. };
  124. enum { /* mc */
  125. Adtr = 0x0001, /* Assert DTR */
  126. Arts = 0x0002, /* Assert RTS */
  127. Ab = 0x0010, /* Assert BREAK */
  128. };
  129. enum { /* ms */
  130. Scts = 0x0001, /* Status od CTS */
  131. Sdsr = 0x0002, /* Status of DSR */
  132. Sri = 0x0004, /* Status of RI */
  133. Sdcd = 0x0008, /* Status of DCD */
  134. };
  135. enum { /* bs */
  136. Rd = 0x0001, /* Receiver Disabled */
  137. Td = 0x0002, /* Transmitter Disabled */
  138. Tbxoff = 0x0004, /* Tx Blocked by XOFF */
  139. Tbcts = 0x0008, /* Tx Blocked by CTS */
  140. Rbxoff = 0x0010, /* Rx Blocked by XOFF */
  141. Rbrts = 0x0020, /* Rx Blocked by RTS */
  142. };
  143. enum { /* Local Configuration */
  144. Range = 0x00,
  145. Remap = 0x04,
  146. Region = 0x18,
  147. Mb0 = 0x40, /* Mailbox 0 */
  148. Ldb = 0x60, /* PCI to Local Doorbell */
  149. Pdb = 0x64, /* Local to PCI Doorbell */
  150. Ics = 0x68, /* Interrupt Control/Status */
  151. Mcc = 0x6C, /* Misc. Command and Control */
  152. };
  153. enum { /* Mb0 */
  154. Edcc = 1, /* exec. downloaded code cmd */
  155. Aic = 0x10, /* adapter init'zed correctly */
  156. Cpr = 1ul << 31, /* control program ready */
  157. };
  158. enum { /* Mcc */
  159. Rcr = 1ul << 29, /* reload config. reg.s */
  160. Asr = 1ul << 30, /* pci adapter sw reset */
  161. Lis = 1ul << 31, /* local init status */
  162. };
  163. typedef struct Cc Cc;
  164. typedef struct Ccb Ccb;
  165. typedef struct Ctlr Ctlr;
  166. /*
  167. * Channel Control, one per uart.
  168. * Devuart communicates via the PhysUart functions with
  169. * a Uart* argument. Uart.regs is filled in by this driver
  170. * to point to a Cc, and Cc.ctlr points to the Axp board
  171. * controller.
  172. */
  173. struct Cc {
  174. int uartno;
  175. Ccb* ccb;
  176. Ctlr* ctlr;
  177. Rendez;
  178. Uart;
  179. };
  180. typedef struct Ctlr {
  181. char* name;
  182. Pcidev* pcidev;
  183. int ctlrno;
  184. Ctlr* next;
  185. u32int* reg;
  186. uchar* mem;
  187. Gcb* gcb;
  188. int im; /* interrupt mask */
  189. Cc cc[16];
  190. } Ctlr;
  191. #define csr32r(c, r) (*((c)->reg+((r)/4)))
  192. #define csr32w(c, r, v) (*((c)->reg+((r)/4)) = (v))
  193. static Ctlr* axpctlrhead;
  194. static Ctlr* axpctlrtail;
  195. extern PhysUart axpphysuart;
  196. static int
  197. axpccdone(void* ccb)
  198. {
  199. return !((Ccb*)ccb)->cc; /* hw sets ccb->cc to zero */
  200. }
  201. static void
  202. axpcc(Cc* cc, int cmd)
  203. {
  204. Ccb *ccb;
  205. int timeo;
  206. u16int cs;
  207. ccb = cc->ccb;
  208. ccb->cc = cmd;
  209. if(!cc->ctlr->im)
  210. for(timeo = 0; timeo < 1000000; timeo++){
  211. if(!ccb->cc)
  212. break;
  213. microdelay(1);
  214. }
  215. else
  216. tsleep(cc, axpccdone, ccb, 1000);
  217. cs = ccb->cs;
  218. if(ccb->cc || cs){
  219. print("%s: cmd %#ux didn't terminate: %#ux %#ux\n",
  220. cc->name, cmd, ccb->cc, cs);
  221. if(cc->ctlr->im)
  222. error(Eio);
  223. }
  224. }
  225. static long
  226. axpstatus(Uart* uart, void* buf, long n, long offset)
  227. {
  228. char *p;
  229. Ccb *ccb;
  230. u16int bs, fstat, ms;
  231. ccb = ((Cc*)(uart->regs))->ccb;
  232. p = malloc(READSTR);
  233. bs = ccb->bs;
  234. fstat = ccb->df;
  235. ms = ccb->ms;
  236. snprint(p, READSTR,
  237. "b%d c%d d%d e%d l%d m%d p%c r%d s%d i%d\n"
  238. "dev(%d) type(%d) framing(%d) overruns(%d) "
  239. "berr(%d) serr(%d)%s%s%s%s\n",
  240. uart->baud,
  241. uart->hup_dcd,
  242. ms & Sdsr,
  243. uart->hup_dsr,
  244. (fstat & DbMASK) + 5,
  245. 0,
  246. (fstat & PMASK) ? ((fstat & Ep) == Ep? 'e': 'o'): 'n',
  247. (bs & Rbrts) ? 1 : 0,
  248. (fstat & Sb2) ? 2 : 1,
  249. 0,
  250. uart->dev,
  251. uart->type,
  252. uart->ferr,
  253. uart->oerr,
  254. uart->berr,
  255. uart->serr,
  256. (ms & Scts) ? " cts" : "",
  257. (ms & Sdsr) ? " dsr" : "",
  258. (ms & Sdcd) ? " dcd" : "",
  259. (ms & Sri) ? " ring" : ""
  260. );
  261. n = readstr(offset, buf, n, p);
  262. free(p);
  263. return n;
  264. }
  265. static void
  266. axpfifo(Uart*, int)
  267. {
  268. }
  269. static void
  270. axpdtr(Uart* uart, int on)
  271. {
  272. Ccb *ccb;
  273. u16int mc;
  274. ccb = ((Cc*)(uart->regs))->ccb;
  275. mc = ccb->mc;
  276. if(on)
  277. mc |= Adtr;
  278. else
  279. mc &= ~Adtr;
  280. ccb->mc = mc;
  281. }
  282. /*
  283. * can be called from uartstageinput() during an input interrupt,
  284. * with uart->rlock ilocked or the uart qlocked, sometimes both.
  285. */
  286. static void
  287. axprts(Uart* uart, int on)
  288. {
  289. Ccb *ccb;
  290. u16int mc;
  291. ccb = ((Cc*)(uart->regs))->ccb;
  292. mc = ccb->mc;
  293. if(on)
  294. mc |= Arts;
  295. else
  296. mc &= ~Arts;
  297. ccb->mc = mc;
  298. }
  299. static void
  300. axpmodemctl(Uart* uart, int on)
  301. {
  302. Ccb *ccb;
  303. u16int lp;
  304. ccb = ((Cc*)(uart->regs))->ccb;
  305. ilock(&uart->tlock);
  306. lp = ccb->lp;
  307. if(on){
  308. lp |= Cts|Rts;
  309. lp &= ~Emcs;
  310. uart->cts = ccb->ms & Scts;
  311. }
  312. else{
  313. lp &= ~(Cts|Rts);
  314. lp |= Emcs;
  315. uart->cts = 1;
  316. }
  317. uart->modem = on;
  318. iunlock(&uart->tlock);
  319. ccb->lp = lp;
  320. axpcc(uart->regs, Ccu);
  321. }
  322. static int
  323. axpparity(Uart* uart, int parity)
  324. {
  325. Ccb *ccb;
  326. u16int df;
  327. switch(parity){
  328. default:
  329. return -1;
  330. case 'e':
  331. parity = Ep;
  332. break;
  333. case 'o':
  334. parity = Op;
  335. break;
  336. case 'n':
  337. parity = Np;
  338. break;
  339. }
  340. ccb = ((Cc*)(uart->regs))->ccb;
  341. df = ccb->df & ~PMASK;
  342. ccb->df = df|parity;
  343. axpcc(uart->regs, Ccu);
  344. return 0;
  345. }
  346. static int
  347. axpstop(Uart* uart, int stop)
  348. {
  349. Ccb *ccb;
  350. u16int df;
  351. switch(stop){
  352. default:
  353. return -1;
  354. case 1:
  355. stop = Sb1;
  356. break;
  357. case 2:
  358. stop = Sb2;
  359. break;
  360. }
  361. ccb = ((Cc*)(uart->regs))->ccb;
  362. df = ccb->df & ~SbMASK;
  363. ccb->df = df|stop;
  364. axpcc(uart->regs, Ccu);
  365. return 0;
  366. }
  367. static int
  368. axpbits(Uart* uart, int bits)
  369. {
  370. Ccb *ccb;
  371. u16int df;
  372. bits -= 5;
  373. if(bits < 0 || bits > 3)
  374. return -1;
  375. ccb = ((Cc*)(uart->regs))->ccb;
  376. df = ccb->df & ~DbMASK;
  377. ccb->df = df|bits;
  378. axpcc(uart->regs, Ccu);
  379. return 0;
  380. }
  381. static int
  382. axpbaud(Uart* uart, int baud)
  383. {
  384. Ccb *ccb;
  385. int i, ibtr;
  386. /*
  387. * Set baud rate (high rates are special - only 16 bits).
  388. */
  389. if(baud <= 0)
  390. return -1;
  391. uart->baud = baud;
  392. ccb = ((Cc*)(uart->regs))->ccb;
  393. switch(baud){
  394. default:
  395. ccb->br = baud;
  396. break;
  397. case 76800:
  398. ccb->br = Br76800;
  399. break;
  400. case 115200:
  401. ccb->br = Br115200;
  402. break;
  403. }
  404. /*
  405. * Set trigger level to about 50 per second.
  406. */
  407. ibtr = baud/500;
  408. i = (ccb->ibea - ccb->ibsa)/2;
  409. if(ibtr > i)
  410. ibtr = i;
  411. ccb->ibtr = ibtr;
  412. axpcc(uart->regs, Ccu);
  413. return 0;
  414. }
  415. static void
  416. axpbreak(Uart* uart, int ms)
  417. {
  418. Ccb *ccb;
  419. u16int mc;
  420. /*
  421. * Send a break.
  422. */
  423. if(ms <= 0)
  424. ms = 200;
  425. ccb = ((Cc*)(uart->regs))->ccb;
  426. mc = ccb->mc;
  427. ccb->mc = Ab|mc;
  428. tsleep(&up->sleep, return0, 0, ms);
  429. ccb->mc = mc & ~Ab;
  430. }
  431. /* only called from interrupt service */
  432. static void
  433. axpmc(Cc* cc)
  434. {
  435. int old;
  436. Ccb *ccb;
  437. u16int ms;
  438. ccb = cc->ccb;
  439. ms = ccb->ms;
  440. if(ms & Scts){
  441. ilock(&cc->tlock);
  442. old = cc->cts;
  443. cc->cts = ms & Scts;
  444. if(old == 0 && cc->cts)
  445. cc->ctsbackoff = 2;
  446. iunlock(&cc->tlock);
  447. }
  448. if(ms & Sdsr){
  449. old = ms & Sdsr;
  450. if(cc->hup_dsr && cc->dsr && !old)
  451. cc->dohup = 1;
  452. cc->dsr = old;
  453. }
  454. if(ms & Sdcd){
  455. old = ms & Sdcd;
  456. if(cc->hup_dcd && cc->dcd && !old)
  457. cc->dohup = 1;
  458. cc->dcd = old;
  459. }
  460. }
  461. /* called from uartkick() with uart->tlock ilocked */
  462. static void
  463. axpkick(Uart* uart)
  464. {
  465. Cc *cc;
  466. Ccb *ccb;
  467. uchar *ep, *mem, *rp, *wp, *bp;
  468. if(uart->cts == 0 || uart->blocked)
  469. return;
  470. cc = uart->regs;
  471. ccb = cc->ccb;
  472. mem = (uchar*)cc->ctlr->gcb;
  473. bp = mem + ccb->obsa;
  474. rp = mem + ccb->obrp;
  475. wp = mem + ccb->obwp;
  476. ep = mem + ccb->obea;
  477. while(wp != rp-1 && (rp != bp || wp != ep)){
  478. /*
  479. * if we've exhausted the uart's output buffer,
  480. * ask for more from the output queue, and quit if there
  481. * isn't any.
  482. */
  483. if(uart->op >= uart->oe && uartstageoutput(uart) == 0)
  484. break;
  485. *wp++ = *(uart->op++);
  486. if(wp > ep)
  487. wp = bp;
  488. ccb->obwp = wp - mem;
  489. }
  490. }
  491. /* only called from interrupt service */
  492. static void
  493. axprecv(Cc* cc)
  494. {
  495. Ccb *ccb;
  496. uchar *ep, *mem, *rp, *wp;
  497. ccb = cc->ccb;
  498. mem = (uchar*)cc->ctlr->gcb;
  499. rp = mem + ccb->ibrp;
  500. wp = mem + ccb->ibwp;
  501. ep = mem + ccb->ibea;
  502. while(rp != wp){
  503. uartrecv(cc, *rp++); /* ilocks cc->tlock */
  504. if(rp > ep)
  505. rp = mem + ccb->ibsa;
  506. ccb->ibrp = rp - mem;
  507. }
  508. }
  509. static void
  510. axpinterrupt(Ureg*, void* arg)
  511. {
  512. int work;
  513. Cc *cc;
  514. Ctlr *ctlr;
  515. u32int ics;
  516. u16int r, sr;
  517. work = 0;
  518. ctlr = arg;
  519. ics = csr32r(ctlr, Ics);
  520. if(ics & 0x0810C000)
  521. print("%s: unexpected interrupt %#ux\n", ctlr->name, ics);
  522. if(!(ics & 0x00002000)) {
  523. /* we get a steady stream of these on consoles */
  524. // print("%s: non-doorbell interrupt\n", ctlr->name);
  525. ctlr->gcb->gcw2 = 0x0001; /* set Gintack */
  526. return;
  527. }
  528. // while(work to do){
  529. cc = ctlr->cc;
  530. for(sr = xchgw(&ctlr->gcb->isr, 0); sr != 0; sr >>= 1){
  531. if(sr & 0x0001)
  532. work++, axprecv(cc);
  533. cc++;
  534. }
  535. cc = ctlr->cc;
  536. for(sr = xchgw(&ctlr->gcb->osr, 0); sr != 0; sr >>= 1){
  537. if(sr & 0x0001)
  538. work++, uartkick(&cc->Uart);
  539. cc++;
  540. }
  541. cc = ctlr->cc;
  542. for(sr = xchgw(&ctlr->gcb->csr, 0); sr != 0; sr >>= 1){
  543. if(sr & 0x0001)
  544. work++, wakeup(cc);
  545. cc++;
  546. }
  547. cc = ctlr->cc;
  548. for(sr = xchgw(&ctlr->gcb->msr, 0); sr != 0; sr >>= 1){
  549. if(sr & 0x0001)
  550. work++, axpmc(cc);
  551. cc++;
  552. }
  553. cc = ctlr->cc;
  554. for(sr = xchgw(&ctlr->gcb->esr, 0); sr != 0; sr >>= 1){
  555. if(sr & 0x0001){
  556. r = cc->ccb->ms;
  557. if(r & Oe)
  558. cc->oerr++;
  559. if(r & Pe)
  560. cc->perr++;
  561. if(r & Fe)
  562. cc->ferr++;
  563. if (r & (Oe|Pe|Fe))
  564. work++;
  565. }
  566. cc++;
  567. }
  568. // }
  569. /* only meaningful if we don't share the irq */
  570. if (0 && !work)
  571. print("%s: interrupt with no work\n", ctlr->name);
  572. csr32w(ctlr, Pdb, 1); /* clear doorbell interrupt */
  573. ctlr->gcb->gcw2 = 0x0001; /* set Gintack */
  574. }
  575. static void
  576. axpdisable(Uart* uart)
  577. {
  578. Cc *cc;
  579. u16int lp;
  580. Ctlr *ctlr;
  581. /*
  582. * Turn off DTR and RTS, disable interrupts.
  583. */
  584. (*uart->phys->dtr)(uart, 0);
  585. (*uart->phys->rts)(uart, 0);
  586. cc = uart->regs;
  587. lp = cc->ccb->lp;
  588. cc->ccb->lp = Emcs|lp;
  589. axpcc(cc, Dt|Dr|Fob|Fib|Ccu);
  590. /*
  591. * The Uart is qlocked.
  592. */
  593. ctlr = cc->ctlr;
  594. ctlr->im &= ~(1<<cc->uartno);
  595. if(ctlr->im == 0)
  596. intrdisable(ctlr->pcidev->intl, axpinterrupt, ctlr,
  597. ctlr->pcidev->tbdf, ctlr->name);
  598. }
  599. static void
  600. axpenable(Uart* uart, int ie)
  601. {
  602. Cc *cc;
  603. Ctlr *ctlr;
  604. u16int lp;
  605. cc = uart->regs;
  606. ctlr = cc->ctlr;
  607. /*
  608. * Enable interrupts and turn on DTR and RTS.
  609. * Be careful if this is called to set up a polled serial line
  610. * early on not to try to enable interrupts as interrupt-
  611. * -enabling mechanisms might not be set up yet.
  612. */
  613. if(ie){
  614. /*
  615. * The Uart is qlocked.
  616. */
  617. if(ctlr->im == 0){
  618. intrenable(ctlr->pcidev->intl, axpinterrupt, ctlr,
  619. ctlr->pcidev->tbdf, ctlr->name);
  620. csr32w(ctlr, Ics, 0x00031F00);
  621. csr32w(ctlr, Pdb, 1);
  622. ctlr->gcb->gcw2 = 1;
  623. }
  624. ctlr->im |= 1<<cc->uartno;
  625. }
  626. (*uart->phys->dtr)(uart, 1);
  627. (*uart->phys->rts)(uart, 1);
  628. /*
  629. * Make sure we control RTS, DTR and break.
  630. */
  631. lp = cc->ccb->lp;
  632. cc->ccb->lp = Emcs|lp;
  633. cc->ccb->oblw = 64;
  634. axpcc(cc, Et|Er|Ccu);
  635. }
  636. static void*
  637. axpdealloc(Ctlr* ctlr)
  638. {
  639. int i;
  640. for(i = 0; i < 16; i++){
  641. if(ctlr->cc[i].name != nil)
  642. free(ctlr->cc[i].name);
  643. }
  644. if(ctlr->reg != nil)
  645. vunmap(ctlr->reg, ctlr->pcidev->mem[0].size);
  646. if(ctlr->mem != nil)
  647. vunmap(ctlr->mem, ctlr->pcidev->mem[2].size);
  648. if(ctlr->name != nil)
  649. free(ctlr->name);
  650. free(ctlr);
  651. return nil;
  652. }
  653. static Uart*
  654. axpalloc(int ctlrno, Pcidev* pcidev)
  655. {
  656. Cc *cc;
  657. uchar *p;
  658. Ctlr *ctlr;
  659. void *addr;
  660. char name[64];
  661. u32int bar, r;
  662. int i, n, timeo;
  663. ctlr = malloc(sizeof(Ctlr));
  664. seprint(name, name+sizeof(name), "uartaxp%d", ctlrno);
  665. kstrdup(&ctlr->name, name);
  666. ctlr->pcidev = pcidev;
  667. ctlr->ctlrno = ctlrno;
  668. /*
  669. * Access to runtime registers.
  670. */
  671. bar = pcidev->mem[0].bar;
  672. if((addr = vmap(bar & ~0x0F, pcidev->mem[0].size)) == 0){
  673. print("%s: can't map registers at %#ux\n", ctlr->name, bar);
  674. return axpdealloc(ctlr);
  675. }
  676. ctlr->reg = addr;
  677. print("%s: port 0x%ux irq %d ", ctlr->name, bar, pcidev->intl);
  678. /*
  679. * Local address space 0.
  680. */
  681. bar = pcidev->mem[2].bar;
  682. if((addr = vmap(bar & ~0x0F, pcidev->mem[2].size)) == 0){
  683. print("%s: can't map memory at %#ux\n", ctlr->name, bar);
  684. return axpdealloc(ctlr);
  685. }
  686. ctlr->mem = addr;
  687. ctlr->gcb = (Gcb*)(ctlr->mem+0x10000);
  688. print("mem 0x%ux size %d: ", bar, pcidev->mem[2].size);
  689. /*
  690. * Toggle the software reset and wait for
  691. * the adapter local init status to indicate done.
  692. *
  693. * The two 'delay(100)'s below are important,
  694. * without them the board seems to become confused
  695. * (perhaps it needs some 'quiet time' because the
  696. * timeout loops are not sufficient in themselves).
  697. */
  698. r = csr32r(ctlr, Mcc);
  699. csr32w(ctlr, Mcc, r|Asr);
  700. microdelay(1);
  701. csr32w(ctlr, Mcc, r&~Asr);
  702. delay(100);
  703. for(timeo = 0; timeo < 100000; timeo++){
  704. if(csr32r(ctlr, Mcc) & Lis)
  705. break;
  706. microdelay(1);
  707. }
  708. if(!(csr32r(ctlr, Mcc) & Lis)){
  709. print("%s: couldn't reset\n", ctlr->name);
  710. return axpdealloc(ctlr);
  711. }
  712. print("downloading...");
  713. /*
  714. * Copy the control programme to the card memory.
  715. * The card's i960 control structures live at 0xD000.
  716. */
  717. if(sizeof(uartaxpcp) > 0xD000){
  718. print("%s: control programme too big\n", ctlr->name);
  719. return axpdealloc(ctlr);
  720. }
  721. /* TODO: is this right for more than 1 card? devastar does the same */
  722. csr32w(ctlr, Remap, 0xA0000001);
  723. for(i = 0; i < sizeof(uartaxpcp); i++)
  724. ctlr->mem[i] = uartaxpcp[i];
  725. /*
  726. * Execute downloaded code and wait for it
  727. * to signal ready.
  728. */
  729. csr32w(ctlr, Mb0, Edcc);
  730. delay(100);
  731. /* the manual says to wait for Cpr for 1 second */
  732. for(timeo = 0; timeo < 10000; timeo++){
  733. if(csr32r(ctlr, Mb0) & Cpr)
  734. break;
  735. microdelay(100);
  736. }
  737. if(!(csr32r(ctlr, Mb0) & Cpr)){
  738. print("control programme not ready; Mb0 %#ux\n",
  739. csr32r(ctlr, Mb0));
  740. print("%s: distribution panel not connected or card not fully seated?\n",
  741. ctlr->name);
  742. return axpdealloc(ctlr);
  743. }
  744. print("\n");
  745. n = ctlr->gcb->ccbn;
  746. if(ctlr->gcb->bt != 0x12 || n > 16){
  747. print("%s: wrong board type %#ux, %d channels\n",
  748. ctlr->name, ctlr->gcb->bt, ctlr->gcb->ccbn);
  749. return axpdealloc(ctlr);
  750. }
  751. p = ((uchar*)ctlr->gcb) + ctlr->gcb->ccboff;
  752. for(i = 0; i < n; i++){
  753. cc = &ctlr->cc[i];
  754. cc->ccb = (Ccb*)p;
  755. p += ctlr->gcb->ccbsz;
  756. cc->uartno = i;
  757. cc->ctlr = ctlr;
  758. cc->regs = cc; /* actually Uart->regs */
  759. seprint(name, name+sizeof(name), "uartaxp%d%2.2d", ctlrno, i);
  760. kstrdup(&cc->name, name);
  761. cc->freq = 0;
  762. cc->bits = 8;
  763. cc->stop = 1;
  764. cc->parity = 'n';
  765. cc->baud = 9600;
  766. cc->phys = &axpphysuart;
  767. cc->console = 0;
  768. cc->special = 0;
  769. cc->next = &ctlr->cc[i+1];
  770. }
  771. ctlr->cc[n-1].next = nil;
  772. ctlr->next = nil;
  773. if(axpctlrhead != nil)
  774. axpctlrtail->next = ctlr;
  775. else
  776. axpctlrhead = ctlr;
  777. axpctlrtail = ctlr;
  778. return ctlr->cc;
  779. }
  780. static Uart*
  781. axppnp(void)
  782. {
  783. Pcidev *p;
  784. int ctlrno;
  785. Uart *head, *tail, *uart;
  786. /*
  787. * Loop through all PCI devices looking for simple serial
  788. * controllers (ccrb == 0x07) and configure the ones which
  789. * are familiar.
  790. */
  791. head = tail = nil;
  792. ctlrno = 0;
  793. for(p = pcimatch(nil, 0, 0); p != nil; p = pcimatch(p, 0, 0)){
  794. if(p->ccrb != 0x07)
  795. continue;
  796. switch((p->did<<16)|p->vid){
  797. default:
  798. continue;
  799. case (0x6001<<16)|0x114F: /* AvanstarXp */
  800. if((uart = axpalloc(ctlrno, p)) == nil)
  801. continue;
  802. break;
  803. }
  804. if(head != nil)
  805. tail->next = uart;
  806. else
  807. head = uart;
  808. for(tail = uart; tail->next != nil; tail = tail->next)
  809. ;
  810. ctlrno++;
  811. }
  812. return head;
  813. }
  814. PhysUart axpphysuart = {
  815. .name = "AvanstarXp",
  816. .pnp = axppnp,
  817. .enable = axpenable,
  818. .disable = axpdisable,
  819. .kick = axpkick,
  820. .dobreak = axpbreak,
  821. .baud = axpbaud,
  822. .bits = axpbits,
  823. .stop = axpstop,
  824. .parity = axpparity,
  825. .modemctl = axpmodemctl,
  826. .rts = axprts,
  827. .dtr = axpdtr,
  828. .status = axpstatus,
  829. .fifo = axpfifo,
  830. .getc = nil,
  831. .putc = nil,
  832. };