sdata.c 52 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "ureg.h"
  8. #include "../port/error.h"
  9. #include "../port/sd.h"
  10. #define HOWMANY(x, y) (((x)+((y)-1))/(y))
  11. #define ROUNDUP(x, y) (HOWMANY((x), (y))*(y))
  12. extern SDifc sdataifc;
  13. enum {
  14. DbgCONFIG = 0x0001, /* detected drive config info */
  15. DbgIDENTIFY = 0x0002, /* detected drive identify info */
  16. DbgSTATE = 0x0004, /* dump state on panic */
  17. DbgPROBE = 0x0008, /* trace device probing */
  18. DbgDEBUG = 0x0080, /* the current problem... */
  19. DbgINL = 0x0100, /* That Inil20+ message we hate */
  20. Dbg48BIT = 0x0200, /* 48-bit LBA */
  21. DbgBsy = 0x0400, /* interrupt but Bsy (shared IRQ) */
  22. };
  23. #define DEBUG (DbgDEBUG|DbgSTATE)
  24. enum { /* I/O ports */
  25. Data = 0,
  26. Error = 1, /* (read) */
  27. Features = 1, /* (write) */
  28. Count = 2, /* sector count<7-0>, sector count<15-8> */
  29. Ir = 2, /* interrupt reason (PACKET) */
  30. Sector = 3, /* sector number */
  31. Lbalo = 3, /* LBA<7-0>, LBA<31-24> */
  32. Cyllo = 4, /* cylinder low */
  33. Bytelo = 4, /* byte count low (PACKET) */
  34. Lbamid = 4, /* LBA<15-8>, LBA<39-32> */
  35. Cylhi = 5, /* cylinder high */
  36. Bytehi = 5, /* byte count hi (PACKET) */
  37. Lbahi = 5, /* LBA<23-16>, LBA<47-40> */
  38. Dh = 6, /* Device/Head, LBA<27-24> */
  39. Status = 7, /* (read) */
  40. Command = 7, /* (write) */
  41. As = 2, /* Alternate Status (read) */
  42. Dc = 2, /* Device Control (write) */
  43. };
  44. enum { /* Error */
  45. Med = 0x01, /* Media error */
  46. Ili = 0x01, /* command set specific (PACKET) */
  47. Nm = 0x02, /* No Media */
  48. Eom = 0x02, /* command set specific (PACKET) */
  49. Abrt = 0x04, /* Aborted command */
  50. Mcr = 0x08, /* Media Change Request */
  51. Idnf = 0x10, /* no user-accessible address */
  52. Mc = 0x20, /* Media Change */
  53. Unc = 0x40, /* Uncorrectable data error */
  54. Wp = 0x40, /* Write Protect */
  55. Icrc = 0x80, /* Interface CRC error */
  56. };
  57. enum { /* Features */
  58. Dma = 0x01, /* data transfer via DMA (PACKET) */
  59. Ovl = 0x02, /* command overlapped (PACKET) */
  60. };
  61. enum { /* Interrupt Reason */
  62. Cd = 0x01, /* Command/Data */
  63. Io = 0x02, /* I/O direction */
  64. Rel = 0x04, /* Bus Release */
  65. };
  66. enum { /* Device/Head */
  67. Dev0 = 0xA0, /* Master */
  68. Dev1 = 0xB0, /* Slave */
  69. Lba = 0x40, /* LBA mode */
  70. };
  71. enum { /* Status, Alternate Status */
  72. Err = 0x01, /* Error */
  73. Chk = 0x01, /* Check error (PACKET) */
  74. Drq = 0x08, /* Data Request */
  75. Dsc = 0x10, /* Device Seek Complete */
  76. Serv = 0x10, /* Service */
  77. Df = 0x20, /* Device Fault */
  78. Dmrd = 0x20, /* DMA ready (PACKET) */
  79. Drdy = 0x40, /* Device Ready */
  80. Bsy = 0x80, /* Busy */
  81. };
  82. enum { /* Command */
  83. Cnop = 0x00, /* NOP */
  84. Cdr = 0x08, /* Device Reset */
  85. Crs = 0x20, /* Read Sectors */
  86. Crs48 = 0x24, /* Read Sectors Ext */
  87. Crd48 = 0x25, /* Read w/ DMA Ext */
  88. Crdq48 = 0x26, /* Read w/ DMA Queued Ext */
  89. Crsm48 = 0x29, /* Read Multiple Ext */
  90. Cws = 0x30, /* Write Sectors */
  91. Cws48 = 0x34, /* Write Sectors Ext */
  92. Cwd48 = 0x35, /* Write w/ DMA Ext */
  93. Cwdq48 = 0x36, /* Write w/ DMA Queued Ext */
  94. Cwsm48 = 0x39, /* Write Multiple Ext */
  95. Cedd = 0x90, /* Execute Device Diagnostics */
  96. Cpkt = 0xA0, /* Packet */
  97. Cidpkt = 0xA1, /* Identify Packet Device */
  98. Crsm = 0xC4, /* Read Multiple */
  99. Cwsm = 0xC5, /* Write Multiple */
  100. Csm = 0xC6, /* Set Multiple */
  101. Crdq = 0xC7, /* Read DMA queued */
  102. Crd = 0xC8, /* Read DMA */
  103. Cwd = 0xCA, /* Write DMA */
  104. Cwdq = 0xCC, /* Write DMA queued */
  105. Cstandby = 0xE2, /* Standby */
  106. Cid = 0xEC, /* Identify Device */
  107. Csf = 0xEF, /* Set Features */
  108. };
  109. enum { /* Device Control */
  110. Nien = 0x02, /* (not) Interrupt Enable */
  111. Srst = 0x04, /* Software Reset */
  112. Hob = 0x80, /* High Order Bit [sic] */
  113. };
  114. enum { /* PCI Configuration Registers */
  115. Bmiba = 0x20, /* Bus Master Interface Base Address */
  116. Idetim = 0x40, /* IE Timing */
  117. Sidetim = 0x44, /* Slave IE Timing */
  118. Udmactl = 0x48, /* Ultra DMA/33 Control */
  119. Udmatim = 0x4A, /* Ultra DMA/33 Timing */
  120. };
  121. enum { /* Bus Master IDE I/O Ports */
  122. Bmicx = 0, /* Command */
  123. Bmisx = 2, /* Status */
  124. Bmidtpx = 4, /* Descriptor Table Pointer */
  125. };
  126. enum { /* Bmicx */
  127. Ssbm = 0x01, /* Start/Stop Bus Master */
  128. Rwcon = 0x08, /* Read/Write Control */
  129. };
  130. enum { /* Bmisx */
  131. Bmidea = 0x01, /* Bus Master IDE Active */
  132. Idedmae = 0x02, /* IDE DMA Error (R/WC) */
  133. Ideints = 0x04, /* IDE Interrupt Status (R/WC) */
  134. Dma0cap = 0x20, /* Drive 0 DMA Capable */
  135. Dma1cap = 0x40, /* Drive 0 DMA Capable */
  136. };
  137. enum { /* Physical Region Descriptor */
  138. PrdEOT = 0x80000000, /* End of Transfer */
  139. };
  140. enum { /* offsets into the identify info. */
  141. Iconfig = 0, /* general configuration */
  142. Ilcyl = 1, /* logical cylinders */
  143. Ilhead = 3, /* logical heads */
  144. Ilsec = 6, /* logical sectors per logical track */
  145. Iserial = 10, /* serial number */
  146. Ifirmware = 23, /* firmware revision */
  147. Imodel = 27, /* model number */
  148. Imaxrwm = 47, /* max. read/write multiple sectors */
  149. Icapabilities = 49, /* capabilities */
  150. Istandby = 50, /* device specific standby timer */
  151. Ipiomode = 51, /* PIO data transfer mode number */
  152. Ivalid = 53,
  153. Iccyl = 54, /* cylinders if (valid&0x01) */
  154. Ichead = 55, /* heads if (valid&0x01) */
  155. Icsec = 56, /* sectors if (valid&0x01) */
  156. Iccap = 57, /* capacity if (valid&0x01) */
  157. Irwm = 59, /* read/write multiple */
  158. Ilba = 60, /* LBA size */
  159. Imwdma = 63, /* multiword DMA mode */
  160. Iapiomode = 64, /* advanced PIO modes supported */
  161. Iminmwdma = 65, /* min. multiword DMA cycle time */
  162. Irecmwdma = 66, /* rec. multiword DMA cycle time */
  163. Iminpio = 67, /* min. PIO cycle w/o flow control */
  164. Iminiordy = 68, /* min. PIO cycle with IORDY */
  165. Ipcktbr = 71, /* time from PACKET to bus release */
  166. Iserbsy = 72, /* time from SERVICE to !Bsy */
  167. Iqdepth = 75, /* max. queue depth */
  168. Imajor = 80, /* major version number */
  169. Iminor = 81, /* minor version number */
  170. Icsfs = 82, /* command set/feature supported */
  171. Icsfe = 85, /* command set/feature enabled */
  172. Iudma = 88, /* ultra DMA mode */
  173. Ierase = 89, /* time for security erase */
  174. Ieerase = 90, /* time for enhanced security erase */
  175. Ipower = 91, /* current advanced power management */
  176. Ilba48 = 100, /* 48-bit LBA size (64 bits in 100-103) */
  177. Irmsn = 127, /* removable status notification */
  178. Isecstat = 128, /* security status */
  179. Icfapwr = 160, /* CFA power mode */
  180. Imediaserial = 176, /* current media serial number */
  181. Icksum = 255, /* checksum */
  182. };
  183. enum { /* bit masks for config identify info */
  184. Mpktsz = 0x0003, /* packet command size */
  185. Mincomplete = 0x0004, /* incomplete information */
  186. Mdrq = 0x0060, /* DRQ type */
  187. Mrmdev = 0x0080, /* device is removable */
  188. Mtype = 0x1F00, /* device type */
  189. Mproto = 0x8000, /* command protocol */
  190. };
  191. enum { /* bit masks for capabilities identify info */
  192. Mdma = 0x0100, /* DMA supported */
  193. Mlba = 0x0200, /* LBA supported */
  194. Mnoiordy = 0x0400, /* IORDY may be disabled */
  195. Miordy = 0x0800, /* IORDY supported */
  196. Msoftrst = 0x1000, /* needs soft reset when Bsy */
  197. Mstdby = 0x2000, /* standby supported */
  198. Mqueueing = 0x4000, /* queueing overlap supported */
  199. Midma = 0x8000, /* interleaved DMA supported */
  200. };
  201. enum { /* bit masks for supported/enabled features */
  202. Msmart = 0x0001,
  203. Msecurity = 0x0002,
  204. Mrmmedia = 0x0004,
  205. Mpwrmgmt = 0x0008,
  206. Mpkt = 0x0010,
  207. Mwcache = 0x0020,
  208. Mlookahead = 0x0040,
  209. Mrelirq = 0x0080,
  210. Msvcirq = 0x0100,
  211. Mreset = 0x0200,
  212. Mprotected = 0x0400,
  213. Mwbuf = 0x1000,
  214. Mrbuf = 0x2000,
  215. Mnop = 0x4000,
  216. Mmicrocode = 0x0001,
  217. Mqueued = 0x0002,
  218. Mcfa = 0x0004,
  219. Mapm = 0x0008,
  220. Mnotify = 0x0010,
  221. Mstandby = 0x0020,
  222. Mspinup = 0x0040,
  223. Mmaxsec = 0x0100,
  224. Mautoacoustic = 0x0200,
  225. Maddr48 = 0x0400,
  226. Mdevconfov = 0x0800,
  227. Mflush = 0x1000,
  228. Mflush48 = 0x2000,
  229. Msmarterror = 0x0001,
  230. Msmartselftest = 0x0002,
  231. Mmserial = 0x0004,
  232. Mmpassthru = 0x0008,
  233. Mlogging = 0x0020,
  234. };
  235. typedef struct Ctlr Ctlr;
  236. typedef struct Drive Drive;
  237. typedef struct Prd { /* Physical Region Descriptor */
  238. ulong pa; /* Physical Base Address */
  239. int count;
  240. } Prd;
  241. enum {
  242. BMspan = 64*1024, /* must be power of 2 <= 64*1024 */
  243. Nprd = SDmaxio/BMspan+2,
  244. };
  245. typedef struct Ctlr {
  246. int cmdport;
  247. int ctlport;
  248. int irq;
  249. int tbdf;
  250. int bmiba; /* bus master interface base address */
  251. int maxio; /* sector count transfer maximum */
  252. int span; /* don't span this boundary with dma */
  253. Pcidev* pcidev;
  254. void (*ienable)(Ctlr*);
  255. void (*idisable)(Ctlr*);
  256. SDev* sdev;
  257. Drive* drive[2];
  258. Prd* prdt; /* physical region descriptor table */
  259. QLock; /* current command */
  260. Drive* curdrive;
  261. int command; /* last command issued (debugging) */
  262. Rendez;
  263. int done;
  264. Lock; /* register access */
  265. } Ctlr;
  266. typedef struct Drive {
  267. Ctlr* ctlr;
  268. int dev;
  269. ushort info[256];
  270. int c; /* cylinder */
  271. int h; /* head */
  272. int s; /* sector */
  273. vlong sectors; /* total */
  274. int secsize; /* sector size */
  275. int dma; /* DMA R/W possible */
  276. int dmactl;
  277. int rwm; /* read/write multiple possible */
  278. int rwmctl;
  279. int pkt; /* PACKET device, length of pktcmd */
  280. uchar pktcmd[16];
  281. int pktdma; /* this PACKET command using dma */
  282. uchar sense[18];
  283. uchar inquiry[48];
  284. QLock; /* drive access */
  285. int command; /* current command */
  286. int write;
  287. uchar* data;
  288. int dlen;
  289. uchar* limit;
  290. int count; /* sectors */
  291. int block; /* R/W bytes per block */
  292. int status;
  293. int error;
  294. int flags; /* internal flags */
  295. } Drive;
  296. enum { /* internal flags */
  297. Lba48 = 0x1, /* LBA48 mode */
  298. Lba48always = 0x2, /* ... */
  299. };
  300. static void
  301. pc87415ienable(Ctlr* ctlr)
  302. {
  303. Pcidev *p;
  304. int x;
  305. p = ctlr->pcidev;
  306. if(p == nil)
  307. return;
  308. x = pcicfgr32(p, 0x40);
  309. if(ctlr->cmdport == p->mem[0].bar)
  310. x &= ~0x00000100;
  311. else
  312. x &= ~0x00000200;
  313. pcicfgw32(p, 0x40, x);
  314. }
  315. static void
  316. atadumpstate(Drive* drive, uchar* cmd, vlong lba, int count)
  317. {
  318. Prd *prd;
  319. Pcidev *p;
  320. Ctlr *ctlr;
  321. int i, bmiba;
  322. if(!(DEBUG & DbgSTATE)){
  323. USED(drive, cmd, lba, count);
  324. return;
  325. }
  326. ctlr = drive->ctlr;
  327. print("command %2.2uX\n", ctlr->command);
  328. print("data %8.8p limit %8.8p dlen %d status %uX error %uX\n",
  329. drive->data, drive->limit, drive->dlen,
  330. drive->status, drive->error);
  331. if(cmd != nil){
  332. print("lba %d -> %lld, count %d -> %d (%d)\n",
  333. (cmd[2]<<24)|(cmd[3]<<16)|(cmd[4]<<8)|cmd[5], lba,
  334. (cmd[7]<<8)|cmd[8], count, drive->count);
  335. }
  336. if(!(inb(ctlr->ctlport+As) & Bsy)){
  337. for(i = 1; i < 7; i++)
  338. print(" 0x%2.2uX", inb(ctlr->cmdport+i));
  339. print(" 0x%2.2uX\n", inb(ctlr->ctlport+As));
  340. }
  341. if(drive->command == Cwd || drive->command == Crd){
  342. bmiba = ctlr->bmiba;
  343. prd = ctlr->prdt;
  344. print("bmicx %2.2uX bmisx %2.2uX prdt %8.8p\n",
  345. inb(bmiba+Bmicx), inb(bmiba+Bmisx), prd);
  346. for(;;){
  347. print("pa 0x%8.8luX count %8.8uX\n",
  348. prd->pa, prd->count);
  349. if(prd->count & PrdEOT)
  350. break;
  351. prd++;
  352. }
  353. }
  354. if(ctlr->pcidev && ctlr->pcidev->vid == 0x8086){
  355. p = ctlr->pcidev;
  356. print("0x40: %4.4uX 0x42: %4.4uX",
  357. pcicfgr16(p, 0x40), pcicfgr16(p, 0x42));
  358. print("0x48: %2.2uX\n", pcicfgr8(p, 0x48));
  359. print("0x4A: %4.4uX\n", pcicfgr16(p, 0x4A));
  360. }
  361. }
  362. static int
  363. atadebug(int cmdport, int ctlport, char* fmt, ...)
  364. {
  365. int i, n;
  366. va_list arg;
  367. char buf[PRINTSIZE];
  368. if(!(DEBUG & DbgPROBE)){
  369. USED(cmdport, ctlport, fmt);
  370. return 0;
  371. }
  372. va_start(arg, fmt);
  373. n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;
  374. va_end(arg);
  375. if(cmdport){
  376. if(buf[n-1] == '\n')
  377. n--;
  378. n += snprint(buf+n, PRINTSIZE-n, " ataregs 0x%uX:",
  379. cmdport);
  380. for(i = Features; i < Command; i++)
  381. n += snprint(buf+n, PRINTSIZE-n, " 0x%2.2uX",
  382. inb(cmdport+i));
  383. if(ctlport)
  384. n += snprint(buf+n, PRINTSIZE-n, " 0x%2.2uX",
  385. inb(ctlport+As));
  386. n += snprint(buf+n, PRINTSIZE-n, "\n");
  387. }
  388. putstrn(buf, n);
  389. return n;
  390. }
  391. static int
  392. ataready(int cmdport, int ctlport, int dev, int reset, int ready, int micro)
  393. {
  394. int as;
  395. atadebug(cmdport, ctlport, "ataready: dev %uX reset %uX ready %uX",
  396. dev, reset, ready);
  397. for(;;){
  398. /*
  399. * Wait for the controller to become not busy and
  400. * possibly for a status bit to become true (usually
  401. * Drdy). Must change to the appropriate device
  402. * register set if necessary before testing for ready.
  403. * Always run through the loop at least once so it
  404. * can be used as a test for !Bsy.
  405. */
  406. as = inb(ctlport+As);
  407. if(as & reset){
  408. /* nothing to do */
  409. }
  410. else if(dev){
  411. outb(cmdport+Dh, dev);
  412. dev = 0;
  413. }
  414. else if(ready == 0 || (as & ready)){
  415. atadebug(0, 0, "ataready: %d 0x%2.2uX\n", micro, as);
  416. return as;
  417. }
  418. if(micro-- <= 0){
  419. atadebug(0, 0, "ataready: %d 0x%2.2uX\n", micro, as);
  420. break;
  421. }
  422. microdelay(1);
  423. }
  424. atadebug(cmdport, ctlport, "ataready: timeout");
  425. return -1;
  426. }
  427. /*
  428. static int
  429. atacsf(Drive* drive, vlong csf, int supported)
  430. {
  431. ushort *info;
  432. int cmdset, i, x;
  433. if(supported)
  434. info = &drive->info[Icsfs];
  435. else
  436. info = &drive->info[Icsfe];
  437. for(i = 0; i < 3; i++){
  438. x = (csf>>(16*i)) & 0xFFFF;
  439. if(x == 0)
  440. continue;
  441. cmdset = info[i];
  442. if(cmdset == 0 || cmdset == 0xFFFF)
  443. return 0;
  444. return cmdset & x;
  445. }
  446. return 0;
  447. }
  448. */
  449. static int
  450. atadone(void* arg)
  451. {
  452. return ((Ctlr*)arg)->done;
  453. }
  454. static int
  455. atarwmmode(Drive* drive, int cmdport, int ctlport, int dev)
  456. {
  457. int as, maxrwm, rwm;
  458. maxrwm = (drive->info[Imaxrwm] & 0xFF);
  459. if(maxrwm == 0)
  460. return 0;
  461. /*
  462. * Sometimes drives come up with the current count set
  463. * to 0; if so, set a suitable value, otherwise believe
  464. * the value in Irwm if the 0x100 bit is set.
  465. */
  466. if(drive->info[Irwm] & 0x100)
  467. rwm = (drive->info[Irwm] & 0xFF);
  468. else
  469. rwm = 0;
  470. if(rwm == 0)
  471. rwm = maxrwm;
  472. if(rwm > 16)
  473. rwm = 16;
  474. if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 102*1000) < 0)
  475. return 0;
  476. outb(cmdport+Count, rwm);
  477. outb(cmdport+Command, Csm);
  478. microdelay(1);
  479. as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 1000);
  480. inb(cmdport+Status);
  481. if(as < 0 || (as & (Df|Err)))
  482. return 0;
  483. drive->rwm = rwm;
  484. return rwm;
  485. }
  486. static int
  487. atadmamode(Drive* drive)
  488. {
  489. int dma;
  490. /*
  491. * Check if any DMA mode enabled.
  492. * Assumes the BIOS has picked and enabled the best.
  493. * This is completely passive at the moment, no attempt is
  494. * made to ensure the hardware is correctly set up.
  495. */
  496. dma = drive->info[Imwdma] & 0x0707;
  497. drive->dma = (dma>>8) & dma;
  498. if(drive->dma == 0 && (drive->info[Ivalid] & 0x04)){
  499. dma = drive->info[Iudma] & 0x7F7F;
  500. drive->dma = (dma>>8) & dma;
  501. if(drive->dma)
  502. drive->dma |= 'U'<<16;
  503. }
  504. return dma;
  505. }
  506. static int
  507. ataidentify(int cmdport, int ctlport, int dev, int pkt, void* info)
  508. {
  509. int as, command, drdy;
  510. if(pkt){
  511. command = Cidpkt;
  512. drdy = 0;
  513. }
  514. else{
  515. command = Cid;
  516. drdy = Drdy;
  517. }
  518. as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
  519. if(as < 0)
  520. return as;
  521. outb(cmdport+Command, command);
  522. microdelay(1);
  523. as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
  524. if(as < 0)
  525. return -1;
  526. if(as & Err)
  527. return as;
  528. memset(info, 0, 512);
  529. inss(cmdport+Data, info, 256);
  530. inb(cmdport+Status);
  531. if(DEBUG & DbgIDENTIFY){
  532. int i;
  533. ushort *sp;
  534. sp = (ushort*)info;
  535. for(i = 0; i < 256; i++){
  536. if(i && (i%16) == 0)
  537. print("\n");
  538. print(" %4.4uX", *sp);
  539. sp++;
  540. }
  541. print("\n");
  542. }
  543. return 0;
  544. }
  545. static Drive*
  546. atadrive(int cmdport, int ctlport, int dev)
  547. {
  548. Drive *drive;
  549. int as, i, pkt;
  550. uchar buf[512], *p;
  551. ushort iconfig, *sp;
  552. atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
  553. pkt = 1;
  554. retry:
  555. as = ataidentify(cmdport, ctlport, dev, pkt, buf);
  556. if(as < 0)
  557. return nil;
  558. if(as & Err){
  559. if(pkt == 0)
  560. return nil;
  561. pkt = 0;
  562. goto retry;
  563. }
  564. if((drive = malloc(sizeof(Drive))) == nil)
  565. return nil;
  566. drive->dev = dev;
  567. memmove(drive->info, buf, sizeof(drive->info));
  568. drive->sense[0] = 0x70;
  569. drive->sense[7] = sizeof(drive->sense)-7;
  570. drive->inquiry[2] = 2;
  571. drive->inquiry[3] = 2;
  572. drive->inquiry[4] = sizeof(drive->inquiry)-4;
  573. p = &drive->inquiry[8];
  574. sp = &drive->info[Imodel];
  575. for(i = 0; i < 20; i++){
  576. *p++ = *sp>>8;
  577. *p++ = *sp++;
  578. }
  579. drive->secsize = 512;
  580. /*
  581. * Beware the CompactFlash Association feature set.
  582. * Now, why this value in Iconfig just walks all over the bit
  583. * definitions used in the other parts of the ATA/ATAPI standards
  584. * is a mystery and a sign of true stupidity on someone's part.
  585. * Anyway, the standard says if this value is 0x848A then it's
  586. * CompactFlash and it's NOT a packet device.
  587. */
  588. iconfig = drive->info[Iconfig];
  589. if(iconfig != 0x848A && (iconfig & 0xC000) == 0x8000){
  590. if(iconfig & 0x01)
  591. drive->pkt = 16;
  592. else
  593. drive->pkt = 12;
  594. }
  595. else{
  596. if(drive->info[Ivalid] & 0x0001){
  597. drive->c = drive->info[Iccyl];
  598. drive->h = drive->info[Ichead];
  599. drive->s = drive->info[Icsec];
  600. }
  601. else{
  602. drive->c = drive->info[Ilcyl];
  603. drive->h = drive->info[Ilhead];
  604. drive->s = drive->info[Ilsec];
  605. }
  606. if(drive->info[Icapabilities] & Mlba){
  607. if(drive->info[Icsfs+1] & Maddr48){
  608. drive->sectors = drive->info[Ilba48]
  609. | (drive->info[Ilba48+1]<<16)
  610. | ((vlong)drive->info[Ilba48+2]<<32);
  611. drive->flags |= Lba48;
  612. }
  613. else{
  614. drive->sectors = (drive->info[Ilba+1]<<16)
  615. |drive->info[Ilba];
  616. }
  617. drive->dev |= Lba;
  618. }
  619. else
  620. drive->sectors = drive->c*drive->h*drive->s;
  621. atarwmmode(drive, cmdport, ctlport, dev);
  622. }
  623. atadmamode(drive);
  624. if(DEBUG & DbgCONFIG){
  625. print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
  626. dev, cmdport, iconfig, drive->info[Icapabilities]);
  627. print(" mwdma %4.4uX", drive->info[Imwdma]);
  628. if(drive->info[Ivalid] & 0x04)
  629. print(" udma %4.4uX", drive->info[Iudma]);
  630. print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
  631. if(drive->flags&Lba48)
  632. print("\tLLBA sectors %lld", drive->sectors);
  633. print("\n");
  634. }
  635. return drive;
  636. }
  637. static void
  638. atasrst(int ctlport)
  639. {
  640. /*
  641. * Srst is a big stick and may cause problems if further
  642. * commands are tried before the drives become ready again.
  643. * Also, there will be problems here if overlapped commands
  644. * are ever supported.
  645. */
  646. microdelay(5);
  647. outb(ctlport+Dc, Srst);
  648. microdelay(5);
  649. outb(ctlport+Dc, 0);
  650. microdelay(2*1000);
  651. }
  652. static SDev*
  653. ataprobe(int cmdport, int ctlport, int irq)
  654. {
  655. Ctlr* ctlr;
  656. SDev *sdev;
  657. Drive *drive;
  658. int dev, error, rhi, rlo;
  659. static int nonlegacy = 'C';
  660. if(ioalloc(cmdport, 8, 0, "atacmd") < 0) {
  661. print("ataprobe: Cannot allocate %X\n", cmdport);
  662. return nil;
  663. }
  664. if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
  665. print("ataprobe: Cannot allocate %X\n", ctlport + As);
  666. iofree(cmdport);
  667. return nil;
  668. }
  669. /*
  670. * Try to detect a floating bus.
  671. * Bsy should be cleared. If not, see if the cylinder registers
  672. * are read/write capable.
  673. * If the master fails, try the slave to catch slave-only
  674. * configurations.
  675. * There's no need to restore the tested registers as they will
  676. * be reset on any detected drives by the Cedd command.
  677. * All this indicates is that there is at least one drive on the
  678. * controller; when the non-existent drive is selected in a
  679. * single-drive configuration the registers of the existing drive
  680. * are often seen, only command execution fails.
  681. */
  682. dev = Dev0;
  683. if(inb(ctlport+As) & Bsy){
  684. outb(cmdport+Dh, dev);
  685. microdelay(1);
  686. trydev1:
  687. atadebug(cmdport, ctlport, "ataprobe bsy");
  688. outb(cmdport+Cyllo, 0xAA);
  689. outb(cmdport+Cylhi, 0x55);
  690. outb(cmdport+Sector, 0xFF);
  691. rlo = inb(cmdport+Cyllo);
  692. rhi = inb(cmdport+Cylhi);
  693. if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55)){
  694. if(dev == Dev1){
  695. release:
  696. iofree(cmdport);
  697. iofree(ctlport+As);
  698. return nil;
  699. }
  700. dev = Dev1;
  701. if(ataready(cmdport, ctlport, dev, Bsy, 0, 20*1000) < 0)
  702. goto trydev1;
  703. }
  704. }
  705. /*
  706. * Disable interrupts on any detected controllers.
  707. */
  708. outb(ctlport+Dc, Nien);
  709. tryedd1:
  710. if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 105*1000) < 0){
  711. /*
  712. * There's something there, but it didn't come up clean,
  713. * so try hitting it with a big stick. The timing here is
  714. * wrong but this is a last-ditch effort and it sometimes
  715. * gets some marginal hardware back online.
  716. */
  717. atasrst(ctlport);
  718. if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 106*1000) < 0)
  719. goto release;
  720. }
  721. /*
  722. * Can only get here if controller is not busy.
  723. * If there are drives Bsy will be set within 400nS,
  724. * must wait 2mS before testing Status.
  725. * Wait for the command to complete (6 seconds max).
  726. */
  727. outb(cmdport+Command, Cedd);
  728. delay(2);
  729. if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 6*1000*1000) < 0)
  730. goto release;
  731. /*
  732. * If bit 0 of the error register is set then the selected drive
  733. * exists. This is enough to detect single-drive configurations.
  734. * However, if the master exists there is no way short of executing
  735. * a command to determine if a slave is present.
  736. * It appears possible to get here testing Dev0 although it doesn't
  737. * exist and the EDD won't take, so try again with Dev1.
  738. */
  739. error = inb(cmdport+Error);
  740. atadebug(cmdport, ctlport, "ataprobe: dev %uX", dev);
  741. if((error & ~0x80) != 0x01){
  742. if(dev == Dev1)
  743. goto release;
  744. dev = Dev1;
  745. goto tryedd1;
  746. }
  747. /*
  748. * At least one drive is known to exist, try to
  749. * identify it. If that fails, don't bother checking
  750. * any further.
  751. * If the one drive found is Dev0 and the EDD command
  752. * didn't indicate Dev1 doesn't exist, check for it.
  753. */
  754. if((drive = atadrive(cmdport, ctlport, dev)) == nil)
  755. goto release;
  756. if((ctlr = malloc(sizeof(Ctlr))) == nil){
  757. free(drive);
  758. goto release;
  759. }
  760. memset(ctlr, 0, sizeof(Ctlr));
  761. if((sdev = malloc(sizeof(SDev))) == nil){
  762. free(ctlr);
  763. free(drive);
  764. goto release;
  765. }
  766. memset(sdev, 0, sizeof(SDev));
  767. drive->ctlr = ctlr;
  768. if(dev == Dev0){
  769. ctlr->drive[0] = drive;
  770. if(!(error & 0x80)){
  771. /*
  772. * Always leave Dh pointing to a valid drive,
  773. * otherwise a subsequent call to ataready on
  774. * this controller may try to test a bogus Status.
  775. * Ataprobe is the only place possibly invalid
  776. * drives should be selected.
  777. */
  778. drive = atadrive(cmdport, ctlport, Dev1);
  779. if(drive != nil){
  780. drive->ctlr = ctlr;
  781. ctlr->drive[1] = drive;
  782. }
  783. else{
  784. outb(cmdport+Dh, Dev0);
  785. microdelay(1);
  786. }
  787. }
  788. }
  789. else
  790. ctlr->drive[1] = drive;
  791. ctlr->cmdport = cmdport;
  792. ctlr->ctlport = ctlport;
  793. ctlr->irq = irq;
  794. ctlr->tbdf = BUSUNKNOWN;
  795. ctlr->command = Cedd; /* debugging */
  796. switch(cmdport){
  797. default:
  798. sdev->idno = nonlegacy;
  799. break;
  800. case 0x1F0:
  801. sdev->idno = 'C';
  802. nonlegacy = 'E';
  803. break;
  804. case 0x170:
  805. sdev->idno = 'D';
  806. nonlegacy = 'E';
  807. break;
  808. }
  809. sdev->ifc = &sdataifc;
  810. sdev->ctlr = ctlr;
  811. sdev->nunit = 2;
  812. ctlr->sdev = sdev;
  813. return sdev;
  814. }
  815. static void
  816. ataclear(SDev *sdev)
  817. {
  818. Ctlr* ctlr;
  819. ctlr = sdev->ctlr;
  820. iofree(ctlr->cmdport);
  821. iofree(ctlr->ctlport + As);
  822. if (ctlr->drive[0])
  823. free(ctlr->drive[0]);
  824. if (ctlr->drive[1])
  825. free(ctlr->drive[1]);
  826. if (sdev->name)
  827. free(sdev->name);
  828. if (sdev->unitflg)
  829. free(sdev->unitflg);
  830. if (sdev->unit)
  831. free(sdev->unit);
  832. free(ctlr);
  833. free(sdev);
  834. }
  835. static char *
  836. atastat(SDev *sdev, char *p, char *e)
  837. {
  838. Ctlr *ctlr = sdev->ctlr;
  839. return seprint(p, e, "%s ata port %X ctl %X irq %d\n",
  840. sdev->name, ctlr->cmdport, ctlr->ctlport, ctlr->irq);
  841. }
  842. static SDev*
  843. ataprobew(DevConf *cf)
  844. {
  845. char *p;
  846. ISAConf isa;
  847. if (cf->nports != 2)
  848. error(Ebadarg);
  849. memset(&isa, 0, sizeof isa);
  850. isa.port = cf->ports[0].port;
  851. isa.irq = cf->intnum;
  852. if((p=strchr(cf->type, '/')) == nil || pcmspecial(p+1, &isa) < 0)
  853. error("cannot find controller");
  854. return ataprobe(cf->ports[0].port, cf->ports[1].port, cf->intnum);
  855. }
  856. /*
  857. * These are duplicated with sdsetsense, etc., in devsd.c, but
  858. * those assume that the disk is not SCSI while in fact here
  859. * ata drives are not SCSI but ATAPI ones kind of are.
  860. */
  861. static int
  862. atasetsense(Drive* drive, int status, int key, int asc, int ascq)
  863. {
  864. drive->sense[2] = key;
  865. drive->sense[12] = asc;
  866. drive->sense[13] = ascq;
  867. return status;
  868. }
  869. static int
  870. atamodesense(Drive* drive, uchar* cmd)
  871. {
  872. int len;
  873. /*
  874. * Fake a vendor-specific request with page code 0,
  875. * return the drive info.
  876. */
  877. if((cmd[2] & 0x3F) != 0 && (cmd[2] & 0x3F) != 0x3F)
  878. return atasetsense(drive, SDcheck, 0x05, 0x24, 0);
  879. len = (cmd[7]<<8)|cmd[8];
  880. if(len == 0)
  881. return SDok;
  882. if(len < 8+sizeof(drive->info))
  883. return atasetsense(drive, SDcheck, 0x05, 0x1A, 0);
  884. if(drive->data == nil || drive->dlen < len)
  885. return atasetsense(drive, SDcheck, 0x05, 0x20, 1);
  886. memset(drive->data, 0, 8);
  887. drive->data[0] = sizeof(drive->info)>>8;
  888. drive->data[1] = sizeof(drive->info);
  889. memmove(drive->data+8, drive->info, sizeof(drive->info));
  890. drive->data += 8+sizeof(drive->info);
  891. return SDok;
  892. }
  893. static int
  894. atastandby(Drive* drive, int period)
  895. {
  896. Ctlr* ctlr;
  897. int cmdport, done;
  898. ctlr = drive->ctlr;
  899. drive->command = Cstandby;
  900. qlock(ctlr);
  901. cmdport = ctlr->cmdport;
  902. ilock(ctlr);
  903. outb(cmdport+Count, period);
  904. outb(cmdport+Dh, drive->dev);
  905. ctlr->done = 0;
  906. ctlr->curdrive = drive;
  907. ctlr->command = Cstandby; /* debugging */
  908. outb(cmdport+Command, Cstandby);
  909. iunlock(ctlr);
  910. while(waserror())
  911. ;
  912. tsleep(ctlr, atadone, ctlr, 60*1000);
  913. poperror();
  914. done = ctlr->done;
  915. qunlock(ctlr);
  916. if(!done || (drive->status & Err))
  917. return atasetsense(drive, SDcheck, 4, 8, drive->error);
  918. return SDok;
  919. }
  920. static void
  921. atanop(Drive* drive, int subcommand)
  922. {
  923. Ctlr* ctlr;
  924. int as, cmdport, ctlport, timeo;
  925. /*
  926. * Attempt to abort a command by using NOP.
  927. * In response, the drive is supposed to set Abrt
  928. * in the Error register, set (Drdy|Err) in Status
  929. * and clear Bsy when done. However, some drives
  930. * (e.g. ATAPI Zip) just go Bsy then clear Status
  931. * when done, hence the timeout loop only on Bsy
  932. * and the forced setting of drive->error.
  933. */
  934. ctlr = drive->ctlr;
  935. cmdport = ctlr->cmdport;
  936. outb(cmdport+Features, subcommand);
  937. outb(cmdport+Dh, drive->dev);
  938. ctlr->command = Cnop; /* debugging */
  939. outb(cmdport+Command, Cnop);
  940. microdelay(1);
  941. ctlport = ctlr->ctlport;
  942. for(timeo = 0; timeo < 1000; timeo++){
  943. as = inb(ctlport+As);
  944. if(!(as & Bsy))
  945. break;
  946. microdelay(1);
  947. }
  948. drive->error |= Abrt;
  949. }
  950. static void
  951. ataabort(Drive* drive, int dolock)
  952. {
  953. /*
  954. * If NOP is available (packet commands) use it otherwise
  955. * must try a software reset.
  956. */
  957. if(dolock)
  958. ilock(drive->ctlr);
  959. if(drive->info[Icsfs] & Mnop)
  960. atanop(drive, 0);
  961. else{
  962. atasrst(drive->ctlr->ctlport);
  963. drive->error |= Abrt;
  964. }
  965. if(dolock)
  966. iunlock(drive->ctlr);
  967. }
  968. static int
  969. atadmasetup(Drive* drive, int len)
  970. {
  971. Prd *prd;
  972. ulong pa;
  973. Ctlr *ctlr;
  974. int bmiba, bmisx, count, i, span;
  975. ctlr = drive->ctlr;
  976. pa = PCIWADDR(drive->data);
  977. if(pa & 0x03)
  978. return -1;
  979. /*
  980. * Sometimes drives identify themselves as being DMA capable
  981. * although they are not on a busmastering controller.
  982. */
  983. prd = ctlr->prdt;
  984. if(prd == nil){
  985. drive->dmactl = 0;
  986. print("disabling dma: not on a busmastering controller\n");
  987. return -1;
  988. }
  989. for(i = 0; len && i < Nprd; i++){
  990. prd->pa = pa;
  991. span = ROUNDUP(pa, ctlr->span);
  992. if(span == pa)
  993. span += ctlr->span;
  994. count = span - pa;
  995. if(count >= len){
  996. prd->count = PrdEOT|len;
  997. break;
  998. }
  999. prd->count = count;
  1000. len -= count;
  1001. pa += count;
  1002. prd++;
  1003. }
  1004. if(i == Nprd)
  1005. (prd-1)->count |= PrdEOT;
  1006. bmiba = ctlr->bmiba;
  1007. outl(bmiba+Bmidtpx, PCIWADDR(ctlr->prdt));
  1008. if(drive->write)
  1009. outb(ctlr->bmiba+Bmicx, 0);
  1010. else
  1011. outb(ctlr->bmiba+Bmicx, Rwcon);
  1012. bmisx = inb(bmiba+Bmisx);
  1013. outb(bmiba+Bmisx, bmisx|Ideints|Idedmae);
  1014. return 0;
  1015. }
  1016. static void
  1017. atadmastart(Ctlr* ctlr, int write)
  1018. {
  1019. if(write)
  1020. outb(ctlr->bmiba+Bmicx, Ssbm);
  1021. else
  1022. outb(ctlr->bmiba+Bmicx, Rwcon|Ssbm);
  1023. }
  1024. static int
  1025. atadmastop(Ctlr* ctlr)
  1026. {
  1027. int bmiba;
  1028. bmiba = ctlr->bmiba;
  1029. outb(bmiba+Bmicx, inb(bmiba+Bmicx) & ~Ssbm);
  1030. return inb(bmiba+Bmisx);
  1031. }
  1032. static void
  1033. atadmainterrupt(Drive* drive, int count)
  1034. {
  1035. Ctlr* ctlr;
  1036. int bmiba, bmisx;
  1037. ctlr = drive->ctlr;
  1038. bmiba = ctlr->bmiba;
  1039. bmisx = inb(bmiba+Bmisx);
  1040. switch(bmisx & (Ideints|Idedmae|Bmidea)){
  1041. case Bmidea:
  1042. /*
  1043. * Data transfer still in progress, nothing to do
  1044. * (this should never happen).
  1045. */
  1046. return;
  1047. case Ideints:
  1048. case Ideints|Bmidea:
  1049. /*
  1050. * Normal termination, tidy up.
  1051. */
  1052. drive->data += count;
  1053. break;
  1054. default:
  1055. /*
  1056. * What's left are error conditions (memory transfer
  1057. * problem) and the device is not done but the PRD is
  1058. * exhausted. For both cases must somehow tell the
  1059. * drive to abort.
  1060. */
  1061. ataabort(drive, 0);
  1062. break;
  1063. }
  1064. atadmastop(ctlr);
  1065. ctlr->done = 1;
  1066. }
  1067. static void
  1068. atapktinterrupt(Drive* drive)
  1069. {
  1070. Ctlr* ctlr;
  1071. int cmdport, len;
  1072. ctlr = drive->ctlr;
  1073. cmdport = ctlr->cmdport;
  1074. switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
  1075. case Cd:
  1076. outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
  1077. break;
  1078. case 0:
  1079. len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
  1080. if(drive->data+len > drive->limit){
  1081. atanop(drive, 0);
  1082. break;
  1083. }
  1084. outss(cmdport+Data, drive->data, len/2);
  1085. drive->data += len;
  1086. break;
  1087. case Io:
  1088. len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
  1089. if(drive->data+len > drive->limit){
  1090. atanop(drive, 0);
  1091. break;
  1092. }
  1093. inss(cmdport+Data, drive->data, len/2);
  1094. drive->data += len;
  1095. break;
  1096. case Io|Cd:
  1097. if(drive->pktdma)
  1098. atadmainterrupt(drive, drive->dlen);
  1099. else
  1100. ctlr->done = 1;
  1101. break;
  1102. }
  1103. }
  1104. static int
  1105. atapktio(Drive* drive, uchar* cmd, int clen)
  1106. {
  1107. Ctlr *ctlr;
  1108. int as, cmdport, ctlport, len, r, timeo;
  1109. if(cmd[0] == 0x5A && (cmd[2] & 0x3F) == 0)
  1110. return atamodesense(drive, cmd);
  1111. r = SDok;
  1112. drive->command = Cpkt;
  1113. memmove(drive->pktcmd, cmd, clen);
  1114. memset(drive->pktcmd+clen, 0, drive->pkt-clen);
  1115. drive->limit = drive->data+drive->dlen;
  1116. ctlr = drive->ctlr;
  1117. cmdport = ctlr->cmdport;
  1118. ctlport = ctlr->ctlport;
  1119. qlock(ctlr);
  1120. as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 107*1000);
  1121. /* used to test as&Chk as failure too, but some CD readers use that for media change */
  1122. if(as < 0){
  1123. qunlock(ctlr);
  1124. return -1;
  1125. }
  1126. ilock(ctlr);
  1127. if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen))
  1128. drive->pktdma = Dma;
  1129. else
  1130. drive->pktdma = 0;
  1131. outb(cmdport+Features, drive->pktdma);
  1132. outb(cmdport+Count, 0);
  1133. outb(cmdport+Sector, 0);
  1134. len = 16*drive->secsize;
  1135. outb(cmdport+Bytelo, len);
  1136. outb(cmdport+Bytehi, len>>8);
  1137. outb(cmdport+Dh, drive->dev);
  1138. ctlr->done = 0;
  1139. ctlr->curdrive = drive;
  1140. ctlr->command = Cpkt; /* debugging */
  1141. if(drive->pktdma)
  1142. atadmastart(ctlr, drive->write);
  1143. outb(cmdport+Command, Cpkt);
  1144. if((drive->info[Iconfig] & Mdrq) != 0x0020){
  1145. microdelay(1);
  1146. as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 4*1000);
  1147. if(as < 0 || (as & (Bsy|Chk))){
  1148. drive->status = as<0 ? 0 : as;
  1149. ctlr->curdrive = nil;
  1150. ctlr->done = 1;
  1151. r = SDtimeout;
  1152. }else
  1153. atapktinterrupt(drive);
  1154. }
  1155. iunlock(ctlr);
  1156. while(waserror())
  1157. ;
  1158. if(!drive->pktdma)
  1159. sleep(ctlr, atadone, ctlr);
  1160. else for(timeo = 0; !ctlr->done; timeo++){
  1161. tsleep(ctlr, atadone, ctlr, 1000);
  1162. if(ctlr->done)
  1163. break;
  1164. ilock(ctlr);
  1165. atadmainterrupt(drive, 0);
  1166. if(!drive->error && timeo > 20){
  1167. ataabort(drive, 0);
  1168. atadmastop(ctlr);
  1169. drive->dmactl = 0;
  1170. drive->error |= Abrt;
  1171. }
  1172. if(drive->error){
  1173. drive->status |= Chk;
  1174. ctlr->curdrive = nil;
  1175. }
  1176. iunlock(ctlr);
  1177. }
  1178. poperror();
  1179. qunlock(ctlr);
  1180. if(drive->status & Chk)
  1181. r = SDcheck;
  1182. return r;
  1183. }
  1184. static uchar cmd48[256] = {
  1185. [Crs] Crs48,
  1186. [Crd] Crd48,
  1187. [Crdq] Crdq48,
  1188. [Crsm] Crsm48,
  1189. [Cws] Cws48,
  1190. [Cwd] Cwd48,
  1191. [Cwdq] Cwdq48,
  1192. [Cwsm] Cwsm48,
  1193. };
  1194. static int
  1195. atageniostart(Drive* drive, vlong lba)
  1196. {
  1197. Ctlr *ctlr;
  1198. uchar cmd;
  1199. int as, c, cmdport, ctlport, h, len, s, use48;
  1200. use48 = 0;
  1201. if((drive->flags&Lba48always) || (lba>>28) || drive->count > 256){
  1202. if(!(drive->flags & Lba48))
  1203. return -1;
  1204. use48 = 1;
  1205. c = h = s = 0;
  1206. }
  1207. else if(drive->dev & Lba){
  1208. c = (lba>>8) & 0xFFFF;
  1209. h = (lba>>24) & 0x0F;
  1210. s = lba & 0xFF;
  1211. }
  1212. else{
  1213. c = lba/(drive->s*drive->h);
  1214. h = ((lba/drive->s) % drive->h);
  1215. s = (lba % drive->s) + 1;
  1216. }
  1217. ctlr = drive->ctlr;
  1218. cmdport = ctlr->cmdport;
  1219. ctlport = ctlr->ctlport;
  1220. if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 101*1000) < 0)
  1221. return -1;
  1222. ilock(ctlr);
  1223. if(drive->dmactl && !atadmasetup(drive, drive->count*drive->secsize)){
  1224. if(drive->write)
  1225. drive->command = Cwd;
  1226. else
  1227. drive->command = Crd;
  1228. }
  1229. else if(drive->rwmctl){
  1230. drive->block = drive->rwm*drive->secsize;
  1231. if(drive->write)
  1232. drive->command = Cwsm;
  1233. else
  1234. drive->command = Crsm;
  1235. }
  1236. else{
  1237. drive->block = drive->secsize;
  1238. if(drive->write)
  1239. drive->command = Cws;
  1240. else
  1241. drive->command = Crs;
  1242. }
  1243. drive->limit = drive->data + drive->count*drive->secsize;
  1244. cmd = drive->command;
  1245. if(use48){
  1246. outb(cmdport+Count, (drive->count>>8) & 0xFF);
  1247. outb(cmdport+Count, drive->count & 0XFF);
  1248. outb(cmdport+Lbalo, (lba>>24) & 0xFF);
  1249. outb(cmdport+Lbalo, lba & 0xFF);
  1250. outb(cmdport+Lbamid, (lba>>32) & 0xFF);
  1251. outb(cmdport+Lbamid, (lba>>8) & 0xFF);
  1252. outb(cmdport+Lbahi, (lba>>40) & 0xFF);
  1253. outb(cmdport+Lbahi, (lba>>16) & 0xFF);
  1254. outb(cmdport+Dh, drive->dev|Lba);
  1255. cmd = cmd48[cmd];
  1256. if(DEBUG & Dbg48BIT)
  1257. print("using 48-bit commands\n");
  1258. }
  1259. else{
  1260. outb(cmdport+Count, drive->count);
  1261. outb(cmdport+Sector, s);
  1262. outb(cmdport+Cyllo, c);
  1263. outb(cmdport+Cylhi, c>>8);
  1264. outb(cmdport+Dh, drive->dev|h);
  1265. }
  1266. ctlr->done = 0;
  1267. ctlr->curdrive = drive;
  1268. ctlr->command = drive->command; /* debugging */
  1269. outb(cmdport+Command, cmd);
  1270. switch(drive->command){
  1271. case Cws:
  1272. case Cwsm:
  1273. microdelay(1);
  1274. /* 10*1000 for flash ide drives - maybe detect them? */
  1275. as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 10*1000);
  1276. if(as < 0 || (as & Err)){
  1277. iunlock(ctlr);
  1278. return -1;
  1279. }
  1280. len = drive->block;
  1281. if(drive->data+len > drive->limit)
  1282. len = drive->limit-drive->data;
  1283. outss(cmdport+Data, drive->data, len/2);
  1284. break;
  1285. case Crd:
  1286. case Cwd:
  1287. atadmastart(ctlr, drive->write);
  1288. break;
  1289. }
  1290. iunlock(ctlr);
  1291. return 0;
  1292. }
  1293. static int
  1294. atagenioretry(Drive* drive)
  1295. {
  1296. if(drive->dmactl){
  1297. drive->dmactl = 0;
  1298. print("atagenioretry: disabling dma\n");
  1299. }
  1300. else if(drive->rwmctl)
  1301. drive->rwmctl = 0;
  1302. else
  1303. return atasetsense(drive, SDcheck, 4, 8, drive->error);
  1304. return SDretry;
  1305. }
  1306. static int
  1307. atagenio(Drive* drive, uchar* cmd, int)
  1308. {
  1309. uchar *p;
  1310. Ctlr *ctlr;
  1311. vlong lba, len;
  1312. int count, maxio;
  1313. /*
  1314. * Map SCSI commands into ATA commands for discs.
  1315. * Fail any command with a LUN except INQUIRY which
  1316. * will return 'logical unit not supported'.
  1317. */
  1318. if((cmd[1]>>5) && cmd[0] != 0x12)
  1319. return atasetsense(drive, SDcheck, 0x05, 0x25, 0);
  1320. switch(cmd[0]){
  1321. default:
  1322. return atasetsense(drive, SDcheck, 0x05, 0x20, 0);
  1323. case 0x00: /* test unit ready */
  1324. return SDok;
  1325. case 0x03: /* request sense */
  1326. if(cmd[4] < sizeof(drive->sense))
  1327. len = cmd[4];
  1328. else
  1329. len = sizeof(drive->sense);
  1330. if(drive->data && drive->dlen >= len){
  1331. memmove(drive->data, drive->sense, len);
  1332. drive->data += len;
  1333. }
  1334. return SDok;
  1335. case 0x12: /* inquiry */
  1336. if(cmd[4] < sizeof(drive->inquiry))
  1337. len = cmd[4];
  1338. else
  1339. len = sizeof(drive->inquiry);
  1340. if(drive->data && drive->dlen >= len){
  1341. memmove(drive->data, drive->inquiry, len);
  1342. drive->data += len;
  1343. }
  1344. return SDok;
  1345. case 0x1B: /* start/stop unit */
  1346. /*
  1347. * NOP for now, can use the power management feature
  1348. * set later.
  1349. */
  1350. return SDok;
  1351. case 0x25: /* read capacity */
  1352. if((cmd[1] & 0x01) || cmd[2] || cmd[3])
  1353. return atasetsense(drive, SDcheck, 0x05, 0x24, 0);
  1354. if(drive->data == nil || drive->dlen < 8)
  1355. return atasetsense(drive, SDcheck, 0x05, 0x20, 1);
  1356. /*
  1357. * Read capacity returns the LBA of the last sector.
  1358. */
  1359. len = drive->sectors-1;
  1360. p = drive->data;
  1361. *p++ = len>>24;
  1362. *p++ = len>>16;
  1363. *p++ = len>>8;
  1364. *p++ = len;
  1365. len = drive->secsize;
  1366. *p++ = len>>24;
  1367. *p++ = len>>16;
  1368. *p++ = len>>8;
  1369. *p = len;
  1370. drive->data += 8;
  1371. return SDok;
  1372. case 0x9E: /* long read capacity */
  1373. if((cmd[1] & 0x01) || cmd[2] || cmd[3])
  1374. return atasetsense(drive, SDcheck, 0x05, 0x24, 0);
  1375. if(drive->data == nil || drive->dlen < 8)
  1376. return atasetsense(drive, SDcheck, 0x05, 0x20, 1);
  1377. /*
  1378. * Read capacity returns the LBA of the last sector.
  1379. */
  1380. len = drive->sectors-1;
  1381. p = drive->data;
  1382. *p++ = len>>56;
  1383. *p++ = len>>48;
  1384. *p++ = len>>40;
  1385. *p++ = len>>32;
  1386. *p++ = len>>24;
  1387. *p++ = len>>16;
  1388. *p++ = len>>8;
  1389. *p++ = len;
  1390. len = drive->secsize;
  1391. *p++ = len>>24;
  1392. *p++ = len>>16;
  1393. *p++ = len>>8;
  1394. *p = len;
  1395. drive->data += 12;
  1396. return SDok;
  1397. case 0x28: /* read */
  1398. case 0x2A: /* write */
  1399. break;
  1400. case 0x5A:
  1401. return atamodesense(drive, cmd);
  1402. }
  1403. ctlr = drive->ctlr;
  1404. lba = (cmd[2]<<24)|(cmd[3]<<16)|(cmd[4]<<8)|cmd[5];
  1405. count = (cmd[7]<<8)|cmd[8];
  1406. if(drive->data == nil)
  1407. return SDok;
  1408. if(drive->dlen < count*drive->secsize)
  1409. count = drive->dlen/drive->secsize;
  1410. qlock(ctlr);
  1411. if(ctlr->maxio)
  1412. maxio = ctlr->maxio;
  1413. else if(drive->flags & Lba48)
  1414. maxio = 65536;
  1415. else
  1416. maxio = 256;
  1417. while(count){
  1418. if(count > maxio)
  1419. drive->count = maxio;
  1420. else
  1421. drive->count = count;
  1422. if(atageniostart(drive, lba)){
  1423. ilock(ctlr);
  1424. atanop(drive, 0);
  1425. iunlock(ctlr);
  1426. qunlock(ctlr);
  1427. return atagenioretry(drive);
  1428. }
  1429. while(waserror())
  1430. ;
  1431. tsleep(ctlr, atadone, ctlr, 60*1000);
  1432. poperror();
  1433. if(!ctlr->done){
  1434. /*
  1435. * What should the above timeout be? In
  1436. * standby and sleep modes it could take as
  1437. * long as 30 seconds for a drive to respond.
  1438. * Very hard to get out of this cleanly.
  1439. */
  1440. atadumpstate(drive, cmd, lba, count);
  1441. ataabort(drive, 1);
  1442. qunlock(ctlr);
  1443. return atagenioretry(drive);
  1444. }
  1445. if(drive->status & Err){
  1446. qunlock(ctlr);
  1447. return atasetsense(drive, SDcheck, 4, 8, drive->error);
  1448. }
  1449. count -= drive->count;
  1450. lba += drive->count;
  1451. }
  1452. qunlock(ctlr);
  1453. return SDok;
  1454. }
  1455. static int
  1456. atario(SDreq* r)
  1457. {
  1458. Ctlr *ctlr;
  1459. Drive *drive;
  1460. SDunit *unit;
  1461. uchar cmd10[10], *cmdp, *p;
  1462. int clen, reqstatus, status;
  1463. unit = r->unit;
  1464. if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil){
  1465. r->status = SDtimeout;
  1466. return SDtimeout;
  1467. }
  1468. drive = ctlr->drive[unit->subno];
  1469. /*
  1470. * Most SCSI commands can be passed unchanged except for
  1471. * the padding on the end. The few which require munging
  1472. * are not used internally. Mode select/sense(6) could be
  1473. * converted to the 10-byte form but it's not worth the
  1474. * effort. Read/write(6) are easy.
  1475. */
  1476. switch(r->cmd[0]){
  1477. case 0x08: /* read */
  1478. case 0x0A: /* write */
  1479. cmdp = cmd10;
  1480. memset(cmdp, 0, sizeof(cmd10));
  1481. cmdp[0] = r->cmd[0]|0x20;
  1482. cmdp[1] = r->cmd[1] & 0xE0;
  1483. cmdp[5] = r->cmd[3];
  1484. cmdp[4] = r->cmd[2];
  1485. cmdp[3] = r->cmd[1] & 0x0F;
  1486. cmdp[8] = r->cmd[4];
  1487. clen = sizeof(cmd10);
  1488. break;
  1489. default:
  1490. cmdp = r->cmd;
  1491. clen = r->clen;
  1492. break;
  1493. }
  1494. qlock(drive);
  1495. retry:
  1496. drive->write = r->write;
  1497. drive->data = r->data;
  1498. drive->dlen = r->dlen;
  1499. drive->status = 0;
  1500. drive->error = 0;
  1501. if(drive->pkt)
  1502. status = atapktio(drive, cmdp, clen);
  1503. else
  1504. status = atagenio(drive, cmdp, clen);
  1505. if(status == SDretry){
  1506. if(DbgDEBUG)
  1507. print("%s: retry: dma %8.8uX rwm %4.4uX\n",
  1508. unit->name, drive->dmactl, drive->rwmctl);
  1509. goto retry;
  1510. }
  1511. if(status == SDok){
  1512. atasetsense(drive, SDok, 0, 0, 0);
  1513. if(drive->data){
  1514. p = r->data;
  1515. r->rlen = drive->data - p;
  1516. }
  1517. else
  1518. r->rlen = 0;
  1519. }
  1520. else if(status == SDcheck && !(r->flags & SDnosense)){
  1521. drive->write = 0;
  1522. memset(cmd10, 0, sizeof(cmd10));
  1523. cmd10[0] = 0x03;
  1524. cmd10[1] = r->lun<<5;
  1525. cmd10[4] = sizeof(r->sense)-1;
  1526. drive->data = r->sense;
  1527. drive->dlen = sizeof(r->sense)-1;
  1528. drive->status = 0;
  1529. drive->error = 0;
  1530. if(drive->pkt)
  1531. reqstatus = atapktio(drive, cmd10, 6);
  1532. else
  1533. reqstatus = atagenio(drive, cmd10, 6);
  1534. if(reqstatus == SDok){
  1535. r->flags |= SDvalidsense;
  1536. atasetsense(drive, SDok, 0, 0, 0);
  1537. }
  1538. }
  1539. qunlock(drive);
  1540. r->status = status;
  1541. if(status != SDok)
  1542. return status;
  1543. /*
  1544. * Fix up any results.
  1545. * Many ATAPI CD-ROMs ignore the LUN field completely and
  1546. * return valid INQUIRY data. Patch the response to indicate
  1547. * 'logical unit not supported' if the LUN is non-zero.
  1548. */
  1549. switch(cmdp[0]){
  1550. case 0x12: /* inquiry */
  1551. if((p = r->data) == nil)
  1552. break;
  1553. if((cmdp[1]>>5) && (!drive->pkt || (p[0] & 0x1F) == 0x05))
  1554. p[0] = 0x7F;
  1555. /*FALLTHROUGH*/
  1556. default:
  1557. break;
  1558. }
  1559. return SDok;
  1560. }
  1561. static void
  1562. atainterrupt(Ureg*, void* arg)
  1563. {
  1564. Ctlr *ctlr;
  1565. Drive *drive;
  1566. int cmdport, len, status;
  1567. ctlr = arg;
  1568. ilock(ctlr);
  1569. if(inb(ctlr->ctlport+As) & Bsy){
  1570. iunlock(ctlr);
  1571. if(DEBUG & DbgBsy)
  1572. print("IBsy+");
  1573. return;
  1574. }
  1575. cmdport = ctlr->cmdport;
  1576. status = inb(cmdport+Status);
  1577. if((drive = ctlr->curdrive) == nil){
  1578. iunlock(ctlr);
  1579. if((DEBUG & DbgINL) && ctlr->command != Cedd)
  1580. print("Inil%2.2uX+", ctlr->command);
  1581. return;
  1582. }
  1583. if(status & Err)
  1584. drive->error = inb(cmdport+Error);
  1585. else switch(drive->command){
  1586. default:
  1587. drive->error = Abrt;
  1588. break;
  1589. case Crs:
  1590. case Crsm:
  1591. if(!(status & Drq)){
  1592. drive->error = Abrt;
  1593. break;
  1594. }
  1595. len = drive->block;
  1596. if(drive->data+len > drive->limit)
  1597. len = drive->limit-drive->data;
  1598. inss(cmdport+Data, drive->data, len/2);
  1599. drive->data += len;
  1600. if(drive->data >= drive->limit)
  1601. ctlr->done = 1;
  1602. break;
  1603. case Cws:
  1604. case Cwsm:
  1605. len = drive->block;
  1606. if(drive->data+len > drive->limit)
  1607. len = drive->limit-drive->data;
  1608. drive->data += len;
  1609. if(drive->data >= drive->limit){
  1610. ctlr->done = 1;
  1611. break;
  1612. }
  1613. if(!(status & Drq)){
  1614. drive->error = Abrt;
  1615. break;
  1616. }
  1617. len = drive->block;
  1618. if(drive->data+len > drive->limit)
  1619. len = drive->limit-drive->data;
  1620. outss(cmdport+Data, drive->data, len/2);
  1621. break;
  1622. case Cpkt:
  1623. atapktinterrupt(drive);
  1624. break;
  1625. case Crd:
  1626. case Cwd:
  1627. atadmainterrupt(drive, drive->count*drive->secsize);
  1628. break;
  1629. case Cstandby:
  1630. ctlr->done = 1;
  1631. break;
  1632. }
  1633. iunlock(ctlr);
  1634. if(drive->error){
  1635. status |= Err;
  1636. ctlr->done = 1;
  1637. }
  1638. if(ctlr->done){
  1639. ctlr->curdrive = nil;
  1640. drive->status = status;
  1641. wakeup(ctlr);
  1642. }
  1643. }
  1644. static SDev*
  1645. atapnp(void)
  1646. {
  1647. Ctlr *ctlr;
  1648. Pcidev *p;
  1649. SDev *legacy[2], *sdev, *head, *tail;
  1650. int channel, ispc87415, maxio, pi, r, span;
  1651. legacy[0] = legacy[1] = head = tail = nil;
  1652. if(sdev = ataprobe(0x1F0, 0x3F4, IrqATA0)){
  1653. head = tail = sdev;
  1654. legacy[0] = sdev;
  1655. }
  1656. if(sdev = ataprobe(0x170, 0x374, IrqATA1)){
  1657. if(head != nil)
  1658. tail->next = sdev;
  1659. else
  1660. head = sdev;
  1661. tail = sdev;
  1662. legacy[1] = sdev;
  1663. }
  1664. p = nil;
  1665. while(p = pcimatch(p, 0, 0)){
  1666. /*
  1667. * Look for devices with the correct class and sub-class
  1668. * code and known device and vendor ID; add native-mode
  1669. * channels to the list to be probed, save info for the
  1670. * compatibility mode channels.
  1671. * Note that the legacy devices should not be considered
  1672. * PCI devices by the interrupt controller.
  1673. * For both native and legacy, save info for busmastering
  1674. * if capable.
  1675. * Promise Ultra ATA/66 (PDC20262) appears to
  1676. * 1) give a sub-class of 'other mass storage controller'
  1677. * instead of 'IDE controller', regardless of whether it's
  1678. * the only controller or not;
  1679. * 2) put 0 in the programming interface byte (probably
  1680. * as a consequence of 1) above).
  1681. * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
  1682. */
  1683. if(p->ccrb != 0x01)
  1684. continue;
  1685. if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
  1686. continue;
  1687. pi = p->ccrp;
  1688. ispc87415 = 0;
  1689. maxio = 0;
  1690. span = BMspan;
  1691. switch((p->did<<16)|p->vid){
  1692. default:
  1693. continue;
  1694. case (0x0002<<16)|0x100B: /* NS PC87415 */
  1695. /*
  1696. * Disable interrupts on both channels until
  1697. * after they are probed for drives.
  1698. * This must be called before interrupts are
  1699. * enabled because the IRQ may be shared.
  1700. */
  1701. ispc87415 = 1;
  1702. pcicfgw32(p, 0x40, 0x00000300);
  1703. break;
  1704. case (0x1000<<16)|0x1042: /* PC-Tech RZ1000 */
  1705. /*
  1706. * Turn off prefetch. Overkill, but cheap.
  1707. */
  1708. r = pcicfgr32(p, 0x40);
  1709. r &= ~0x2000;
  1710. pcicfgw32(p, 0x40, r);
  1711. break;
  1712. case (0x4D38<<16)|0x105A: /* Promise PDC20262 */
  1713. case (0x4D30<<16)|0x105A: /* Promise PDC202xx */
  1714. case (0x4D68<<16)|0x105A: /* Promise PDC20268 */
  1715. case (0x4D69<<16)|0x105A: /* Promise Ultra/133 TX2 */
  1716. case (0x3373<<16)|0x105A: /* Promise 20378 RAID */
  1717. case (0x3149<<16)|0x1106: /* VIA VT8237 SATA/RAID */
  1718. case (0x4379<<16)|0x1002: /* ATI 4379 SATA*/
  1719. case (0x3112<<16)|0x1095: /* SiI 3112 SATA/RAID */
  1720. maxio = 15;
  1721. span = 8*1024;
  1722. /*FALLTHROUGH*/
  1723. case (0x3114<<16)|0x1095: /* SiI 3114 SATA/RAID */
  1724. pi = 0x85;
  1725. break;
  1726. case (0x0004<<16)|0x1103: /* HighPoint HPT366 */
  1727. pi = 0x85;
  1728. /*
  1729. * Turn off fast interrupt prediction.
  1730. */
  1731. if((r = pcicfgr8(p, 0x51)) & 0x80)
  1732. pcicfgw8(p, 0x51, r & ~0x80);
  1733. if((r = pcicfgr8(p, 0x55)) & 0x80)
  1734. pcicfgw8(p, 0x55, r & ~0x80);
  1735. break;
  1736. case (0x0640<<16)|0x1095: /* CMD 640B */
  1737. /*
  1738. * Bugfix code here...
  1739. */
  1740. break;
  1741. case (0x7441<<16)|0x1022: /* AMD 768 */
  1742. /*
  1743. * Set:
  1744. * 0x41 prefetch, postwrite;
  1745. * 0x43 FIFO configuration 1/2 and 1/2;
  1746. * 0x44 status register read retry;
  1747. * 0x46 DMA read and end of sector flush.
  1748. */
  1749. r = pcicfgr8(p, 0x41);
  1750. pcicfgw8(p, 0x41, r|0xF0);
  1751. r = pcicfgr8(p, 0x43);
  1752. pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
  1753. r = pcicfgr8(p, 0x44);
  1754. pcicfgw8(p, 0x44, r|0x08);
  1755. r = pcicfgr8(p, 0x46);
  1756. pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
  1757. /*FALLTHROUGH*/
  1758. case (0x7401<<16)|0x1022: /* AMD 755 Cobra */
  1759. case (0x7409<<16)|0x1022: /* AMD 756 Viper */
  1760. case (0x7410<<16)|0x1022: /* AMD 766 Viper Plus */
  1761. case (0x7469<<16)|0x1022: /* AMD 3111 */
  1762. /*
  1763. * This can probably be lumped in with the 768 above.
  1764. */
  1765. /*FALLTHROUGH*/
  1766. case (0x209A<<16)|0x1022: /* AMD CS5536 */
  1767. case (0x01BC<<16)|0x10DE: /* nVidia nForce1 */
  1768. case (0x0065<<16)|0x10DE: /* nVidia nForce2 */
  1769. case (0x0085<<16)|0x10DE: /* nVidia nForce2 MCP */
  1770. case (0x00D5<<16)|0x10DE: /* nVidia nForce3 */
  1771. case (0x00E5<<16)|0x10DE: /* nVidia nForce3 Pro */
  1772. case (0x0035<<16)|0x10DE: /* nVidia nForce3 MCP */
  1773. case (0x0053<<16)|0x10DE: /* nVidia nForce4 */
  1774. case (0x0054<<16)|0x10DE: /* nVidia nForce4 SATA */
  1775. case (0x0055<<16)|0x10DE: /* nVidia nForce4 SATA */
  1776. case (0x0266<<16)|0x10DE: /* nVidia nForce4 430 SATA */
  1777. case (0x0267<<16)|0x10DE: /* nVidia nForce 55 MCP SATA */
  1778. case (0x03EC<<16)|0x10DE: /* nVidia nForce 61 MCP SATA */
  1779. case (0x0448<<16)|0x10DE: /* nVidia nForce 65 MCP SATA */
  1780. case (0x0560<<16)|0x10DE: /* nVidia nForce 69 MCP SATA */
  1781. /*
  1782. * Ditto, although it may have a different base
  1783. * address for the registers (0x50?).
  1784. */
  1785. /*FALLTHROUGH*/
  1786. case (0x1002<<16)|0x4372: /* ATI SB400 */
  1787. case (0x4376<<16)|0x1002: /* ATI Radeon Xpress 200M */
  1788. break;
  1789. case (0x0211<<16)|0x1166: /* ServerWorks IB6566 */
  1790. {
  1791. Pcidev *sb;
  1792. sb = pcimatch(nil, 0x1166, 0x0200);
  1793. if(sb == nil)
  1794. break;
  1795. r = pcicfgr32(sb, 0x64);
  1796. r &= ~0x2000;
  1797. pcicfgw32(sb, 0x64, r);
  1798. }
  1799. span = 32*1024;
  1800. break;
  1801. case (0x5229<<16)|0x10B9: /* ALi M1543 */
  1802. case (0x5288<<16)|0x10B9: /* ALi M5288 SATA */
  1803. /*FALLTHROUGH*/
  1804. case (0x5513<<16)|0x1039: /* SiS 962 */
  1805. case (0x0646<<16)|0x1095: /* CMD 646 */
  1806. case (0x0571<<16)|0x1106: /* VIA 82C686 */
  1807. case (0x1230<<16)|0x8086: /* 82371FB (PIIX) */
  1808. case (0x7010<<16)|0x8086: /* 82371SB (PIIX3) */
  1809. case (0x7111<<16)|0x8086: /* 82371[AE]B (PIIX4[E]) */
  1810. case (0x2411<<16)|0x8086: /* 82801AA (ICH) */
  1811. case (0x2421<<16)|0x8086: /* 82801AB (ICH0) */
  1812. case (0x244A<<16)|0x8086: /* 82801BA (ICH2, Mobile) */
  1813. case (0x244B<<16)|0x8086: /* 82801BA (ICH2, High-End) */
  1814. case (0x248A<<16)|0x8086: /* 82801CA (ICH3, Mobile) */
  1815. case (0x248B<<16)|0x8086: /* 82801CA (ICH3, High-End) */
  1816. case (0x24CA<<16)|0x8086: /* 82801DBM (ICH4, Mobile) */
  1817. case (0x24CB<<16)|0x8086: /* 82801DB (ICH4, High-End) */
  1818. case (0x24DB<<16)|0x8086: /* 82801EB (ICH5) */
  1819. case (0x266F<<16)|0x8086: /* 82801FB (ICH6) */
  1820. case (0x27DF<<16)|0x8086: /* 82801G SATA (ICH7) */
  1821. case (0x27C0<<16)|0x8086: /* 82801GB SATA AHCI (ICH7) */
  1822. case (0x27C4<<16)|0x8086: /* 82801GBM SATA (ICH7) */
  1823. case (0x27C5<<16)|0x8086: /* 82801GBM SATA AHCI (ICH7) */
  1824. break;
  1825. }
  1826. for(channel = 0; channel < 2; channel++){
  1827. if(pi & (1<<(2*channel))){
  1828. sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
  1829. p->mem[1+2*channel].bar & ~0x01,
  1830. p->intl);
  1831. if(sdev == nil)
  1832. continue;
  1833. ctlr = sdev->ctlr;
  1834. if(ispc87415) {
  1835. ctlr->ienable = pc87415ienable;
  1836. print("pc87415disable: not yet implemented\n");
  1837. }
  1838. if(head != nil)
  1839. tail->next = sdev;
  1840. else
  1841. head = sdev;
  1842. tail = sdev;
  1843. ctlr->tbdf = p->tbdf;
  1844. }
  1845. else if((sdev = legacy[channel]) == nil)
  1846. continue;
  1847. else
  1848. ctlr = sdev->ctlr;
  1849. ctlr->pcidev = p;
  1850. ctlr->maxio = maxio;
  1851. ctlr->span = span;
  1852. if(!(pi & 0x80))
  1853. continue;
  1854. ctlr->bmiba = (p->mem[4].bar & ~0x01) + channel*8;
  1855. }
  1856. }
  1857. if(0){
  1858. int port;
  1859. ISAConf isa;
  1860. /*
  1861. * Hack for PCMCIA drives.
  1862. * This will be tidied once we figure out how the whole
  1863. * removeable device thing is going to work.
  1864. */
  1865. memset(&isa, 0, sizeof(isa));
  1866. isa.port = 0x180; /* change this for your machine */
  1867. isa.irq = 11; /* change this for your machine */
  1868. port = isa.port+0x0C;
  1869. channel = pcmspecial("MK2001MPL", &isa);
  1870. if(channel == -1)
  1871. channel = pcmspecial("SunDisk", &isa);
  1872. if(channel == -1){
  1873. isa.irq = 10;
  1874. channel = pcmspecial("CF", &isa);
  1875. }
  1876. if(channel == -1){
  1877. isa.irq = 10;
  1878. channel = pcmspecial("OLYMPUS", &isa);
  1879. }
  1880. if(channel == -1){
  1881. port = isa.port+0x204;
  1882. channel = pcmspecial("ATA/ATAPI", &isa);
  1883. }
  1884. if(channel >= 0 && (sdev = ataprobe(isa.port, port, isa.irq)) != nil){
  1885. if(head != nil)
  1886. tail->next = sdev;
  1887. else
  1888. head = sdev;
  1889. }
  1890. }
  1891. return head;
  1892. }
  1893. static SDev*
  1894. atalegacy(int port, int irq)
  1895. {
  1896. return ataprobe(port, port+0x204, irq);
  1897. }
  1898. static int
  1899. ataenable(SDev* sdev)
  1900. {
  1901. Ctlr *ctlr;
  1902. char name[32];
  1903. ctlr = sdev->ctlr;
  1904. if(ctlr->bmiba){
  1905. #define ALIGN (4 * 1024)
  1906. if(ctlr->pcidev != nil)
  1907. pcisetbme(ctlr->pcidev);
  1908. ctlr->prdt = mallocalign(Nprd*sizeof(Prd), 4, 0, 4*1024);
  1909. }
  1910. snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
  1911. intrenable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
  1912. outb(ctlr->ctlport+Dc, 0);
  1913. if(ctlr->ienable)
  1914. ctlr->ienable(ctlr);
  1915. return 1;
  1916. }
  1917. static int
  1918. atadisable(SDev *sdev)
  1919. {
  1920. Ctlr *ctlr;
  1921. char name[32];
  1922. ctlr = sdev->ctlr;
  1923. outb(ctlr->ctlport+Dc, Nien); /* disable interrupts */
  1924. if (ctlr->idisable)
  1925. ctlr->idisable(ctlr);
  1926. snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
  1927. intrdisable(ctlr->irq, atainterrupt, ctlr, ctlr->tbdf, name);
  1928. if (ctlr->bmiba) {
  1929. if (ctlr->pcidev)
  1930. pciclrbme(ctlr->pcidev);
  1931. free(ctlr->prdt);
  1932. }
  1933. return 0;
  1934. }
  1935. static int
  1936. atarctl(SDunit* unit, char* p, int l)
  1937. {
  1938. int n;
  1939. Ctlr *ctlr;
  1940. Drive *drive;
  1941. if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
  1942. return 0;
  1943. drive = ctlr->drive[unit->subno];
  1944. qlock(drive);
  1945. n = snprint(p, l, "config %4.4uX capabilities %4.4uX",
  1946. drive->info[Iconfig], drive->info[Icapabilities]);
  1947. if(drive->dma)
  1948. n += snprint(p+n, l-n, " dma %8.8uX dmactl %8.8uX",
  1949. drive->dma, drive->dmactl);
  1950. if(drive->rwm)
  1951. n += snprint(p+n, l-n, " rwm %ud rwmctl %ud",
  1952. drive->rwm, drive->rwmctl);
  1953. if(drive->flags&Lba48)
  1954. n += snprint(p+n, l-n, " lba48always %s",
  1955. (drive->flags&Lba48always) ? "on" : "off");
  1956. n += snprint(p+n, l-n, "\n");
  1957. if(drive->sectors){
  1958. n += snprint(p+n, l-n, "geometry %lld %d",
  1959. drive->sectors, drive->secsize);
  1960. if(drive->pkt == 0)
  1961. n += snprint(p+n, l-n, " %d %d %d",
  1962. drive->c, drive->h, drive->s);
  1963. n += snprint(p+n, l-n, "\n");
  1964. }
  1965. qunlock(drive);
  1966. return n;
  1967. }
  1968. static int
  1969. atawctl(SDunit* unit, Cmdbuf* cb)
  1970. {
  1971. int period;
  1972. Ctlr *ctlr;
  1973. Drive *drive;
  1974. if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil)
  1975. return 0;
  1976. drive = ctlr->drive[unit->subno];
  1977. qlock(drive);
  1978. if(waserror()){
  1979. qunlock(drive);
  1980. nexterror();
  1981. }
  1982. /*
  1983. * Dma and rwm control is passive at the moment,
  1984. * i.e. it is assumed that the hardware is set up
  1985. * correctly already either by the BIOS or when
  1986. * the drive was initially identified.
  1987. */
  1988. if(strcmp(cb->f[0], "dma") == 0){
  1989. if(cb->nf != 2 || drive->dma == 0)
  1990. error(Ebadctl);
  1991. if(strcmp(cb->f[1], "on") == 0)
  1992. drive->dmactl = drive->dma;
  1993. else if(strcmp(cb->f[1], "off") == 0)
  1994. drive->dmactl = 0;
  1995. else
  1996. error(Ebadctl);
  1997. }
  1998. else if(strcmp(cb->f[0], "rwm") == 0){
  1999. if(cb->nf != 2 || drive->rwm == 0)
  2000. error(Ebadctl);
  2001. if(strcmp(cb->f[1], "on") == 0)
  2002. drive->rwmctl = drive->rwm;
  2003. else if(strcmp(cb->f[1], "off") == 0)
  2004. drive->rwmctl = 0;
  2005. else
  2006. error(Ebadctl);
  2007. }
  2008. else if(strcmp(cb->f[0], "standby") == 0){
  2009. switch(cb->nf){
  2010. default:
  2011. error(Ebadctl);
  2012. case 2:
  2013. period = strtol(cb->f[1], 0, 0);
  2014. if(period && (period < 30 || period > 240*5))
  2015. error(Ebadctl);
  2016. period /= 5;
  2017. break;
  2018. }
  2019. if(atastandby(drive, period) != SDok)
  2020. error(Ebadctl);
  2021. }
  2022. else if(strcmp(cb->f[0], "lba48always") == 0){
  2023. if(cb->nf != 2 || !(drive->flags&Lba48))
  2024. error(Ebadctl);
  2025. if(strcmp(cb->f[1], "on") == 0)
  2026. drive->flags |= Lba48always;
  2027. else if(strcmp(cb->f[1], "off") == 0)
  2028. drive->flags &= ~Lba48always;
  2029. else
  2030. error(Ebadctl);
  2031. }
  2032. else
  2033. error(Ebadctl);
  2034. qunlock(drive);
  2035. poperror();
  2036. return 0;
  2037. }
  2038. SDifc sdataifc = {
  2039. "ata", /* name */
  2040. atapnp, /* pnp */
  2041. atalegacy, /* legacy */
  2042. ataenable, /* enable */
  2043. atadisable, /* disable */
  2044. scsiverify, /* verify */
  2045. scsionline, /* online */
  2046. atario, /* rio */
  2047. atarctl, /* rctl */
  2048. atawctl, /* wctl */
  2049. scsibio, /* bio */
  2050. ataprobew, /* probe */
  2051. ataclear, /* clear */
  2052. atastat, /* rtopctl */
  2053. nil, /* wtopctl */
  2054. };