ether82557.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883
  1. /*
  2. * Intel 82557 Fast Ethernet PCI Bus LAN Controller
  3. * as found on the Intel EtherExpress PRO/100B. This chip is full
  4. * of smarts, unfortunately none of them are in the right place.
  5. * To do:
  6. * the PCI scanning code could be made common to other adapters;
  7. * PCI code needs rewritten to handle byte, word, dword accesses
  8. * and using the devno as a bus+dev+function triplet.
  9. */
  10. #include "u.h"
  11. #include "lib.h"
  12. #include "mem.h"
  13. #include "dat.h"
  14. #include "fns.h"
  15. #include "io.h"
  16. #include "etherif.h"
  17. enum {
  18. Nrfd = 4, /* receive frame area */
  19. NullPointer = 0xFFFFFFFF, /* 82557 NULL pointer */
  20. };
  21. enum { /* CSR */
  22. Status = 0x00, /* byte or word (word includes Ack) */
  23. Ack = 0x01, /* byte */
  24. CommandR = 0x02, /* byte or word (word includes Interrupt) */
  25. Interrupt = 0x03, /* byte */
  26. Pointer = 0x04, /* dword */
  27. Port = 0x08, /* dword */
  28. Fcr = 0x0C, /* Flash control register */
  29. Ecr = 0x0E, /* EEPROM control register */
  30. Mcr = 0x10, /* MDI control register */
  31. };
  32. enum { /* Status */
  33. RUidle = 0x0000,
  34. RUsuspended = 0x0004,
  35. RUnoresources = 0x0008,
  36. RUready = 0x0010,
  37. RUrbd = 0x0020, /* bit */
  38. RUstatus = 0x003F, /* mask */
  39. CUidle = 0x0000,
  40. CUsuspended = 0x0040,
  41. CUactive = 0x0080,
  42. CUstatus = 0x00C0, /* mask */
  43. StatSWI = 0x0400, /* SoftWare generated Interrupt */
  44. StatMDI = 0x0800, /* MDI r/w done */
  45. StatRNR = 0x1000, /* Receive unit Not Ready */
  46. StatCNA = 0x2000, /* Command unit Not Active (Active->Idle) */
  47. StatFR = 0x4000, /* Finished Receiving */
  48. StatCX = 0x8000, /* Command eXecuted */
  49. StatTNO = 0x8000, /* Transmit NOT OK */
  50. };
  51. enum { /* Command (byte) */
  52. CUnop = 0x00,
  53. CUstart = 0x10,
  54. CUresume = 0x20,
  55. LoadDCA = 0x40, /* Load Dump Counters Address */
  56. DumpSC = 0x50, /* Dump Statistical Counters */
  57. LoadCUB = 0x60, /* Load CU Base */
  58. ResetSA = 0x70, /* Dump and Reset Statistical Counters */
  59. RUstart = 0x01,
  60. RUresume = 0x02,
  61. RUabort = 0x04,
  62. LoadHDS = 0x05, /* Load Header Data Size */
  63. LoadRUB = 0x06, /* Load RU Base */
  64. RBDresume = 0x07, /* Resume frame reception */
  65. };
  66. enum { /* Interrupt (byte) */
  67. InterruptM = 0x01, /* interrupt Mask */
  68. InterruptSI = 0x02, /* Software generated Interrupt */
  69. };
  70. enum { /* Ecr */
  71. EEsk = 0x01, /* serial clock */
  72. EEcs = 0x02, /* chip select */
  73. EEdi = 0x04, /* serial data in */
  74. EEdo = 0x08, /* serial data out */
  75. EEstart = 0x04, /* start bit */
  76. EEread = 0x02, /* read opcode */
  77. };
  78. enum { /* Mcr */
  79. MDIread = 0x08000000, /* read opcode */
  80. MDIwrite = 0x04000000, /* write opcode */
  81. MDIready = 0x10000000, /* ready bit */
  82. MDIie = 0x20000000, /* interrupt enable */
  83. };
  84. typedef struct Rfd {
  85. int field;
  86. ulong link;
  87. ulong rbd;
  88. ushort count;
  89. ushort size;
  90. Etherpkt;
  91. } Rfd;
  92. enum { /* field */
  93. RfdCollision = 0x00000001,
  94. RfdIA = 0x00000002, /* IA match */
  95. RfdRxerr = 0x00000010, /* PHY character error */
  96. RfdType = 0x00000020, /* Type frame */
  97. RfdRunt = 0x00000080,
  98. RfdOverrun = 0x00000100,
  99. RfdBuffer = 0x00000200,
  100. RfdAlignment = 0x00000400,
  101. RfdCRC = 0x00000800,
  102. RfdOK = 0x00002000, /* frame received OK */
  103. RfdC = 0x00008000, /* reception Complete */
  104. RfdSF = 0x00080000, /* Simplified or Flexible (1) Rfd */
  105. RfdH = 0x00100000, /* Header RFD */
  106. RfdI = 0x20000000, /* Interrupt after completion */
  107. RfdS = 0x40000000, /* Suspend after completion */
  108. RfdEL = 0x80000000, /* End of List */
  109. };
  110. enum { /* count */
  111. RfdF = 0x00004000,
  112. RfdEOF = 0x00008000,
  113. };
  114. typedef struct Cb {
  115. int command;
  116. ulong link;
  117. uchar data[24]; /* CbIAS + CbConfigure */
  118. } Cb;
  119. typedef struct TxCB {
  120. int command;
  121. ulong link;
  122. ulong tbd;
  123. ushort count;
  124. uchar threshold;
  125. uchar number;
  126. } TxCB;
  127. enum { /* action command */
  128. CbOK = 0x00002000, /* DMA completed OK */
  129. CbC = 0x00008000, /* execution Complete */
  130. CbNOP = 0x00000000,
  131. CbIAS = 0x00010000, /* Indvidual Address Setup */
  132. CbConfigure = 0x00020000,
  133. CbMAS = 0x00030000, /* Multicast Address Setup */
  134. CbTransmit = 0x00040000,
  135. CbDump = 0x00060000,
  136. CbDiagnose = 0x00070000,
  137. CbCommand = 0x00070000, /* mask */
  138. CbSF = 0x00080000, /* CbTransmit */
  139. CbI = 0x20000000, /* Interrupt after completion */
  140. CbS = 0x40000000, /* Suspend after completion */
  141. CbEL = 0x80000000, /* End of List */
  142. };
  143. enum { /* CbTransmit count */
  144. CbEOF = 0x00008000,
  145. };
  146. typedef struct Ctlr Ctlr;
  147. typedef struct Ctlr {
  148. int port;
  149. Pcidev* pcidev;
  150. Ctlr* next;
  151. int active;
  152. int eepromsz; /* address size in bits */
  153. ushort* eeprom;
  154. int ctlrno;
  155. char* type;
  156. uchar configdata[24];
  157. Rfd rfd[Nrfd];
  158. int rfdl;
  159. int rfdx;
  160. Block* cbqhead;
  161. Block* cbqtail;
  162. int cbqbusy;
  163. } Ctlr;
  164. static Ctlr* ctlrhead;
  165. static Ctlr* ctlrtail;
  166. static uchar configdata[24] = {
  167. 0x16, /* byte count */
  168. 0x44, /* Rx/Tx FIFO limit */
  169. 0x00, /* adaptive IFS */
  170. 0x00,
  171. 0x04, /* Rx DMA maximum byte count */
  172. 0x84, /* Tx DMA maximum byte count */
  173. 0x33, /* late SCB, CNA interrupts */
  174. 0x01, /* discard short Rx frames */
  175. 0x00, /* 503/MII */
  176. 0x00,
  177. 0x2E, /* normal operation, NSAI */
  178. 0x00, /* linear priority */
  179. 0x60, /* inter-frame spacing */
  180. 0x00,
  181. 0xF2,
  182. 0x48, /* promiscuous mode off */
  183. 0x00,
  184. 0x40,
  185. 0xF2, /* transmit padding enable */
  186. 0x80, /* full duplex pin enable */
  187. 0x3F, /* no Multi IA */
  188. 0x05, /* no Multi Cast ALL */
  189. };
  190. #define csr8r(c, r) (inb((c)->port+(r)))
  191. #define csr16r(c, r) (ins((c)->port+(r)))
  192. #define csr32r(c, r) (inl((c)->port+(r)))
  193. #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
  194. #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
  195. #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
  196. static void
  197. custart(Ctlr* ctlr)
  198. {
  199. if(ctlr->cbqhead == 0){
  200. ctlr->cbqbusy = 0;
  201. return;
  202. }
  203. ctlr->cbqbusy = 1;
  204. csr32w(ctlr, Pointer, PADDR(ctlr->cbqhead->rp));
  205. while(csr8r(ctlr, CommandR))
  206. ;
  207. csr8w(ctlr, CommandR, CUstart);
  208. }
  209. static void
  210. action(Ctlr* ctlr, Block* bp)
  211. {
  212. Cb *cb;
  213. cb = (Cb*)bp->rp;
  214. cb->command |= CbEL;
  215. if(ctlr->cbqhead){
  216. ctlr->cbqtail->next = bp;
  217. cb = (Cb*)ctlr->cbqtail->rp;
  218. cb->link = PADDR(bp->rp);
  219. cb->command &= ~CbEL;
  220. }
  221. else
  222. ctlr->cbqhead = bp;
  223. ctlr->cbqtail = bp;
  224. if(ctlr->cbqbusy == 0)
  225. custart(ctlr);
  226. }
  227. static void
  228. attach(Ether* ether)
  229. {
  230. int status;
  231. Ctlr *ctlr;
  232. ctlr = ether->ctlr;
  233. status = csr16r(ctlr, Status);
  234. if((status & RUstatus) == RUidle){
  235. csr32w(ctlr, Pointer, PADDR(&ctlr->rfd[ctlr->rfdx]));
  236. while(csr8r(ctlr, CommandR))
  237. ;
  238. csr8w(ctlr, CommandR, RUstart);
  239. }
  240. }
  241. static void
  242. configure(void* arg, int promiscuous)
  243. {
  244. Ctlr *ctlr;
  245. Block *bp;
  246. Cb *cb;
  247. ctlr = ((Ether*)arg)->ctlr;
  248. bp = allocb(sizeof(Cb));
  249. cb = (Cb*)bp->rp;
  250. bp->wp += sizeof(Cb);
  251. cb->command = CbConfigure;
  252. cb->link = NullPointer;
  253. memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata));
  254. if(promiscuous)
  255. cb->data[15] |= 0x01;
  256. action(ctlr, bp);
  257. }
  258. static void
  259. transmit(Ether* ether)
  260. {
  261. Block *bp;
  262. TxCB *txcb;
  263. RingBuf *tb;
  264. for(tb = &ether->tb[ether->ti]; tb->owner == Interface; tb = &ether->tb[ether->ti]){
  265. bp = allocb(tb->len+sizeof(TxCB));
  266. txcb = (TxCB*)bp->wp;
  267. bp->wp += sizeof(TxCB);
  268. txcb->command = CbTransmit;
  269. txcb->link = NullPointer;
  270. txcb->tbd = NullPointer;
  271. txcb->count = CbEOF|tb->len;
  272. txcb->threshold = 2;
  273. txcb->number = 0;
  274. memmove(bp->wp, tb->pkt, tb->len);
  275. memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen);
  276. bp->wp += tb->len;
  277. action(ether->ctlr, bp);
  278. tb->owner = Host;
  279. ether->ti = NEXT(ether->ti, ether->ntb);
  280. }
  281. }
  282. static void
  283. interrupt(Ureg*, void* arg)
  284. {
  285. Rfd *rfd;
  286. Block *bp;
  287. Ctlr *ctlr;
  288. Ether *ether;
  289. int status;
  290. RingBuf *rb;
  291. ether = arg;
  292. ctlr = ether->ctlr;
  293. for(;;){
  294. status = csr16r(ctlr, Status);
  295. csr8w(ctlr, Ack, (status>>8) & 0xFF);
  296. if((status & (StatCX|StatFR|StatCNA|StatRNR)) == 0)
  297. return;
  298. if(status & StatFR){
  299. rfd = &ctlr->rfd[ctlr->rfdx];
  300. while(rfd->field & RfdC){
  301. rb = &ether->rb[ether->ri];
  302. if(rb->owner == Interface){
  303. rb->owner = Host;
  304. rb->len = rfd->count & 0x3FFF;
  305. memmove(rb->pkt, rfd->d, rfd->count & 0x3FFF);
  306. ether->ri = NEXT(ether->ri, ether->nrb);
  307. }
  308. /*
  309. * Reinitialise the frame for reception and bump
  310. * the receive frame processing index;
  311. * bump the sentinel index, mark the new sentinel
  312. * and clear the old sentinel suspend bit;
  313. * set bp and rfd for the next receive frame to
  314. * process.
  315. */
  316. rfd->field = 0;
  317. rfd->count = 0;
  318. ctlr->rfdx = NEXT(ctlr->rfdx, Nrfd);
  319. rfd = &ctlr->rfd[ctlr->rfdl];
  320. ctlr->rfdl = NEXT(ctlr->rfdl, Nrfd);
  321. ctlr->rfd[ctlr->rfdl].field |= RfdS;
  322. rfd->field &= ~RfdS;
  323. rfd = &ctlr->rfd[ctlr->rfdx];
  324. }
  325. status &= ~StatFR;
  326. }
  327. if(status & StatRNR){
  328. while(csr8r(ctlr, CommandR))
  329. ;
  330. csr8w(ctlr, CommandR, RUresume);
  331. status &= ~StatRNR;
  332. }
  333. if(status & StatCNA){
  334. while(bp = ctlr->cbqhead){
  335. if((((Cb*)bp->rp)->command & CbC) == 0)
  336. break;
  337. ctlr->cbqhead = bp->next;
  338. freeb(bp);
  339. }
  340. custart(ctlr);
  341. status &= ~StatCNA;
  342. }
  343. if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))
  344. panic("%s#%d: status %uX\n", ctlr->type, ctlr->ctlrno, status);
  345. }
  346. }
  347. static void
  348. ctlrinit(Ctlr* ctlr)
  349. {
  350. int i;
  351. Rfd *rfd;
  352. ulong link;
  353. link = NullPointer;
  354. for(i = Nrfd-1; i >= 0; i--){
  355. rfd = &ctlr->rfd[i];
  356. rfd->field = 0;
  357. rfd->link = link;
  358. link = PADDR(rfd);
  359. rfd->rbd = NullPointer;
  360. rfd->count = 0;
  361. rfd->size = sizeof(Etherpkt);
  362. }
  363. ctlr->rfd[Nrfd-1].link = PADDR(&ctlr->rfd[0]);
  364. ctlr->rfdl = 0;
  365. ctlr->rfd[0].field |= RfdS;
  366. ctlr->rfdx = 2;
  367. memmove(ctlr->configdata, configdata, sizeof(configdata));
  368. }
  369. static int
  370. miir(Ctlr* ctlr, int phyadd, int regadd)
  371. {
  372. int mcr, timo;
  373. csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16));
  374. mcr = 0;
  375. for(timo = 64; timo; timo--){
  376. mcr = csr32r(ctlr, Mcr);
  377. if(mcr & MDIready)
  378. break;
  379. microdelay(1);
  380. }
  381. if(mcr & MDIready)
  382. return mcr & 0xFFFF;
  383. return -1;
  384. }
  385. static int
  386. miiw(Ctlr* ctlr, int phyadd, int regadd, int data)
  387. {
  388. int mcr, timo;
  389. csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF));
  390. mcr = 0;
  391. for(timo = 64; timo; timo--){
  392. mcr = csr32r(ctlr, Mcr);
  393. if(mcr & MDIready)
  394. break;
  395. microdelay(1);
  396. }
  397. if(mcr & MDIready)
  398. return 0;
  399. return -1;
  400. }
  401. static int
  402. hy93c46r(Ctlr* ctlr, int r)
  403. {
  404. int data, i, op, size;
  405. /*
  406. * Hyundai HY93C46 or equivalent serial EEPROM.
  407. * This sequence for reading a 16-bit register 'r'
  408. * in the EEPROM is taken straight from Section
  409. * 3.3.4.2 of the Intel 82557 User's Guide.
  410. */
  411. reread:
  412. csr16w(ctlr, Ecr, EEcs);
  413. op = EEstart|EEread;
  414. for(i = 2; i >= 0; i--){
  415. data = (((op>>i) & 0x01)<<2)|EEcs;
  416. csr16w(ctlr, Ecr, data);
  417. csr16w(ctlr, Ecr, data|EEsk);
  418. microdelay(1);
  419. csr16w(ctlr, Ecr, data);
  420. microdelay(1);
  421. }
  422. /*
  423. * First time through must work out the EEPROM size.
  424. */
  425. if((size = ctlr->eepromsz) == 0)
  426. size = 8;
  427. for(size = size-1; size >= 0; size--){
  428. data = (((r>>size) & 0x01)<<2)|EEcs;
  429. csr16w(ctlr, Ecr, data);
  430. csr16w(ctlr, Ecr, data|EEsk);
  431. delay(1);
  432. csr16w(ctlr, Ecr, data);
  433. microdelay(1);
  434. if(!(csr16r(ctlr, Ecr) & EEdo))
  435. break;
  436. }
  437. data = 0;
  438. for(i = 15; i >= 0; i--){
  439. csr16w(ctlr, Ecr, EEcs|EEsk);
  440. microdelay(1);
  441. if(csr16r(ctlr, Ecr) & EEdo)
  442. data |= (1<<i);
  443. csr16w(ctlr, Ecr, EEcs);
  444. microdelay(1);
  445. }
  446. csr16w(ctlr, Ecr, 0);
  447. if(ctlr->eepromsz == 0){
  448. ctlr->eepromsz = 8-size;
  449. ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
  450. goto reread;
  451. }
  452. return data;
  453. }
  454. static void
  455. i82557pci(void)
  456. {
  457. Pcidev *p;
  458. Ctlr *ctlr;
  459. p = nil;
  460. while(p = pcimatch(p, 0x8086, 0)){
  461. switch(p->did){
  462. default:
  463. continue;
  464. case 0x1031: /* Intel 82562EM */
  465. case 0x1050: /* Intel 82562EZ */
  466. case 0x1039: /* Intel 82801BD PRO/100 VE */
  467. case 0x103A: /* Intel 82562 PRO/100 VE */
  468. case 0x1064: /* Intel 82562 PRO/100 VE */
  469. case 0x2449: /* Intel 82562ET */
  470. case 0x27DC: /* Intel 82801G PRO/100 VE */
  471. case 0x1209: /* Intel 82559ER */
  472. case 0x1229: /* Intel 8255[789] */
  473. case 0x1030: /* Intel 82559 InBusiness 10/100 */
  474. break;
  475. }
  476. /*
  477. * bar[0] is the memory-mapped register address (4KB),
  478. * bar[1] is the I/O port register address (32 bytes) and
  479. * bar[2] is for the flash ROM (1MB).
  480. */
  481. ctlr = malloc(sizeof(Ctlr));
  482. ctlr->port = p->mem[1].bar & ~0x01;
  483. ctlr->pcidev = p;
  484. if(ctlrhead != nil)
  485. ctlrtail->next = ctlr;
  486. else
  487. ctlrhead = ctlr;
  488. ctlrtail = ctlr;
  489. pcisetbme(p);
  490. }
  491. }
  492. static void
  493. detach(Ether* ether)
  494. {
  495. Ctlr *ctlr;
  496. ctlr = ether->ctlr;
  497. csr32w(ctlr, Port, 0);
  498. delay(1);
  499. while(csr8r(ctlr, CommandR))
  500. ;
  501. }
  502. static int
  503. scanphy(Ctlr* ctlr)
  504. {
  505. int i, oui, x;
  506. for(i = 0; i < 32; i++){
  507. if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF)
  508. continue;
  509. oui <<= 6;
  510. x = miir(ctlr, i, 3);
  511. oui |= x>>10;
  512. //print("phy%d: oui %uX reg1 %uX\n", i, oui, miir(ctlr, i, 1));
  513. if(oui == 0xAA00)
  514. ctlr->eeprom[6] = 0x07<<8;
  515. else if(oui == 0x80017){
  516. if(x & 0x01)
  517. ctlr->eeprom[6] = 0x0A<<8;
  518. else
  519. ctlr->eeprom[6] = 0x04<<8;
  520. }
  521. return i;
  522. }
  523. return -1;
  524. }
  525. int
  526. i82557reset(Ether* ether)
  527. {
  528. int anar, anlpar, bmcr, bmsr, force, i, phyaddr, x;
  529. unsigned short sum;
  530. Block *bp;
  531. uchar ea[Eaddrlen];
  532. Ctlr *ctlr;
  533. Cb *cb;
  534. if(ctlrhead == nil)
  535. i82557pci();
  536. /*
  537. * Any adapter matches if no ether->port is supplied,
  538. * otherwise the ports must match.
  539. */
  540. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  541. if(ctlr->active)
  542. continue;
  543. if(ether->port == 0 || ether->port == ctlr->port){
  544. ctlr->active = 1;
  545. break;
  546. }
  547. }
  548. if(ctlr == nil)
  549. return -1;
  550. /*
  551. * Initialise the Ctlr structure.
  552. * Perform a software reset after which need to ensure busmastering
  553. * is still enabled. The EtherExpress PRO/100B appears to leave
  554. * the PCI configuration alone (see the 'To do' list above) so punt
  555. * for now.
  556. * Load the RUB and CUB registers for linear addressing (0).
  557. */
  558. ether->ctlr = ctlr;
  559. ether->port = ctlr->port;
  560. ether->irq = ctlr->pcidev->intl;
  561. ether->tbdf = ctlr->pcidev->tbdf;
  562. ctlr->ctlrno = ether->ctlrno;
  563. ctlr->type = ether->type;
  564. csr32w(ctlr, Port, 0);
  565. delay(1);
  566. while(csr8r(ctlr, CommandR))
  567. ;
  568. csr32w(ctlr, Pointer, 0);
  569. csr8w(ctlr, CommandR, LoadRUB);
  570. while(csr8r(ctlr, CommandR))
  571. ;
  572. csr8w(ctlr, CommandR, LoadCUB);
  573. /*
  574. * Initialise the action and receive frame areas.
  575. */
  576. ctlrinit(ctlr);
  577. /*
  578. * Read the EEPROM.
  579. * Do a dummy read first to get the size
  580. * and allocate ctlr->eeprom.
  581. */
  582. hy93c46r(ctlr, 0);
  583. sum = 0;
  584. for(i = 0; i < (1<<ctlr->eepromsz); i++){
  585. x = hy93c46r(ctlr, i);
  586. ctlr->eeprom[i] = x;
  587. sum += x;
  588. }
  589. if(sum != 0xBABA)
  590. print("#l%d: EEPROM checksum - 0x%4.4uX\n", ether->ctlrno, sum);
  591. /*
  592. * Eeprom[6] indicates whether there is a PHY and whether
  593. * it's not 10Mb-only, in which case use the given PHY address
  594. * to set any PHY specific options and determine the speed.
  595. * Unfortunately, sometimes the EEPROM is blank except for
  596. * the ether address and checksum; in this case look at the
  597. * controller type and if it's am 82558 or 82559 it has an
  598. * embedded PHY so scan for that.
  599. * If no PHY, assume 82503 (serial) operation.
  600. */
  601. if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000))
  602. phyaddr = ctlr->eeprom[6] & 0x00FF;
  603. else
  604. switch(ctlr->pcidev->rid){
  605. case 0x01: /* 82557 A-step */
  606. case 0x02: /* 82557 B-step */
  607. case 0x03: /* 82557 C-step */
  608. default:
  609. phyaddr = -1;
  610. break;
  611. case 0x04: /* 82558 A-step */
  612. case 0x05: /* 82558 B-step */
  613. case 0x06: /* 82559 A-step */
  614. case 0x07: /* 82559 B-step */
  615. case 0x08: /* 82559 C-step */
  616. case 0x09: /* 82559ER A-step */
  617. phyaddr = scanphy(ctlr);
  618. break;
  619. }
  620. if(phyaddr >= 0){
  621. /*
  622. * Resolve the highest common ability of the two
  623. * link partners. In descending order:
  624. * 0x0100 100BASE-TX Full Duplex
  625. * 0x0200 100BASE-T4
  626. * 0x0080 100BASE-TX
  627. * 0x0040 10BASE-T Full Duplex
  628. * 0x0020 10BASE-T
  629. */
  630. anar = miir(ctlr, phyaddr, 0x04);
  631. anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
  632. anar &= anlpar;
  633. bmcr = 0;
  634. if(anar & 0x380)
  635. bmcr = 0x2000;
  636. if(anar & 0x0140)
  637. bmcr |= 0x0100;
  638. switch((ctlr->eeprom[6]>>8) & 0x001F){
  639. case 0x04: /* DP83840 */
  640. case 0x0A: /* DP83840A */
  641. /*
  642. * The DP83840[A] requires some tweaking for
  643. * reliable operation.
  644. * The manual says bit 10 should be unconditionally
  645. * set although it supposedly only affects full-duplex
  646. * operation (an & 0x0140).
  647. */
  648. x = miir(ctlr, phyaddr, 0x17) & ~0x0520;
  649. x |= 0x0420;
  650. for(i = 0; i < ether->nopt; i++){
  651. if(cistrcmp(ether->opt[i], "congestioncontrol"))
  652. continue;
  653. x |= 0x0100;
  654. break;
  655. }
  656. miiw(ctlr, phyaddr, 0x17, x);
  657. /*
  658. * If the link partner can't autonegotiate, determine
  659. * the speed from elsewhere.
  660. */
  661. if(anlpar == 0){
  662. miir(ctlr, phyaddr, 0x01);
  663. bmsr = miir(ctlr, phyaddr, 0x01);
  664. x = miir(ctlr, phyaddr, 0x19);
  665. if((bmsr & 0x0004) && !(x & 0x0040))
  666. bmcr = 0x2000;
  667. }
  668. break;
  669. case 0x07: /* Intel 82555 */
  670. /*
  671. * Auto-negotiation may fail if the other end is
  672. * a DP83840A and the cable is short.
  673. */
  674. bmsr = miir(ctlr, phyaddr, 0x01);
  675. if((miir(ctlr, phyaddr, 0) & 0x1000) && !(bmsr & 0x0020)){
  676. miiw(ctlr, phyaddr, 0x1A, 0x2010);
  677. x = miir(ctlr, phyaddr, 0);
  678. miiw(ctlr, phyaddr, 0, 0x0200|x);
  679. for(i = 0; i < 3000; i++){
  680. delay(1);
  681. if(miir(ctlr, phyaddr, 0x01) & 0x0020)
  682. break;
  683. }
  684. miiw(ctlr, phyaddr, 0x1A, 0x2000);
  685. anar = miir(ctlr, phyaddr, 0x04);
  686. anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
  687. anar &= anlpar;
  688. bmcr = 0;
  689. if(anar & 0x380)
  690. bmcr = 0x2000;
  691. if(anar & 0x0140)
  692. bmcr |= 0x0100;
  693. }
  694. break;
  695. }
  696. /*
  697. * Force speed and duplex if no auto-negotiation.
  698. */
  699. if(anlpar == 0){
  700. force = 0;
  701. for(i = 0; i < ether->nopt; i++){
  702. if(cistrcmp(ether->opt[i], "fullduplex") == 0){
  703. force = 1;
  704. bmcr |= 0x0100;
  705. ctlr->configdata[19] |= 0x40;
  706. }
  707. else if(cistrcmp(ether->opt[i], "speed") == 0){
  708. force = 1;
  709. x = strtol(&ether->opt[i][6], 0, 0);
  710. if(x == 10)
  711. bmcr &= ~0x2000;
  712. else if(x == 100)
  713. bmcr |= 0x2000;
  714. else
  715. force = 0;
  716. }
  717. }
  718. if(force)
  719. miiw(ctlr, phyaddr, 0x00, bmcr);
  720. }
  721. ctlr->configdata[8] = 1;
  722. ctlr->configdata[15] &= ~0x80;
  723. }
  724. else{
  725. ctlr->configdata[8] = 0;
  726. ctlr->configdata[15] |= 0x80;
  727. }
  728. /*
  729. * Load the chip configuration
  730. */
  731. configure(ether, 0);
  732. /*
  733. * Check if the adapter's station address is to be overridden.
  734. * If not, read it from the EEPROM and set in ether->ea prior to loading
  735. * the station address with the Individual Address Setup command.
  736. */
  737. memset(ea, 0, Eaddrlen);
  738. if(memcmp(ea, ether->ea, Eaddrlen) == 0){
  739. for(i = 0; i < Eaddrlen/2; i++){
  740. x = ctlr->eeprom[i];
  741. ether->ea[2*i] = x & 0xFF;
  742. ether->ea[2*i+1] = (x>>8) & 0xFF;
  743. }
  744. }
  745. bp = allocb(sizeof(Cb));
  746. cb = (Cb*)bp->rp;
  747. bp->wp += sizeof(Cb);
  748. cb->command = CbIAS;
  749. cb->link = NullPointer;
  750. memmove(cb->data, ether->ea, Eaddrlen);
  751. action(ctlr, bp);
  752. /*
  753. * Linkage to the generic ethernet driver.
  754. */
  755. ether->attach = attach;
  756. ether->transmit = transmit;
  757. ether->interrupt = interrupt;
  758. ether->detach = detach;
  759. return 0;
  760. }