sdata.c 38 KB

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  1. #include "u.h"
  2. #include "lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "ureg.h"
  8. #include "error.h"
  9. #include "sd.h"
  10. extern SDifc sdataifc;
  11. enum {
  12. DbgCONFIG = 0x0001, /* detected drive config info */
  13. DbgIDENTIFY = 0x0002, /* detected drive identify info */
  14. DbgSTATE = 0x0004, /* dump state on panic */
  15. DbgPROBE = 0x0008, /* trace device probing */
  16. DbgDEBUG = 0x0080, /* the current problem... */
  17. DbgINL = 0x0100, /* That Inil20+ message we hate */
  18. Dbg48BIT = 0x0200, /* 48-bit LBA */
  19. DbgBsy = 0x0400, /* interrupt but Bsy (shared IRQ) */
  20. };
  21. #define DEBUG (DbgDEBUG|DbgCONFIG)
  22. enum { /* I/O ports */
  23. Data = 0,
  24. Error = 1, /* (read) */
  25. Features = 1, /* (write) */
  26. Count = 2, /* sector count<7-0>, sector count<15-8> */
  27. Ir = 2, /* interrupt reason (PACKET) */
  28. Sector = 3, /* sector number */
  29. Lbalo = 3, /* LBA<7-0>, LBA<31-24> */
  30. Cyllo = 4, /* cylinder low */
  31. Bytelo = 4, /* byte count low (PACKET) */
  32. Lbamid = 4, /* LBA<15-8>, LBA<39-32> */
  33. Cylhi = 5, /* cylinder high */
  34. Bytehi = 5, /* byte count hi (PACKET) */
  35. Lbahi = 5, /* LBA<23-16>, LBA<47-40> */
  36. Dh = 6, /* Device/Head, LBA<32-14> */
  37. Status = 7, /* (read) */
  38. Command = 7, /* (write) */
  39. As = 2, /* Alternate Status (read) */
  40. Dc = 2, /* Device Control (write) */
  41. };
  42. enum { /* Error */
  43. Med = 0x01, /* Media error */
  44. Ili = 0x01, /* command set specific (PACKET) */
  45. Nm = 0x02, /* No Media */
  46. Eom = 0x02, /* command set specific (PACKET) */
  47. Abrt = 0x04, /* Aborted command */
  48. Mcr = 0x08, /* Media Change Request */
  49. Idnf = 0x10, /* no user-accessible address */
  50. Mc = 0x20, /* Media Change */
  51. Unc = 0x40, /* Uncorrectable data error */
  52. Wp = 0x40, /* Write Protect */
  53. Icrc = 0x80, /* Interface CRC error */
  54. };
  55. enum { /* Features */
  56. Dma = 0x01, /* data transfer via DMA (PACKET) */
  57. Ovl = 0x02, /* command overlapped (PACKET) */
  58. };
  59. enum { /* Interrupt Reason */
  60. Cd = 0x01, /* Command/Data */
  61. Io = 0x02, /* I/O direction */
  62. Rel = 0x04, /* Bus Release */
  63. };
  64. enum { /* Device/Head */
  65. Dev0 = 0xA0, /* Master */
  66. Dev1 = 0xB0, /* Slave */
  67. Lba = 0x40, /* LBA mode */
  68. };
  69. enum { /* Status, Alternate Status */
  70. Err = 0x01, /* Error */
  71. Chk = 0x01, /* Check error (PACKET) */
  72. Drq = 0x08, /* Data Request */
  73. Dsc = 0x10, /* Device Seek Complete */
  74. Serv = 0x10, /* Service */
  75. Df = 0x20, /* Device Fault */
  76. Dmrd = 0x20, /* DMA ready (PACKET) */
  77. Drdy = 0x40, /* Device Ready */
  78. Bsy = 0x80, /* Busy */
  79. };
  80. enum { /* Command */
  81. Cnop = 0x00, /* NOP */
  82. Cdr = 0x08, /* Device Reset */
  83. Crs = 0x20, /* Read Sectors */
  84. Crs48 = 0x24, /* Read Sectors Ext */
  85. Crd48 = 0x25, /* Read w/ DMA Ext */
  86. Crdq48 = 0x26, /* Read w/ DMA Queued Ext */
  87. Crsm48 = 0x29, /* Read Multiple Ext */
  88. Cws = 0x30, /* Write Sectors */
  89. Cws48 = 0x34, /* Write Sectors Ext */
  90. Cwd48 = 0x35, /* Write w/ DMA Ext */
  91. Cwdq48 = 0x36, /* Write w/ DMA Queued Ext */
  92. Cwsm48 = 0x39, /* Write Multiple Ext */
  93. Cedd = 0x90, /* Execute Device Diagnostics */
  94. Cpkt = 0xA0, /* Packet */
  95. Cidpkt = 0xA1, /* Identify Packet Device */
  96. Crsm = 0xC4, /* Read Multiple */
  97. Cwsm = 0xC5, /* Write Multiple */
  98. Csm = 0xC6, /* Set Multiple */
  99. Crdq = 0xC7, /* Read DMA queued */
  100. Crd = 0xC8, /* Read DMA */
  101. Cwd = 0xCA, /* Write DMA */
  102. Cwdq = 0xCC, /* Write DMA queued */
  103. Cstandby = 0xE2, /* Standby */
  104. Cid = 0xEC, /* Identify Device */
  105. Csf = 0xEF, /* Set Features */
  106. };
  107. enum { /* Device Control */
  108. Nien = 0x02, /* (not) Interrupt Enable */
  109. Srst = 0x04, /* Software Reset */
  110. };
  111. enum { /* PCI Configuration Registers */
  112. Bmiba = 0x20, /* Bus Master Interface Base Address */
  113. Idetim = 0x40, /* IE Timing */
  114. Sidetim = 0x44, /* Slave IE Timing */
  115. Udmactl = 0x48, /* Ultra DMA/33 Control */
  116. Udmatim = 0x4A, /* Ultra DMA/33 Timing */
  117. };
  118. enum { /* Bus Master IDE I/O Ports */
  119. Bmicx = 0, /* Command */
  120. Bmisx = 2, /* Status */
  121. Bmidtpx = 4, /* Descriptor Table Pointer */
  122. };
  123. enum { /* Bmicx */
  124. Ssbm = 0x01, /* Start/Stop Bus Master */
  125. Rwcon = 0x08, /* Read/Write Control */
  126. };
  127. enum { /* Bmisx */
  128. Bmidea = 0x01, /* Bus Master IDE Active */
  129. Idedmae = 0x02, /* IDE DMA Error (R/WC) */
  130. Ideints = 0x04, /* IDE Interrupt Status (R/WC) */
  131. Dma0cap = 0x20, /* Drive 0 DMA Capable */
  132. Dma1cap = 0x40, /* Drive 0 DMA Capable */
  133. };
  134. enum { /* Physical Region Descriptor */
  135. PrdEOT = 0x80000000, /* Bus Master IDE Active */
  136. };
  137. enum { /* offsets into the identify info. */
  138. Iconfig = 0, /* general configuration */
  139. Ilcyl = 1, /* logical cylinders */
  140. Ilhead = 3, /* logical heads */
  141. Ilsec = 6, /* logical sectors per logical track */
  142. Iserial = 10, /* serial number */
  143. Ifirmware = 23, /* firmware revision */
  144. Imodel = 27, /* model number */
  145. Imaxrwm = 47, /* max. read/write multiple sectors */
  146. Icapabilities = 49, /* capabilities */
  147. Istandby = 50, /* device specific standby timer */
  148. Ipiomode = 51, /* PIO data transfer mode number */
  149. Ivalid = 53,
  150. Iccyl = 54, /* cylinders if (valid&0x01) */
  151. Ichead = 55, /* heads if (valid&0x01) */
  152. Icsec = 56, /* sectors if (valid&0x01) */
  153. Iccap = 57, /* capacity if (valid&0x01) */
  154. Irwm = 59, /* read/write multiple */
  155. Ilba = 60, /* LBA size */
  156. Imwdma = 63, /* multiword DMA mode */
  157. Iapiomode = 64, /* advanced PIO modes supported */
  158. Iminmwdma = 65, /* min. multiword DMA cycle time */
  159. Irecmwdma = 66, /* rec. multiword DMA cycle time */
  160. Iminpio = 67, /* min. PIO cycle w/o flow control */
  161. Iminiordy = 68, /* min. PIO cycle with IORDY */
  162. Ipcktbr = 71, /* time from PACKET to bus release */
  163. Iserbsy = 72, /* time from SERVICE to !Bsy */
  164. Iqdepth = 75, /* max. queue depth */
  165. Imajor = 80, /* major version number */
  166. Iminor = 81, /* minor version number */
  167. Icsfs = 82, /* command set/feature supported */
  168. Icsfe = 85, /* command set/feature enabled */
  169. Iudma = 88, /* ultra DMA mode */
  170. Ierase = 89, /* time for security erase */
  171. Ieerase = 90, /* time for enhanced security erase */
  172. Ipower = 91, /* current advanced power management */
  173. Ilba48 = 100, /* 48-bit LBA size (64 bits in 100-103) */
  174. Irmsn = 127, /* removable status notification */
  175. Isecstat = 128, /* security status */
  176. };
  177. typedef struct Ctlr Ctlr;
  178. typedef struct Drive Drive;
  179. typedef struct Prd {
  180. ulong pa; /* Physical Base Address */
  181. int count;
  182. } Prd;
  183. enum {
  184. Nprd = SDmaxio/(64*1024)+2,
  185. };
  186. typedef struct Ctlr {
  187. int cmdport;
  188. int ctlport;
  189. int irq;
  190. int tbdf;
  191. Pcidev* pcidev;
  192. void (*ienable)(Ctlr*);
  193. SDev* sdev;
  194. Drive* drive[2];
  195. Prd* prdt; /* physical region descriptor table */
  196. // QLock; /* current command */
  197. Drive* curdrive;
  198. int command; /* last command issued (debugging) */
  199. // Rendez;
  200. int done;
  201. Lock; /* register access */
  202. } Ctlr;
  203. typedef struct Drive {
  204. Ctlr* ctlr;
  205. int dev;
  206. ushort info[256];
  207. int c; /* cylinder */
  208. int h; /* head */
  209. int s; /* sector */
  210. vlong sectors; /* total */
  211. int secsize; /* sector size */
  212. // int dma; /* DMA R/W possible */
  213. // int dmactl;
  214. // int rwm; /* read/write multiple possible */
  215. // int rwmctl;
  216. int pkt; /* PACKET device, length of pktcmd */
  217. uchar pktcmd[16];
  218. // int pktdma; /* this PACKET command using dma */
  219. uchar sense[18];
  220. uchar inquiry[48];
  221. // QLock; /* drive access */
  222. int command; /* current command */
  223. int write;
  224. uchar* data;
  225. int dlen;
  226. uchar* limit;
  227. int count; /* sectors */
  228. int block; /* R/W bytes per block */
  229. int status;
  230. int error;
  231. int flags; /* internal flags */
  232. } Drive;
  233. enum { /* internal flags */
  234. Lba48 = 0x1, /* LBA48 mode */
  235. Lba48always = 0x2, /* ... */
  236. };
  237. static void
  238. pc87415ienable(Ctlr* ctlr)
  239. {
  240. Pcidev *p;
  241. int x;
  242. p = ctlr->pcidev;
  243. if(p == nil)
  244. return;
  245. x = pcicfgr32(p, 0x40);
  246. if(ctlr->cmdport == p->mem[0].bar)
  247. x &= ~0x00000100;
  248. else
  249. x &= ~0x00000200;
  250. pcicfgw32(p, 0x40, x);
  251. }
  252. static int
  253. atadebug(int cmdport, int ctlport, char* fmt, ...)
  254. {
  255. int i, n;
  256. va_list arg;
  257. char buf[PRINTSIZE];
  258. if(!(DEBUG & DbgPROBE)){
  259. USED(cmdport, ctlport, fmt);
  260. return 0;
  261. }
  262. va_start(arg, fmt);
  263. n = vseprint(buf, buf+sizeof(buf), fmt, arg) - buf;
  264. va_end(arg);
  265. if(cmdport){
  266. if(buf[n-1] == '\n')
  267. n--;
  268. n += snprint(buf+n, PRINTSIZE-n, " ataregs 0x%uX:",
  269. cmdport);
  270. for(i = Features; i < Command; i++)
  271. n += snprint(buf+n, PRINTSIZE-n, " 0x%2.2uX",
  272. inb(cmdport+i));
  273. if(ctlport)
  274. n += snprint(buf+n, PRINTSIZE-n, " 0x%2.2uX",
  275. inb(ctlport+As));
  276. n += snprint(buf+n, PRINTSIZE-n, "\n");
  277. }
  278. putstrn(buf, n);
  279. return n;
  280. }
  281. static int
  282. ataready(int cmdport, int ctlport, int dev, int reset, int ready, int micro)
  283. {
  284. int as;
  285. atadebug(cmdport, ctlport, "ataready: dev %uX reset %uX ready %uX",
  286. dev, reset, ready);
  287. for(;;){
  288. /*
  289. * Wait for the controller to become not busy and
  290. * possibly for a status bit to become true (usually
  291. * Drdy). Must change to the appropriate device
  292. * register set if necessary before testing for ready.
  293. * Always run through the loop at least once so it
  294. * can be used as a test for !Bsy.
  295. */
  296. as = inb(ctlport+As);
  297. if(as & reset){
  298. /* nothing to do */;
  299. }
  300. else if(dev){
  301. outb(cmdport+Dh, dev);
  302. dev = 0;
  303. }
  304. else if(ready == 0 || (as & ready)){
  305. atadebug(0, 0, "ataready: %d 0x%2.2uX\n", micro, as);
  306. return as;
  307. }
  308. if(micro-- <= 0){
  309. atadebug(0, 0, "ataready: %d 0x%2.2uX\n", micro, as);
  310. break;
  311. }
  312. microdelay(1);
  313. }
  314. atadebug(cmdport, ctlport, "ataready: timeout");
  315. return -1;
  316. }
  317. static int
  318. atacsfenabled(Drive* drive, vlong csf)
  319. {
  320. int cmdset, i, x;
  321. for(i = 0; i < 3; i++){
  322. x = (csf>>(16*i)) & 0xFFFF;
  323. if(x == 0)
  324. continue;
  325. cmdset = drive->info[Icsfe+i];
  326. if(cmdset == 0 || cmdset == 0xFFFF)
  327. return 0;
  328. return cmdset & x;
  329. }
  330. return 0;
  331. }
  332. /*
  333. static int
  334. atasf(int cmdport, int ctlport, int dev, uchar* command)
  335. {
  336. int as, i;
  337. if(ataready(cmdport, ctlport, dev, Bsy|Drq, Drdy, 108*1000) < 0)
  338. return -1;
  339. for(i = Features; i < Dh; i++)
  340. outb(cmdport+i, command[i]);
  341. outb(cmdport+Command, Csf);
  342. microdelay(100);
  343. as = ataready(cmdport, ctlport, 0, Bsy, Drdy|Df|Err, 109*1000);
  344. if(as < 0 || (as & (Df|Err)))
  345. return -1;
  346. return 0;
  347. }
  348. */
  349. static int
  350. ataidentify(int cmdport, int ctlport, int dev, int pkt, void* info)
  351. {
  352. int as, command, drdy;
  353. if(pkt){
  354. command = Cidpkt;
  355. drdy = 0;
  356. }
  357. else{
  358. command = Cid;
  359. drdy = Drdy;
  360. }
  361. as = ataready(cmdport, ctlport, dev, Bsy|Drq, drdy, 103*1000);
  362. if(as < 0)
  363. return as;
  364. outb(cmdport+Command, command);
  365. microdelay(1);
  366. as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 400*1000);
  367. if(as < 0)
  368. return -1;
  369. if(as & Err)
  370. return as;
  371. memset(info, 0, 512);
  372. inss(cmdport+Data, info, 256);
  373. inb(cmdport+Status);
  374. if(DEBUG & DbgIDENTIFY){
  375. int i;
  376. ushort *sp;
  377. sp = (ushort*)info;
  378. for(i = 0; i < 256; i++){
  379. if(i && (i%16) == 0)
  380. print("\n");
  381. print(" %4.4uX ", *sp);
  382. sp++;
  383. }
  384. print("\n");
  385. }
  386. return 0;
  387. }
  388. static Drive*
  389. atadrive(int cmdport, int ctlport, int dev)
  390. {
  391. Drive *drive;
  392. int as, i, pkt;
  393. uchar buf[512], *p;
  394. ushort iconfig, *sp;
  395. atadebug(0, 0, "identify: port 0x%uX dev 0x%2.2uX\n", cmdport, dev);
  396. pkt = 1;
  397. retry:
  398. as = ataidentify(cmdport, ctlport, dev, pkt, buf);
  399. if(as < 0)
  400. return nil;
  401. if(as & Err){
  402. if(pkt == 0)
  403. return nil;
  404. pkt = 0;
  405. goto retry;
  406. }
  407. if((drive = malloc(sizeof(Drive))) == nil)
  408. return nil;
  409. drive->dev = dev;
  410. memmove(drive->info, buf, sizeof(drive->info));
  411. drive->sense[0] = 0x70;
  412. drive->sense[7] = sizeof(drive->sense)-7;
  413. drive->inquiry[2] = 2;
  414. drive->inquiry[3] = 2;
  415. drive->inquiry[4] = sizeof(drive->inquiry)-4;
  416. p = &drive->inquiry[8];
  417. sp = &drive->info[Imodel];
  418. for(i = 0; i < 20; i++){
  419. *p++ = *sp>>8;
  420. *p++ = *sp++;
  421. }
  422. drive->secsize = 512;
  423. /*
  424. * Beware the CompactFlash Association feature set.
  425. * Now, why this value in Iconfig just walks all over the bit
  426. * definitions used in the other parts of the ATA/ATAPI standards
  427. * is a mystery and a sign of true stupidity on someone's part.
  428. * Anyway, the standard says if this value is 0x848A then it's
  429. * CompactFlash and it's NOT a packet device.
  430. */
  431. iconfig = drive->info[Iconfig];
  432. if(iconfig != 0x848A && (iconfig & 0xC000) == 0x8000){
  433. if(iconfig & 0x01)
  434. drive->pkt = 16;
  435. else
  436. drive->pkt = 12;
  437. }
  438. else{
  439. if(drive->info[Ivalid] & 0x0001){
  440. drive->c = drive->info[Iccyl];
  441. drive->h = drive->info[Ichead];
  442. drive->s = drive->info[Icsec];
  443. }
  444. else{
  445. drive->c = drive->info[Ilcyl];
  446. drive->h = drive->info[Ilhead];
  447. drive->s = drive->info[Ilsec];
  448. }
  449. if(drive->info[Icapabilities] & 0x0200){
  450. if(drive->info[Icsfs+1] & 0x0400){
  451. drive->sectors = drive->info[Ilba48]
  452. |(drive->info[Ilba48+1]<<16)
  453. |((vlong)drive->info[Ilba48+2]<<32);
  454. drive->flags |= Lba48;
  455. }
  456. else{
  457. drive->sectors = (drive->info[Ilba+1]<<16)
  458. |drive->info[Ilba];
  459. }
  460. drive->dev |= Lba;
  461. }
  462. else
  463. drive->sectors = drive->c*drive->h*drive->s;
  464. // atarwmmode(drive, cmdport, ctlport, dev);
  465. }
  466. // atadmamode(drive);
  467. if(DEBUG & DbgCONFIG){
  468. print("dev %2.2uX port %uX config %4.4uX capabilities %4.4uX",
  469. dev, cmdport, iconfig, drive->info[Icapabilities]);
  470. print(" mwdma %4.4uX", drive->info[Imwdma]);
  471. if(drive->info[Ivalid] & 0x04)
  472. print(" udma %4.4uX", drive->info[Iudma]);
  473. // print(" dma %8.8uX rwm %ud", drive->dma, drive->rwm);
  474. if(drive->flags&Lba48)
  475. print("\tLLBA sectors %lld", drive->sectors);
  476. print("\n");
  477. }
  478. return drive;
  479. }
  480. static void
  481. atasrst(int ctlport)
  482. {
  483. /*
  484. * Srst is a big stick and may cause problems if further
  485. * commands are tried before the drives become ready again.
  486. * Also, there will be problems here if overlapped commands
  487. * are ever supported.
  488. */
  489. microdelay(5);
  490. outb(ctlport+Dc, Srst);
  491. microdelay(5);
  492. outb(ctlport+Dc, 0);
  493. microdelay(2*1000);
  494. }
  495. static SDev*
  496. ataprobe(int cmdport, int ctlport, int irq)
  497. {
  498. Ctlr* ctlr;
  499. SDev *sdev;
  500. Drive *drive;
  501. int dev, error, rhi, rlo;
  502. // if(ioalloc(cmdport, 8, 0, "atacmd") < 0)
  503. // return nil;
  504. // if(ioalloc(ctlport+As, 1, 0, "atactl") < 0){
  505. // iofree(cmdport);
  506. // return nil;
  507. // }
  508. /*
  509. * Try to detect a floating bus.
  510. * Bsy should be cleared. If not, see if the cylinder registers
  511. * are read/write capable.
  512. * If the master fails, try the slave to catch slave-only
  513. * configurations.
  514. * There's no need to restore the tested registers as they will
  515. * be reset on any detected drives by the Cedd command.
  516. * All this indicates is that there is at least one drive on the
  517. * controller; when the non-existent drive is selected in a
  518. * single-drive configuration the registers of the existing drive
  519. * are often seen, only command execution fails.
  520. */
  521. dev = Dev0;
  522. if(inb(ctlport+As) & Bsy){
  523. outb(cmdport+Dh, dev);
  524. microdelay(1);
  525. trydev1:
  526. atadebug(cmdport, ctlport, "ataprobe bsy");
  527. outb(cmdport+Cyllo, 0xAA);
  528. outb(cmdport+Cylhi, 0x55);
  529. outb(cmdport+Sector, 0xFF);
  530. rlo = inb(cmdport+Cyllo);
  531. rhi = inb(cmdport+Cylhi);
  532. if(rlo != 0xAA && (rlo == 0xFF || rhi != 0x55)){
  533. if(dev == Dev1){
  534. release:
  535. // iofree(cmdport);
  536. // iofree(ctlport+As);
  537. return nil;
  538. }
  539. dev = Dev1;
  540. if(ataready(cmdport, ctlport, dev, Bsy, 0, 20*1000) < 0)
  541. goto trydev1;
  542. }
  543. }
  544. /*
  545. * Disable interrupts on any detected controllers.
  546. */
  547. outb(ctlport+Dc, Nien);
  548. tryedd1:
  549. if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 105*1000) < 0){
  550. /*
  551. * There's something there, but it didn't come up clean,
  552. * so try hitting it with a big stick. The timing here is
  553. * wrong but this is a last-ditch effort and it sometimes
  554. * gets some marginal hardware back online.
  555. */
  556. atasrst(ctlport);
  557. if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 106*1000) < 0)
  558. goto release;
  559. }
  560. /*
  561. * Can only get here if controller is not busy.
  562. * If there are drives Bsy will be set within 400nS,
  563. * must wait 2mS before testing Status.
  564. * Wait for the command to complete (6 seconds max).
  565. */
  566. outb(cmdport+Command, Cedd);
  567. delay(2);
  568. if(ataready(cmdport, ctlport, dev, Bsy|Drq, 0, 6*1000*1000) < 0)
  569. goto release;
  570. /*
  571. * If bit 0 of the error register is set then the selected drive
  572. * exists. This is enough to detect single-drive configurations.
  573. * However, if the master exists there is no way short of executing
  574. * a command to determine if a slave is present.
  575. * It appears possible to get here testing Dev0 although it doesn't
  576. * exist and the EDD won't take, so try again with Dev1.
  577. */
  578. error = inb(cmdport+Error);
  579. atadebug(cmdport, ctlport, "ataprobe: dev %uX", dev);
  580. if((error & ~0x80) != 0x01){
  581. if(dev == Dev1)
  582. goto release;
  583. dev = Dev1;
  584. goto tryedd1;
  585. }
  586. /*
  587. * At least one drive is known to exist, try to
  588. * identify it. If that fails, don't bother checking
  589. * any further.
  590. * If the one drive found is Dev0 and the EDD command
  591. * didn't indicate Dev1 doesn't exist, check for it.
  592. */
  593. if((drive = atadrive(cmdport, ctlport, dev)) == nil)
  594. goto release;
  595. if((ctlr = malloc(sizeof(Ctlr))) == nil){
  596. free(drive);
  597. goto release;
  598. }
  599. if((sdev = malloc(sizeof(SDev))) == nil){
  600. free(ctlr);
  601. free(drive);
  602. goto release;
  603. }
  604. drive->ctlr = ctlr;
  605. if(dev == Dev0){
  606. ctlr->drive[0] = drive;
  607. if(!(error & 0x80)){
  608. /*
  609. * Always leave Dh pointing to a valid drive,
  610. * otherwise a subsequent call to ataready on
  611. * this controller may try to test a bogus Status.
  612. * Ataprobe is the only place possibly invalid
  613. * drives should be selected.
  614. */
  615. drive = atadrive(cmdport, ctlport, Dev1);
  616. if(drive != nil){
  617. drive->ctlr = ctlr;
  618. ctlr->drive[1] = drive;
  619. }
  620. else{
  621. outb(cmdport+Dh, Dev0);
  622. microdelay(1);
  623. }
  624. }
  625. }
  626. else
  627. ctlr->drive[1] = drive;
  628. ctlr->cmdport = cmdport;
  629. ctlr->ctlport = ctlport;
  630. ctlr->irq = irq;
  631. ctlr->tbdf = BUSUNKNOWN;
  632. ctlr->command = Cedd; /* debugging */
  633. sdev->ifc = &sdataifc;
  634. sdev->ctlr = ctlr;
  635. sdev->nunit = 2;
  636. ctlr->sdev = sdev;
  637. return sdev;
  638. }
  639. static int
  640. atasetsense(Drive* drive, int status, int key, int asc, int ascq)
  641. {
  642. drive->sense[2] = key;
  643. drive->sense[12] = asc;
  644. drive->sense[13] = ascq;
  645. return status;
  646. }
  647. static int
  648. atamodesense(Drive* drive, uchar* cmd)
  649. {
  650. int len;
  651. /*
  652. * Fake a vendor-specific request with page code 0,
  653. * return the drive info.
  654. */
  655. if((cmd[2] & 0x3F) != 0 && (cmd[2] & 0x3F) != 0x3F)
  656. return atasetsense(drive, SDcheck, 0x05, 0x24, 0);
  657. len = (cmd[7]<<8)|cmd[8];
  658. if(len == 0)
  659. return SDok;
  660. if(len < 8+sizeof(drive->info))
  661. return atasetsense(drive, SDcheck, 0x05, 0x1A, 0);
  662. if(drive->data == nil || drive->dlen < len)
  663. return atasetsense(drive, SDcheck, 0x05, 0x20, 1);
  664. memset(drive->data, 0, 8);
  665. drive->data[0] = sizeof(drive->info)>>8;
  666. drive->data[1] = sizeof(drive->info);
  667. memmove(drive->data+8, drive->info, sizeof(drive->info));
  668. drive->data += 8+sizeof(drive->info);
  669. return SDok;
  670. }
  671. static void
  672. atanop(Drive* drive, int subcommand)
  673. {
  674. Ctlr* ctlr;
  675. int as, cmdport, ctlport, timeo;
  676. /*
  677. * Attempt to abort a command by using NOP.
  678. * In response, the drive is supposed to set Abrt
  679. * in the Error register, set (Drdy|Err) in Status
  680. * and clear Bsy when done. However, some drives
  681. * (e.g. ATAPI Zip) just go Bsy then clear Status
  682. * when done, hence the timeout loop only on Bsy
  683. * and the forced setting of drive->error.
  684. */
  685. ctlr = drive->ctlr;
  686. cmdport = ctlr->cmdport;
  687. outb(cmdport+Features, subcommand);
  688. outb(cmdport+Dh, drive->dev);
  689. ctlr->command = Cnop; /* debugging */
  690. outb(cmdport+Command, Cnop);
  691. microdelay(1);
  692. ctlport = ctlr->ctlport;
  693. for(timeo = 0; timeo < 1000; timeo++){
  694. as = inb(ctlport+As);
  695. if(!(as & Bsy))
  696. break;
  697. microdelay(1);
  698. }
  699. drive->error |= Abrt;
  700. }
  701. static void
  702. ataabort(Drive* drive, int dolock)
  703. {
  704. /*
  705. * If NOP is available (packet commands) use it otherwise
  706. * must try a software reset.
  707. */
  708. if(dolock)
  709. ilock(drive->ctlr);
  710. if(atacsfenabled(drive, 0x0000000000004000LL))
  711. atanop(drive, 0);
  712. else{
  713. atasrst(drive->ctlr->ctlport);
  714. drive->error |= Abrt;
  715. }
  716. if(dolock)
  717. iunlock(drive->ctlr);
  718. }
  719. static int
  720. atapktiodone(void* arg)
  721. {
  722. return ((Ctlr*)arg)->done;
  723. }
  724. static void
  725. atapktinterrupt(Drive* drive)
  726. {
  727. Ctlr* ctlr;
  728. int cmdport, len;
  729. ctlr = drive->ctlr;
  730. cmdport = ctlr->cmdport;
  731. switch(inb(cmdport+Ir) & (/*Rel|*/Io|Cd)){
  732. case Cd:
  733. outss(cmdport+Data, drive->pktcmd, drive->pkt/2);
  734. break;
  735. case 0:
  736. len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
  737. if(drive->data+len > drive->limit){
  738. atanop(drive, 0);
  739. break;
  740. }
  741. outss(cmdport+Data, drive->data, len/2);
  742. drive->data += len;
  743. break;
  744. case Io:
  745. len = (inb(cmdport+Bytehi)<<8)|inb(cmdport+Bytelo);
  746. if(drive->data+len > drive->limit){
  747. atanop(drive, 0);
  748. break;
  749. }
  750. inss(cmdport+Data, drive->data, len/2);
  751. drive->data += len;
  752. break;
  753. case Io|Cd:
  754. // if(drive->pktdma)
  755. // atadmainterrupt(drive, drive->dlen);
  756. // else
  757. ctlr->done = 1;
  758. break;
  759. }
  760. }
  761. static int
  762. atapktio(Drive* drive, uchar* cmd, int clen)
  763. {
  764. Ctlr *ctlr;
  765. int as, cmdport, ctlport, len, r;
  766. if(cmd[0] == 0x5A && (cmd[2] & 0x3F) == 0)
  767. return atamodesense(drive, cmd);
  768. r = SDok;
  769. drive->command = Cpkt;
  770. memmove(drive->pktcmd, cmd, clen);
  771. memset(drive->pktcmd+clen, 0, drive->pkt-clen);
  772. drive->limit = drive->data+drive->dlen;
  773. ctlr = drive->ctlr;
  774. cmdport = ctlr->cmdport;
  775. ctlport = ctlr->ctlport;
  776. qlock(ctlr);
  777. as = ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 107*1000);
  778. if(as < 0 || (as&Chk)){
  779. qunlock(ctlr);
  780. return -1;
  781. }
  782. ilock(ctlr);
  783. // if(drive->dlen && drive->dmactl && !atadmasetup(drive, drive->dlen))
  784. // drive->pktdma = Dma;
  785. // else
  786. // drive->pktdma = 0;
  787. outb(cmdport+Features, 0/*drive->pktdma*/);
  788. outb(cmdport+Count, 0);
  789. outb(cmdport+Sector, 0);
  790. len = 16*drive->secsize;
  791. outb(cmdport+Bytelo, len);
  792. outb(cmdport+Bytehi, len>>8);
  793. outb(cmdport+Dh, drive->dev);
  794. ctlr->done = 0;
  795. ctlr->curdrive = drive;
  796. ctlr->command = Cpkt; /* debugging */
  797. // if(drive->pktdma)
  798. // atadmastart(ctlr, drive->write);
  799. outb(cmdport+Command, Cpkt);
  800. if((drive->info[Iconfig] & 0x0060) != 0x0020){
  801. microdelay(1);
  802. as = ataready(cmdport, ctlport, 0, Bsy, Drq|Chk, 4*1000);
  803. if(as < 0 || (as & (Bsy|Chk))){
  804. drive->status = as<0 ? 0 : as;
  805. ctlr->curdrive = nil;
  806. ctlr->done = 1;
  807. r = SDtimeout;
  808. }else
  809. atapktinterrupt(drive);
  810. }
  811. iunlock(ctlr);
  812. sleep(ctlr, atapktiodone, ctlr);
  813. qunlock(ctlr);
  814. if(drive->status & Chk)
  815. r = SDcheck;
  816. return r;
  817. }
  818. static int
  819. atageniodone(void* arg)
  820. {
  821. return ((Ctlr*)arg)->done;
  822. }
  823. static uchar cmd48[256] = {
  824. [Crs] Crs48,
  825. [Crd] Crd48,
  826. [Crdq] Crdq48,
  827. [Crsm] Crsm48,
  828. [Cws] Cws48,
  829. [Cwd] Cwd48,
  830. [Cwdq] Cwdq48,
  831. [Cwsm] Cwsm48,
  832. };
  833. static int
  834. atageniostart(Drive* drive, vlong lba)
  835. {
  836. Ctlr *ctlr;
  837. uchar cmd;
  838. int as, c, cmdport, ctlport, h, len, s, use48;
  839. use48 = 0;
  840. if((drive->flags&Lba48always) || (lba>>28) || drive->count > 256){
  841. if(!(drive->flags & Lba48))
  842. return -1;
  843. use48 = 1;
  844. c = h = s = 0;
  845. }else if(drive->dev & Lba){
  846. c = (lba>>8) & 0xFFFF;
  847. h = (lba>>24) & 0x0F;
  848. s = lba & 0xFF;
  849. }
  850. else{
  851. c = lba/(drive->s*drive->h);
  852. h = ((lba/drive->s) % drive->h);
  853. s = (lba % drive->s) + 1;
  854. }
  855. ctlr = drive->ctlr;
  856. cmdport = ctlr->cmdport;
  857. ctlport = ctlr->ctlport;
  858. if(ataready(cmdport, ctlport, drive->dev, Bsy|Drq, 0, 101*1000) < 0)
  859. return -1;
  860. ilock(ctlr);
  861. drive->block = drive->secsize;
  862. if(drive->write)
  863. drive->command = Cws;
  864. else
  865. drive->command = Crs;
  866. drive->limit = drive->data + drive->count*drive->secsize;
  867. cmd = drive->command;
  868. if(use48){
  869. outb(cmdport+Count, (drive->count>>8) & 0xFF);
  870. outb(cmdport+Count, drive->count & 0XFF);
  871. outb(cmdport+Lbalo, (lba>>24) & 0xFF);
  872. outb(cmdport+Lbalo, lba & 0xFF);
  873. outb(cmdport+Lbamid, (lba>>32) & 0xFF);
  874. outb(cmdport+Lbamid, (lba>>8) & 0xFF);
  875. outb(cmdport+Lbahi, (lba>>40) & 0xFF);
  876. outb(cmdport+Lbahi, (lba>>16) & 0xFF);
  877. outb(cmdport+Dh, drive->dev|Lba);
  878. cmd = cmd48[cmd];
  879. if(DEBUG & Dbg48BIT)
  880. print("using 48-bit commands\n");
  881. }else{
  882. outb(cmdport+Count, drive->count);
  883. outb(cmdport+Sector, s);
  884. outb(cmdport+Cyllo, c);
  885. outb(cmdport+Cylhi, c>>8);
  886. outb(cmdport+Dh, drive->dev|h);
  887. }
  888. ctlr->done = 0;
  889. ctlr->curdrive = drive;
  890. ctlr->command = drive->command; /* debugging */
  891. outb(cmdport+Command, cmd);
  892. switch(drive->command){
  893. case Cws:
  894. case Cwsm:
  895. microdelay(1);
  896. as = ataready(cmdport, ctlport, 0, Bsy, Drq|Err, 1000);
  897. if(as < 0 || (as & Err)){
  898. iunlock(ctlr);
  899. return -1;
  900. }
  901. len = drive->block;
  902. if(drive->data+len > drive->limit)
  903. len = drive->limit-drive->data;
  904. outss(cmdport+Data, drive->data, len/2);
  905. break;
  906. case Crd:
  907. case Cwd:
  908. // atadmastart(ctlr, drive->write);
  909. break;
  910. }
  911. iunlock(ctlr);
  912. return 0;
  913. }
  914. static int
  915. atagenioretry(Drive* drive)
  916. {
  917. return atasetsense(drive, SDcheck, 4, 8, drive->error);
  918. }
  919. static int
  920. atagenio(Drive* drive, uchar* cmd, int)
  921. {
  922. uchar *p;
  923. Ctlr *ctlr;
  924. int count, max;
  925. vlong lba, len;
  926. /*
  927. * Map SCSI commands into ATA commands for discs.
  928. * Fail any command with a LUN except INQUIRY which
  929. * will return 'logical unit not supported'.
  930. */
  931. if((cmd[1]>>5) && cmd[0] != 0x12)
  932. return atasetsense(drive, SDcheck, 0x05, 0x25, 0);
  933. switch(cmd[0]){
  934. default:
  935. return atasetsense(drive, SDcheck, 0x05, 0x20, 0);
  936. case 0x00: /* test unit ready */
  937. return SDok;
  938. case 0x03: /* request sense */
  939. if(cmd[4] < sizeof(drive->sense))
  940. len = cmd[4];
  941. else
  942. len = sizeof(drive->sense);
  943. if(drive->data && drive->dlen >= len){
  944. memmove(drive->data, drive->sense, len);
  945. drive->data += len;
  946. }
  947. return SDok;
  948. case 0x12: /* inquiry */
  949. if(cmd[4] < sizeof(drive->inquiry))
  950. len = cmd[4];
  951. else
  952. len = sizeof(drive->inquiry);
  953. if(drive->data && drive->dlen >= len){
  954. memmove(drive->data, drive->inquiry, len);
  955. drive->data += len;
  956. }
  957. return SDok;
  958. case 0x1B: /* start/stop unit */
  959. /*
  960. * NOP for now, can use the power management feature
  961. * set later.
  962. */
  963. return SDok;
  964. case 0x25: /* read capacity */
  965. if((cmd[1] & 0x01) || cmd[2] || cmd[3])
  966. return atasetsense(drive, SDcheck, 0x05, 0x24, 0);
  967. if(drive->data == nil || drive->dlen < 8)
  968. return atasetsense(drive, SDcheck, 0x05, 0x20, 1);
  969. /*
  970. * Read capacity returns the LBA of the last sector.
  971. */
  972. len = drive->sectors-1;
  973. p = drive->data;
  974. *p++ = len>>24;
  975. *p++ = len>>16;
  976. *p++ = len>>8;
  977. *p++ = len;
  978. len = drive->secsize;
  979. *p++ = len>>24;
  980. *p++ = len>>16;
  981. *p++ = len>>8;
  982. *p = len;
  983. drive->data += 8;
  984. return SDok;
  985. case 0x9E: /* long read capacity */
  986. if((cmd[1] & 0x01) || cmd[2] || cmd[3])
  987. return atasetsense(drive, SDcheck, 0x05, 0x24, 0);
  988. if(drive->data == nil || drive->dlen < 8)
  989. return atasetsense(drive, SDcheck, 0x05, 0x20, 1);
  990. /*
  991. * Read capacity returns the LBA of the last sector.
  992. */
  993. len = drive->sectors-1;
  994. p = drive->data;
  995. *p++ = len>>56;
  996. *p++ = len>>48;
  997. *p++ = len>>40;
  998. *p++ = len>>32;
  999. *p++ = len>>24;
  1000. *p++ = len>>16;
  1001. *p++ = len>>8;
  1002. *p++ = len;
  1003. len = drive->secsize;
  1004. *p++ = len>>24;
  1005. *p++ = len>>16;
  1006. *p++ = len>>8;
  1007. *p = len;
  1008. drive->data += 8;
  1009. return SDok;
  1010. case 0x28: /* read */
  1011. case 0x2A: /* write */
  1012. break;
  1013. case 0x5A:
  1014. return atamodesense(drive, cmd);
  1015. }
  1016. ctlr = drive->ctlr;
  1017. lba = (cmd[2]<<24)|(cmd[3]<<16)|(cmd[4]<<8)|cmd[5];
  1018. count = (cmd[7]<<8)|cmd[8];
  1019. if(drive->data == nil)
  1020. return SDok;
  1021. if(drive->dlen < count*drive->secsize)
  1022. count = drive->dlen/drive->secsize;
  1023. qlock(ctlr);
  1024. while(count){
  1025. max = (drive->flags&Lba48) ? 65536 : 256;
  1026. if(count > max)
  1027. drive->count = max;
  1028. else
  1029. drive->count = count;
  1030. if(atageniostart(drive, lba)){
  1031. ilock(ctlr);
  1032. atanop(drive, 0);
  1033. iunlock(ctlr);
  1034. qunlock(ctlr);
  1035. return atagenioretry(drive);
  1036. }
  1037. tsleep(ctlr, atageniodone, ctlr, 10*1000);
  1038. if(!ctlr->done){
  1039. /*
  1040. * What should the above timeout be? In
  1041. * standby and sleep modes it could take as
  1042. * long as 30 seconds for a drive to respond.
  1043. * Very hard to get out of this cleanly.
  1044. */
  1045. // atadumpstate(drive, cmd, lba, count);
  1046. ataabort(drive, 1);
  1047. return atagenioretry(drive);
  1048. }
  1049. if(drive->status & Err){
  1050. qunlock(ctlr);
  1051. return atasetsense(drive, SDcheck, 4, 8, drive->error);
  1052. }
  1053. count -= drive->count;
  1054. lba += drive->count;
  1055. }
  1056. qunlock(ctlr);
  1057. return SDok;
  1058. }
  1059. static int
  1060. atario(SDreq* r)
  1061. {
  1062. Ctlr *ctlr;
  1063. Drive *drive;
  1064. SDunit *unit;
  1065. uchar cmd10[10], *cmdp, *p;
  1066. int clen, reqstatus, status;
  1067. unit = r->unit;
  1068. if((ctlr = unit->dev->ctlr) == nil || ctlr->drive[unit->subno] == nil){
  1069. r->status = SDtimeout;
  1070. return SDtimeout;
  1071. }
  1072. drive = ctlr->drive[unit->subno];
  1073. /*
  1074. * Most SCSI commands can be passed unchanged except for
  1075. * the padding on the end. The few which require munging
  1076. * are not used internally. Mode select/sense(6) could be
  1077. * converted to the 10-byte form but it's not worth the
  1078. * effort. Read/write(6) are easy.
  1079. */
  1080. switch(r->cmd[0]){
  1081. case 0x08: /* read */
  1082. case 0x0A: /* write */
  1083. cmdp = cmd10;
  1084. memset(cmdp, 0, sizeof(cmd10));
  1085. cmdp[0] = r->cmd[0]|0x20;
  1086. cmdp[1] = r->cmd[1] & 0xE0;
  1087. cmdp[5] = r->cmd[3];
  1088. cmdp[4] = r->cmd[2];
  1089. cmdp[3] = r->cmd[1] & 0x0F;
  1090. cmdp[8] = r->cmd[4];
  1091. clen = sizeof(cmd10);
  1092. break;
  1093. default:
  1094. cmdp = r->cmd;
  1095. clen = r->clen;
  1096. break;
  1097. }
  1098. qlock(drive);
  1099. drive->write = r->write;
  1100. drive->data = r->data;
  1101. drive->dlen = r->dlen;
  1102. drive->status = 0;
  1103. drive->error = 0;
  1104. if(drive->pkt)
  1105. status = atapktio(drive, cmdp, clen);
  1106. else
  1107. status = atagenio(drive, cmdp, clen);
  1108. if(status == SDok){
  1109. atasetsense(drive, SDok, 0, 0, 0);
  1110. if(drive->data){
  1111. p = r->data;
  1112. r->rlen = drive->data - p;
  1113. }
  1114. else
  1115. r->rlen = 0;
  1116. }
  1117. else if(status == SDcheck && !(r->flags & SDnosense)){
  1118. drive->write = 0;
  1119. memset(cmd10, 0, sizeof(cmd10));
  1120. cmd10[0] = 0x03;
  1121. cmd10[1] = r->lun<<5;
  1122. cmd10[4] = sizeof(r->sense)-1;
  1123. drive->data = r->sense;
  1124. drive->dlen = sizeof(r->sense)-1;
  1125. drive->status = 0;
  1126. drive->error = 0;
  1127. if(drive->pkt)
  1128. reqstatus = atapktio(drive, cmd10, 6);
  1129. else
  1130. reqstatus = atagenio(drive, cmd10, 6);
  1131. if(reqstatus == SDok){
  1132. r->flags |= SDvalidsense;
  1133. atasetsense(drive, SDok, 0, 0, 0);
  1134. }
  1135. }
  1136. qunlock(drive);
  1137. r->status = status;
  1138. if(status != SDok)
  1139. return status;
  1140. /*
  1141. * Fix up any results.
  1142. * Many ATAPI CD-ROMs ignore the LUN field completely and
  1143. * return valid INQUIRY data. Patch the response to indicate
  1144. * 'logical unit not supported' if the LUN is non-zero.
  1145. */
  1146. switch(cmdp[0]){
  1147. case 0x12: /* inquiry */
  1148. if((p = r->data) == nil)
  1149. break;
  1150. if((cmdp[1]>>5) && (!drive->pkt || (p[0] & 0x1F) == 0x05))
  1151. p[0] = 0x7F;
  1152. /*FALLTHROUGH*/
  1153. default:
  1154. break;
  1155. }
  1156. return SDok;
  1157. }
  1158. static void
  1159. atainterrupt(Ureg*, void* arg)
  1160. {
  1161. Ctlr *ctlr;
  1162. Drive *drive;
  1163. int cmdport, len, status;
  1164. ctlr = arg;
  1165. ilock(ctlr);
  1166. if(inb(ctlr->ctlport+As) & Bsy){
  1167. iunlock(ctlr);
  1168. if(DEBUG & DbgBsy)
  1169. print("IBsy+");
  1170. return;
  1171. }
  1172. cmdport = ctlr->cmdport;
  1173. status = inb(cmdport+Status);
  1174. if((drive = ctlr->curdrive) == nil){
  1175. iunlock(ctlr);
  1176. if((DEBUG & DbgINL) && ctlr->command != Cedd)
  1177. print("Inil%2.2uX+", ctlr->command);
  1178. return;
  1179. }
  1180. if(status & Err)
  1181. drive->error = inb(cmdport+Error);
  1182. else switch(drive->command){
  1183. default:
  1184. drive->error = Abrt;
  1185. break;
  1186. case Crs:
  1187. case Crsm:
  1188. if(!(status & Drq)){
  1189. drive->error = Abrt;
  1190. break;
  1191. }
  1192. len = drive->block;
  1193. if(drive->data+len > drive->limit)
  1194. len = drive->limit-drive->data;
  1195. inss(cmdport+Data, drive->data, len/2);
  1196. drive->data += len;
  1197. if(drive->data >= drive->limit)
  1198. ctlr->done = 1;
  1199. break;
  1200. case Cws:
  1201. case Cwsm:
  1202. len = drive->block;
  1203. if(drive->data+len > drive->limit)
  1204. len = drive->limit-drive->data;
  1205. drive->data += len;
  1206. if(drive->data >= drive->limit){
  1207. ctlr->done = 1;
  1208. break;
  1209. }
  1210. if(!(status & Drq)){
  1211. drive->error = Abrt;
  1212. break;
  1213. }
  1214. len = drive->block;
  1215. if(drive->data+len > drive->limit)
  1216. len = drive->limit-drive->data;
  1217. outss(cmdport+Data, drive->data, len/2);
  1218. break;
  1219. case Cpkt:
  1220. atapktinterrupt(drive);
  1221. break;
  1222. case Crd:
  1223. case Cwd:
  1224. // atadmainterrupt(drive, drive->count*drive->secsize);
  1225. break;
  1226. }
  1227. iunlock(ctlr);
  1228. if(drive->error){
  1229. status |= Err;
  1230. ctlr->done = 1;
  1231. }
  1232. if(ctlr->done){
  1233. ctlr->curdrive = nil;
  1234. drive->status = status;
  1235. wakeup(ctlr);
  1236. }
  1237. }
  1238. static SDev*
  1239. atapnp(void)
  1240. {
  1241. Ctlr *ctlr;
  1242. Pcidev *p;
  1243. int channel, ispc87415, pi, r;
  1244. SDev *legacy[2], *sdev, *head, *tail;
  1245. legacy[0] = legacy[1] = head = tail = nil;
  1246. if(sdev = ataprobe(0x1F0, 0x3F4, IrqATA0)){
  1247. head = tail = sdev;
  1248. legacy[0] = sdev;
  1249. }
  1250. if(sdev = ataprobe(0x170, 0x374, IrqATA1)){
  1251. if(head != nil)
  1252. tail->next = sdev;
  1253. else
  1254. head = sdev;
  1255. tail = sdev;
  1256. legacy[1] = sdev;
  1257. }
  1258. p = nil;
  1259. while(p = pcimatch(p, 0, 0)){
  1260. /*
  1261. * Look for devices with the correct class and sub-class
  1262. * code and known device and vendor ID; add native-mode
  1263. * channels to the list to be probed, save info for the
  1264. * compatibility mode channels.
  1265. * Note that the legacy devices should not be considered
  1266. * PCI devices by the interrupt controller.
  1267. * For both native and legacy, save info for busmastering
  1268. * if capable.
  1269. * Promise Ultra ATA/66 (PDC20262) appears to
  1270. * 1) give a sub-class of 'other mass storage controller'
  1271. * instead of 'IDE controller', regardless of whether it's
  1272. * the only controller or not;
  1273. * 2) put 0 in the programming interface byte (probably
  1274. * as a consequence of 1) above).
  1275. * Sub-class code 0x04 is 'RAID controller', e.g. VIA VT8237.
  1276. */
  1277. if(p->ccrb != 0x01)
  1278. continue;
  1279. if(p->ccru != 0x01 && p->ccru != 0x04 && p->ccru != 0x80)
  1280. continue;
  1281. pi = p->ccrp;
  1282. ispc87415 = 0;
  1283. switch((p->did<<16)|p->vid){
  1284. default:
  1285. continue;
  1286. case (0x0002<<16)|0x100B: /* NS PC87415 */
  1287. /*
  1288. * Disable interrupts on both channels until
  1289. * after they are probed for drives.
  1290. * This must be called before interrupts are
  1291. * enabled because the IRQ may be shared.
  1292. */
  1293. ispc87415 = 1;
  1294. pcicfgw32(p, 0x40, 0x00000300);
  1295. break;
  1296. case (0x1000<<16)|0x1042: /* PC-Tech RZ1000 */
  1297. /*
  1298. * Turn off prefetch. Overkill, but cheap.
  1299. */
  1300. r = pcicfgr32(p, 0x40);
  1301. r &= ~0x2000;
  1302. pcicfgw32(p, 0x40, r);
  1303. break;
  1304. case (0x4D38<<16)|0x105A: /* Promise PDC20262 */
  1305. case (0x4D30<<16)|0x105A: /* Promise PDC202xx */
  1306. case (0x4D68<<16)|0x105A: /* Promise PDC20268 */
  1307. case (0x4D69<<16)|0x105A: /* Promise Ultra/133 TX2 */
  1308. case (0x3373<<16)|0x105A: /* Promise 20378 RAID */
  1309. case (0x3149<<16)|0x1106: /* VIA VT8237 SATA/RAID */
  1310. case (0x4379<<16)|0x1002: /* ATI 4379 SATA*/
  1311. case (0x3112<<16)|0x1095: /* SiL 3112 SATA (DMA busted?) */
  1312. case (0x3114<<16)|0x1095: /* SiL 3114 SATA/RAID */
  1313. pi = 0x85;
  1314. break;
  1315. case (0x0004<<16)|0x1103: /* HighPoint HPT-370 */
  1316. pi = 0x85;
  1317. /*
  1318. * Turn off fast interrupt prediction.
  1319. */
  1320. if((r = pcicfgr8(p, 0x51)) & 0x80)
  1321. pcicfgw8(p, 0x51, r & ~0x80);
  1322. if((r = pcicfgr8(p, 0x55)) & 0x80)
  1323. pcicfgw8(p, 0x55, r & ~0x80);
  1324. break;
  1325. case (0x0640<<16)|0x1095: /* CMD 640B */
  1326. /*
  1327. * Bugfix code here...
  1328. */
  1329. break;
  1330. case (0x7441<<16)|0x1022: /* AMD 768 */
  1331. /*
  1332. * Set:
  1333. * 0x41 prefetch, postwrite;
  1334. * 0x43 FIFO configuration 1/2 and 1/2;
  1335. * 0x44 status register read retry;
  1336. * 0x46 DMA read and end of sector flush.
  1337. */
  1338. r = pcicfgr8(p, 0x41);
  1339. pcicfgw8(p, 0x41, r|0xF0);
  1340. r = pcicfgr8(p, 0x43);
  1341. pcicfgw8(p, 0x43, (r & 0x90)|0x2A);
  1342. r = pcicfgr8(p, 0x44);
  1343. pcicfgw8(p, 0x44, r|0x08);
  1344. r = pcicfgr8(p, 0x46);
  1345. pcicfgw8(p, 0x46, (r & 0x0C)|0xF0);
  1346. /*FALLTHROUGH*/
  1347. case (0x7469<<16)|0x1022: /* AMD 3111 */
  1348. /*
  1349. * This can probably be lumped in with the 768 above.
  1350. */
  1351. /*FALLTHROUGH*/
  1352. case (0x209A<<16)|0x1022: /* AMD CS5536 */
  1353. case (0x01BC<<16)|0x10DE: /* nVidia nForce1 */
  1354. case (0x0065<<16)|0x10DE: /* nVidia nForce2 */
  1355. case (0x0085<<16)|0x10DE: /* nVidia nForce2 MCP */
  1356. case (0x00D5<<16)|0x10DE: /* nVidia nForce3 */
  1357. case (0x00E5<<16)|0x10DE: /* nVidia nForce3 Pro */
  1358. case (0x0035<<16)|0x10DE: /* nVidia nForce3 MCP */
  1359. case (0x0053<<16)|0x10DE: /* nVidia nForce4 */
  1360. case (0x0054<<16)|0x10DE: /* nVidia nForce4 SATA */
  1361. case (0x0055<<16)|0x10DE: /* nVidia nForce4 SATA */
  1362. /*
  1363. * Ditto, although it may have a different base
  1364. * address for the registers (0x50?).
  1365. */
  1366. break;
  1367. case (0x0646<<16)|0x1095: /* CMD 646 */
  1368. case (0x0571<<16)|0x1106: /* VIA 82C686 */
  1369. case (0x0211<<16)|0x1166: /* ServerWorks IB6566 */
  1370. case (0x1230<<16)|0x8086: /* 82371FB (PIIX) */
  1371. case (0x7010<<16)|0x8086: /* 82371SB (PIIX3) */
  1372. case (0x7111<<16)|0x8086: /* 82371[AE]B (PIIX4[E]) */
  1373. case (0x2411<<16)|0x8086: /* 82801AA (ICH) */
  1374. case (0x2421<<16)|0x8086: /* 82801AB (ICH0) */
  1375. case (0x244A<<16)|0x8086: /* 82801BA (ICH2, Mobile) */
  1376. case (0x244B<<16)|0x8086: /* 82801BA (ICH2, High-End) */
  1377. case (0x248A<<16)|0x8086: /* 82801CA (ICH3, Mobile) */
  1378. case (0x248B<<16)|0x8086: /* 82801CA (ICH3, High-End) */
  1379. case (0x24CA<<16)|0x8086: /* 82801DBM (ICH4, Mobile) */
  1380. case (0x24CB<<16)|0x8086: /* 82801DB (ICH4, High-End) */
  1381. case (0x24DB<<16)|0x8086: /* 82801EB (ICH5) */
  1382. case (0x266F<<16)|0x8086: /* 82801FB (ICH6) */
  1383. case (0x27DF<<16)|0x8086: /* 82801G SATA (ICH7) */
  1384. case (0x27C0<<16)|0x8086: /* 82801GB SATA AHCI (ICH7) */
  1385. case (0x27C4<<16)|0x8086: /* 82801GBM SATA (ICH7) */
  1386. case (0x27C5<<16)|0x8086: /* 82801GBM SATA AHCI (ICH7) */
  1387. break;
  1388. }
  1389. for(channel = 0; channel < 2; channel++){
  1390. if(pi & (1<<(2*channel))){
  1391. sdev = ataprobe(p->mem[0+2*channel].bar & ~0x01,
  1392. p->mem[1+2*channel].bar & ~0x01,
  1393. p->intl);
  1394. if(sdev == nil)
  1395. continue;
  1396. ctlr = sdev->ctlr;
  1397. if(ispc87415)
  1398. ctlr->ienable = pc87415ienable;
  1399. if(head != nil)
  1400. tail->next = sdev;
  1401. else
  1402. head = sdev;
  1403. tail = sdev;
  1404. ctlr->tbdf = p->tbdf;
  1405. }
  1406. else if((sdev = legacy[channel]) == nil)
  1407. continue;
  1408. else
  1409. ctlr = sdev->ctlr;
  1410. ctlr->pcidev = p;
  1411. }
  1412. }
  1413. return head;
  1414. }
  1415. static SDev*
  1416. atalegacy(int port, int irq)
  1417. {
  1418. return ataprobe(port, port+0x204, irq);
  1419. }
  1420. static SDev*
  1421. ataid(SDev* sdev)
  1422. {
  1423. int i;
  1424. Ctlr *ctlr;
  1425. /*
  1426. * Legacy controllers are always 'C' and 'D' and if
  1427. * they exist and have drives will be first in the list.
  1428. * If there are no active legacy controllers, native
  1429. * controllers start at 'C'.
  1430. */
  1431. if(sdev == nil)
  1432. return nil;
  1433. ctlr = sdev->ctlr;
  1434. if(ctlr->cmdport == 0x1F0 || ctlr->cmdport == 0x170)
  1435. i = 2;
  1436. else
  1437. i = 0;
  1438. while(sdev){
  1439. if(sdev->ifc == &sdataifc){
  1440. ctlr = sdev->ctlr;
  1441. if(ctlr->cmdport == 0x1F0)
  1442. sdev->idno = 'C';
  1443. else if(ctlr->cmdport == 0x170)
  1444. sdev->idno = 'D';
  1445. else{
  1446. sdev->idno = 'C'+i;
  1447. i++;
  1448. }
  1449. // snprint(sdev->name, NAMELEN, "sd%c", sdev->idno);
  1450. }
  1451. sdev = sdev->next;
  1452. }
  1453. return nil;
  1454. }
  1455. static int
  1456. ataenable(SDev* sdev)
  1457. {
  1458. Ctlr *ctlr;
  1459. ctlr = sdev->ctlr;
  1460. setvec(ctlr->irq+VectorPIC, atainterrupt, ctlr);
  1461. outb(ctlr->ctlport+Dc, 0);
  1462. if(ctlr->ienable)
  1463. ctlr->ienable(ctlr);
  1464. return 1;
  1465. }
  1466. SDifc sdataifc = {
  1467. "ata", /* name */
  1468. atapnp, /* pnp */
  1469. atalegacy, /* legacy */
  1470. ataid, /* id */
  1471. ataenable, /* enable */
  1472. nil, /* disable */
  1473. scsiverify, /* verify */
  1474. scsionline, /* online */
  1475. atario, /* rio */
  1476. nil, /* rctl */
  1477. nil, /* wctl */
  1478. scsibio, /* bio */
  1479. };