sdiahci.c 28 KB

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  1. /*
  2. * intel/amd ahci (advanced host controller interface) sata controller
  3. * bootstrap driver
  4. * copyright © 2007, 2008 coraid, inc.
  5. */
  6. #include "u.h"
  7. #include "lib.h"
  8. #include "mem.h"
  9. #include "dat.h"
  10. #include "fns.h"
  11. #include "io.h"
  12. #include "error.h"
  13. #include "sd.h"
  14. #include "ahci.h"
  15. #define dprint(...) if(debug == 1) print(__VA_ARGS__); else USED(debug)
  16. #define idprint(...) if(prid == 1) print(__VA_ARGS__); else USED(prid)
  17. #define aprint(...) if(datapi == 1) print(__VA_ARGS__); else USED(datapi)
  18. enum {
  19. NCtlr = 2,
  20. NCtlrdrv= 8,
  21. NDrive = NCtlr*NCtlrdrv,
  22. Read = 0,
  23. Write
  24. };
  25. /* pci space configurtion */
  26. enum {
  27. Pmap = 0x90,
  28. Ppcs = 0x91,
  29. Prev = 0xa8,
  30. };
  31. enum {
  32. Tesb,
  33. Tich,
  34. Tsb600,
  35. };
  36. #define Intel(x) ((x) == Tesb || (x) == Tich)
  37. static char *tname[] = {
  38. "63xxesb",
  39. "ich",
  40. "sb600",
  41. };
  42. enum {
  43. Dnull,
  44. Dmissing,
  45. Dnew,
  46. Dready,
  47. Derror,
  48. Dreset,
  49. Doffline,
  50. Dportreset,
  51. Dlast
  52. };
  53. static char *diskstates[Dlast] = {
  54. "null",
  55. "missing",
  56. "new",
  57. "ready",
  58. "error",
  59. "reset",
  60. "offline",
  61. "portreset",
  62. };
  63. extern SDifc sdiahciifc;
  64. typedef struct Ctlr Ctlr;
  65. enum {
  66. DMautoneg,
  67. DMsatai,
  68. DMsataii,
  69. };
  70. static char *modename[] = {
  71. "auto",
  72. "satai",
  73. "sataii",
  74. };
  75. typedef struct {
  76. Lock;
  77. Ctlr *ctlr;
  78. SDunit *unit;
  79. char name[10];
  80. Aport *port;
  81. Aportm portm;
  82. Aportc portc; /* redundant ptr to port and portm. */
  83. uchar mediachange;
  84. uchar state;
  85. uchar smartrs;
  86. uvlong sectors;
  87. ulong intick;
  88. int wait;
  89. uchar mode; /* DMautoneg, satai or sataii. */
  90. uchar active;
  91. char serial[20+1];
  92. char firmware[8+1];
  93. char model[40+1];
  94. ushort info[0x200];
  95. int driveno; /* ctlr*NCtlrdrv + unit */
  96. int portno; /* ctlr port # != drive # when not all ports enabled. */
  97. } Drive;
  98. struct Ctlr {
  99. Lock;
  100. int type;
  101. int enabled;
  102. SDev *sdev;
  103. Pcidev *pci;
  104. uchar *mmio;
  105. ulong *lmmio;
  106. Ahba *hba;
  107. Drive rawdrive[NCtlrdrv];
  108. Drive* drive[NCtlrdrv];
  109. int ndrive;
  110. };
  111. static Ctlr iactlr[NCtlr];
  112. static SDev sdevs[NCtlr];
  113. static int niactlr;
  114. static int prid = 0;
  115. static int datapi = 0;
  116. static char stab[] = {
  117. [0] 'i', 'm',
  118. [8] 't', 'c', 'p', 'e',
  119. [16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  120. };
  121. static void
  122. serrstr(ulong r, char *s, char *e)
  123. {
  124. int i;
  125. e -= 3;
  126. for(i = 0; i < nelem(stab) && s < e; i++)
  127. if((r & (1<<i)) && stab[i]){
  128. *s++ = stab[i];
  129. if(SerrBad & (1<<i))
  130. *s++ = '*';
  131. }
  132. *s = 0;
  133. }
  134. static char ntab[] = "0123456789abcdef";
  135. static void
  136. preg(uchar *reg, int n)
  137. {
  138. int i;
  139. char buf[25*3+1], *e;
  140. e = buf;
  141. for(i = 0; i < n; i++){
  142. *e++ = ntab[reg[i] >> 4];
  143. *e++ = ntab[reg[i] & 0xf];
  144. *e++ = ' ';
  145. }
  146. *e++ = '\n';
  147. *e = 0;
  148. dprint(buf);
  149. }
  150. static void
  151. dreg(char *s, Aport *p)
  152. {
  153. dprint("%stask=%lux; cmd=%lux; ci=%lux; is=%lux\n",
  154. s, p->task, p->cmd, p->ci, p->isr);
  155. }
  156. static void
  157. esleep(int ms)
  158. {
  159. delay(ms);
  160. }
  161. typedef struct {
  162. Aport *p;
  163. int i;
  164. } Asleep;
  165. static int
  166. ahciclear(void *v)
  167. {
  168. Asleep *s;
  169. s = v;
  170. return (s->p->ci & s->i) == 0;
  171. }
  172. static void
  173. aesleep(Aportm *, Asleep *a, int ms)
  174. {
  175. ulong start;
  176. start = m->ticks;
  177. while((a->p->ci & a->i) != 0)
  178. if(TK2MS(m->ticks-start) >= ms)
  179. break;
  180. }
  181. static int
  182. ahciwait(Aportc *c, int ms)
  183. {
  184. Aport *p;
  185. Asleep as;
  186. p = c->p;
  187. p->ci = 1;
  188. as.p = p;
  189. as.i = 1;
  190. aesleep(c->m, &as, ms);
  191. if((p->task & 1) == 0 && p->ci == 0)
  192. return 0;
  193. dreg("ahciwait timeout ", c->p);
  194. return -1;
  195. }
  196. static int
  197. setfeatures(Aportc *pc, uchar f)
  198. {
  199. uchar *c;
  200. Actab *t;
  201. Alist *l;
  202. t = pc->m->ctab;
  203. c = t->cfis;
  204. memset(c, 0, 0x20);
  205. c[0] = 0x27;
  206. c[1] = 0x80;
  207. c[2] = 0xef;
  208. c[3] = f;
  209. c[7] = 0xa0; /* obsolete device bits */
  210. l = pc->m->list;
  211. l->flags = Lwrite|0x5;
  212. l->len = 0;
  213. l->ctab = PCIWADDR(t);
  214. l->ctabhi = 0;
  215. return ahciwait(pc, 3*1000);
  216. }
  217. static int
  218. setudmamode(Aportc *pc, uchar f)
  219. {
  220. uchar *c;
  221. Actab *t;
  222. Alist *l;
  223. t = pc->m->ctab;
  224. c = t->cfis;
  225. memset(c, 0, 0x20);
  226. c[0] = 0x27;
  227. c[1] = 0x80;
  228. c[2] = 0xef;
  229. c[3] = 3; /* set transfer mode */
  230. c[7] = 0xa0; /* obsolete device bits */
  231. c[12] = 0x40 | f; /* sector count */
  232. l = pc->m->list;
  233. l->flags = Lwrite | 0x5;
  234. l->len = 0;
  235. l->ctab = PCIWADDR(t);
  236. l->ctabhi = 0;
  237. return ahciwait(pc, 3*1000);
  238. }
  239. static void
  240. asleep(int ms)
  241. {
  242. delay(ms);
  243. }
  244. static int
  245. ahciportreset(Aportc *c)
  246. {
  247. ulong *cmd, i;
  248. Aport *p;
  249. p = c->p;
  250. cmd = &p->cmd;
  251. *cmd &= ~(Afre|Ast);
  252. for(i = 0; i < 500; i += 25){
  253. if((*cmd & Acr) == 0)
  254. break;
  255. asleep(25);
  256. }
  257. p->sctl = 1 | (p->sctl & ~7);
  258. delay(1);
  259. p->sctl &= ~7;
  260. return 0;
  261. }
  262. static ushort
  263. gbit16(void *a)
  264. {
  265. uchar *i;
  266. i = a;
  267. return i[1]<<8 | i[0];
  268. }
  269. static ulong
  270. gbit32(void *a)
  271. {
  272. ulong j;
  273. uchar *i;
  274. i = a;
  275. j = i[3] << 24;
  276. j |= i[2] << 16;
  277. j |= i[1] << 8;
  278. j |= i[0];
  279. return j;
  280. }
  281. static uvlong
  282. gbit64(void *a)
  283. {
  284. uchar *i;
  285. i = a;
  286. return (uvlong) gbit32(i+4)<<32 | gbit32(a);
  287. }
  288. static int
  289. ahciidentify0(Aportc *pc, void *id, int atapi)
  290. {
  291. uchar *c;
  292. Actab *t;
  293. Alist *l;
  294. Aprdt *p;
  295. static uchar tab[] = { 0xec, 0xa1 };
  296. t = pc->m->ctab;
  297. c = t->cfis;
  298. memset(c, 0, 0x20);
  299. c[0] = 0x27;
  300. c[1] = 0x80;
  301. c[2] = tab[atapi];
  302. c[7] = 0xa0; /* obsolete device bits */
  303. l = pc->m->list;
  304. l->flags = 1<<16 | 0x5;
  305. l->len = 0;
  306. l->ctab = PCIWADDR(t);
  307. l->ctabhi = 0;
  308. memset(id, 0, 0x100);
  309. p = &t->prdt;
  310. p->dba = PCIWADDR(id);
  311. p->dbahi = 0;
  312. p->count = 1<<31 | (0x200-2) | 1;
  313. return ahciwait(pc, 3*1000);
  314. }
  315. static vlong
  316. ahciidentify(Aportc *pc, ushort *id)
  317. {
  318. int i, sig;
  319. vlong s;
  320. Aportm *m;
  321. m = pc->m;
  322. m->feat = 0;
  323. m->smart = 0;
  324. i = 0;
  325. sig = pc->p->sig >> 16;
  326. if(sig == 0xeb14){
  327. m->feat |= Datapi;
  328. i = 1;
  329. }
  330. if(ahciidentify0(pc, id, i) == -1)
  331. return -1;
  332. i = gbit16(id+83) | gbit16(id+86);
  333. if(i & (1<<10)){
  334. m->feat |= Dllba;
  335. s = gbit64(id+100);
  336. }else
  337. s = gbit32(id+60);
  338. if(m->feat & Datapi){
  339. i = gbit16(id+0);
  340. if(i & 1)
  341. m->feat |= Datapi16;
  342. }
  343. i = gbit16(id+83);
  344. if((i>>14) != 1)
  345. return s;
  346. if(i & (1<<3))
  347. m->feat |= Dpower;
  348. i = gbit16(id+82);
  349. if(i & 1)
  350. m->feat |= Dsmart;
  351. if(i & (1<<14))
  352. m->feat |= Dnop;
  353. return s;
  354. }
  355. static int
  356. ahciquiet(Aport *a)
  357. {
  358. ulong *p, i;
  359. p = &a->cmd;
  360. *p &= ~Ast;
  361. for(i = 0; i < 500; i += 50){
  362. if((*p & Acr) == 0)
  363. goto stop;
  364. asleep(50);
  365. }
  366. return -1;
  367. stop:
  368. if((a->task & (ASdrq|ASbsy)) == 0){
  369. *p |= Ast;
  370. return 0;
  371. }
  372. *p |= Aclo;
  373. for(i = 0; i < 500; i += 50){
  374. if((*p & Aclo) == 0)
  375. goto stop1;
  376. asleep(50);
  377. }
  378. return -1;
  379. stop1:
  380. /* extra check */
  381. dprint("clo clear %lx\n", a->task);
  382. if(a->task & ASbsy)
  383. return -1;
  384. *p |= Ast;
  385. return 0;
  386. }
  387. static int
  388. ahciidle(Aport *port)
  389. {
  390. ulong *p, i, r;
  391. p = &port->cmd;
  392. if((*p & Arun) == 0)
  393. return 0;
  394. *p &= ~Ast;
  395. r = 0;
  396. for(i = 0; i < 500; i += 25){
  397. if((*p & Acr) == 0)
  398. goto stop;
  399. asleep(25);
  400. }
  401. r = -1;
  402. stop:
  403. if((*p & Afre) == 0)
  404. return r;
  405. *p &= ~Afre;
  406. for(i = 0; i < 500; i += 25){
  407. if((*p & Afre) == 0)
  408. return 0;
  409. asleep(25);
  410. }
  411. return -1;
  412. }
  413. /*
  414. * §6.2.2.1 first part; comreset handled by reset disk.
  415. * - remainder is handled by configdisk.
  416. * - ahcirecover is a quick recovery from a failed command.
  417. */
  418. int
  419. ahciswreset(Aportc *pc)
  420. {
  421. int i;
  422. i = ahciidle(pc->p);
  423. pc->p->cmd |= Afre;
  424. if(i == -1)
  425. return -1;
  426. if(pc->p->task & (ASdrq|ASbsy))
  427. return -1;
  428. return 0;
  429. }
  430. int
  431. ahcirecover(Aportc *pc)
  432. {
  433. ahciswreset(pc);
  434. pc->p->cmd |= Ast;
  435. if(setudmamode(pc, 5) == -1)
  436. return -1;
  437. return 0;
  438. }
  439. static void*
  440. malign(int size, int align)
  441. {
  442. void *v;
  443. v = xspanalloc(size, align, 0);
  444. memset(v, 0, size);
  445. return v;
  446. }
  447. static void
  448. setupfis(Afis *f)
  449. {
  450. f->base = malign(0x100, 0x100);
  451. f->d = f->base + 0;
  452. f->p = f->base + 0x20;
  453. f->r = f->base + 0x40;
  454. f->u = f->base + 0x60;
  455. f->devicebits = (ulong*)(f->base + 0x58);
  456. }
  457. static void
  458. ahciwakeup(Aport *p)
  459. {
  460. ushort s;
  461. s = p->sstatus;
  462. if((s & 0x700) != 0x600)
  463. return;
  464. if((s & 7) != 1){
  465. print("ahci: slumbering drive unwakeable %ux\n", s);
  466. return;
  467. }
  468. p->sctl = 3*Aipm | 0*Aspd | Adet;
  469. delay(1);
  470. p->sctl &= ~7;
  471. // iprint("ahci: wake %ux -> %ux\n", s, p->sstatus);
  472. }
  473. static int
  474. ahciconfigdrive(Ahba *h, Aportc *c, int mode)
  475. {
  476. Aportm *m;
  477. Aport *p;
  478. p = c->p;
  479. m = c->m;
  480. if(m->list == 0){
  481. setupfis(&m->fis);
  482. m->list = malign(sizeof *m->list, 1024);
  483. m->ctab = malign(sizeof *m->ctab, 128);
  484. }
  485. if(p->sstatus & 3 && h->cap & Hsss){
  486. dprint("configdrive: spinning up ... [%lux]\n", p->sstatus);
  487. p->cmd |= Apod|Asud;
  488. asleep(1400);
  489. }
  490. p->serror = SerrAll;
  491. p->list = PCIWADDR(m->list);
  492. p->listhi = 0;
  493. p->fis = PCIWADDR(m->fis.base);
  494. p->fishi = 0;
  495. p->cmd |= Afre | Ast;
  496. if((p->sstatus & 0x707) == 0x601) /* drive coming up in slumbering? */
  497. ahciwakeup(p);
  498. /* disable power managment sequence from book. */
  499. p->sctl = (3*Aipm) | (mode*Aspd) | (0*Adet);
  500. p->cmd &= ~Aalpe;
  501. p->ie = IEM;
  502. return 0;
  503. }
  504. static int
  505. ahcienable(Ahba *h)
  506. {
  507. h->ghc |= Hie;
  508. return 0;
  509. }
  510. static int
  511. ahcidisable(Ahba *h)
  512. {
  513. h->ghc &= ~Hie;
  514. return 0;
  515. }
  516. static int
  517. countbits(ulong u)
  518. {
  519. int i, n;
  520. n = 0;
  521. for(i = 0; i < 32; i++)
  522. if(u & (1<<i))
  523. n++;
  524. return n;
  525. }
  526. static int
  527. ahciconf(Ctlr *c)
  528. {
  529. ulong u;
  530. Ahba *h;
  531. static int count;
  532. h = c->hba = (Ahba*)c->mmio;
  533. u = h->cap;
  534. if((u & Hsam) == 0)
  535. h->ghc |= Hae;
  536. print("ahci%d port %#p: hba sss %ld; ncs %ld; coal %ld; mports %ld; "
  537. "led %ld; clo %ld; ems %ld;\n", count++, h,
  538. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1,
  539. (u>>24) & 1, (u>>6) & 1);
  540. return countbits(h->pi);
  541. }
  542. static int
  543. ahcihbareset(Ahba *h)
  544. {
  545. int wait;
  546. h->ghc |= 1;
  547. for(wait = 0; wait < 1000; wait += 100){
  548. if(h->ghc == 0)
  549. return 0;
  550. delay(100);
  551. }
  552. return -1;
  553. }
  554. static void
  555. idmove(char *p, ushort *a, int n)
  556. {
  557. int i;
  558. char *op, *e;
  559. op = p;
  560. for(i = 0; i < n/2; i++){
  561. *p++ = a[i] >> 8;
  562. *p++ = a[i];
  563. }
  564. *p = 0;
  565. while(p > op && *--p == ' ')
  566. *p = 0;
  567. e = p;
  568. for (p = op; *p == ' '; p++)
  569. ;
  570. memmove(op, p, n - (e - p));
  571. }
  572. static int
  573. identify(Drive *d)
  574. {
  575. ushort *id;
  576. vlong osectors, s;
  577. uchar oserial[21];
  578. SDunit *u;
  579. id = d->info;
  580. s = ahciidentify(&d->portc, id);
  581. if(s == -1){
  582. d->state = Derror;
  583. return -1;
  584. }
  585. osectors = d->sectors;
  586. memmove(oserial, d->serial, sizeof d->serial);
  587. d->sectors = s;
  588. d->smartrs = 0;
  589. idmove(d->serial, id+10, 20);
  590. idmove(d->firmware, id+23, 8);
  591. idmove(d->model, id+27, 40);
  592. u = d->unit;
  593. memset(u->inquiry, 0, sizeof u->inquiry);
  594. u->inquiry[2] = 2;
  595. u->inquiry[3] = 2;
  596. u->inquiry[4] = sizeof u->inquiry - 4;
  597. memmove(u->inquiry+8, d->model, 40);
  598. if((osectors == 0 || osectors != s) &&
  599. memcmp(oserial, d->serial, sizeof oserial) != 0){
  600. d->mediachange = 1;
  601. u->sectors = 0;
  602. }
  603. return 0;
  604. }
  605. static void
  606. clearci(Aport *p)
  607. {
  608. if((p->cmd & Ast) == 0)
  609. return;
  610. p->cmd &= ~Ast;
  611. p->cmd |= Ast;
  612. }
  613. static void
  614. updatedrive(Drive *d)
  615. {
  616. ulong cause, serr, s0, pr, ewake;
  617. char *name;
  618. Aport *p;
  619. static ulong last;
  620. pr = 1;
  621. ewake = 0;
  622. p = d->port;
  623. cause = p->isr;
  624. serr = p->serror;
  625. p->isr = cause;
  626. name = "??";
  627. if(d->unit && d->unit->name)
  628. name = d->unit->name;
  629. if(p->ci == 0){
  630. d->portm.flag |= Fdone;
  631. pr = 0;
  632. }else if(cause & Adps)
  633. pr = 0;
  634. if(cause&Ifatal){
  635. ewake = 1;
  636. dprint("Fatal\n");
  637. }
  638. if(cause & Adhrs){
  639. if(p->task & (32|1)){
  640. dprint("Adhrs cause = %lux; serr = %lux; task=%lux\n",
  641. cause, serr, p->task);
  642. d->portm.flag |= Ferror;
  643. ewake = 1;
  644. }
  645. pr = 0;
  646. }
  647. if(pr)
  648. dprint("%s: upd %lux ta %lux\n", name, cause, p->task);
  649. if(cause & (Aprcs|Aifs)){
  650. s0 = d->state;
  651. switch(p->sstatus & 7){
  652. case 0:
  653. d->state = Dmissing;
  654. break;
  655. case 1:
  656. if((p->sstatus & 0x700) == 0x600)
  657. d->state = Dnew;
  658. else
  659. d->state = Derror;
  660. break;
  661. case 3:
  662. /* power mgnt crap for surprise removal */
  663. p->ie |= Aprcs | Apcs; /* is this required? */
  664. d->state = Dreset;
  665. break;
  666. case 4:
  667. d->state = Doffline;
  668. break;
  669. }
  670. dprint("%s: %s → %s [Apcrs] %lux\n", name, diskstates[s0],
  671. diskstates[d->state], p->sstatus);
  672. if(s0 == Dready && d->state != Dready)
  673. idprint("%s: pulled\n", name);
  674. if(d->state != Dready)
  675. d->portm.flag |= Ferror;
  676. ewake = 1;
  677. }
  678. p->serror = serr;
  679. if(ewake)
  680. clearci(p);
  681. last = cause;
  682. }
  683. static void
  684. pstatus(Drive *d, ulong s)
  685. {
  686. /*
  687. * bogus code because the first interrupt is currently dropped.
  688. * likely my fault. serror may be cleared at the wrong time.
  689. */
  690. switch(s){
  691. case 0:
  692. d->state = Dmissing;
  693. break;
  694. case 2: /* should this be missing? need testcase. */
  695. dprint("pstatus 2\n");
  696. case 3:
  697. d->wait = 0;
  698. d->state = Dnew;
  699. break;
  700. case 4:
  701. d->state = Doffline;
  702. break;
  703. case 6:
  704. d->state = Dnew;
  705. break;
  706. }
  707. }
  708. static int
  709. configdrive(Drive *d)
  710. {
  711. if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1)
  712. return -1;
  713. ilock(d);
  714. pstatus(d, d->port->sstatus & 7);
  715. iunlock(d);
  716. return 0;
  717. }
  718. static void
  719. resetdisk(Drive *d)
  720. {
  721. uint state, det, stat;
  722. Aport *p;
  723. p = d->port;
  724. det = p->sctl & 7;
  725. stat = p->sstatus & 7;
  726. state = (p->cmd>>28) & 0xf;
  727. dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat);
  728. if(stat != 3){
  729. ilock(d);
  730. d->state = Dportreset;
  731. iunlock(d);
  732. return;
  733. }
  734. ilock(d);
  735. state = d->state;
  736. if(d->state != Dready || d->state != Dnew)
  737. d->portm.flag |= Ferror;
  738. clearci(p); /* satisfy sleep condition. */
  739. iunlock(d);
  740. qlock(&d->portm);
  741. if(p->cmd & Ast && ahciswreset(&d->portc) == -1){
  742. ilock(d);
  743. d->state = Dportreset; /* get a bigger stick. */
  744. iunlock(d);
  745. } else {
  746. ilock(d);
  747. d->state = Dmissing;
  748. iunlock(d);
  749. configdrive(d);
  750. }
  751. dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]);
  752. qunlock(&d->portm);
  753. }
  754. static int
  755. newdrive(Drive *d)
  756. {
  757. char *name, *s;
  758. Aportc *c;
  759. Aportm *m;
  760. c = &d->portc;
  761. m = &d->portm;
  762. name = d->unit->name;
  763. if(name == 0)
  764. name = "??";
  765. if(d->port->task == 0x80)
  766. return -1;
  767. qlock(c->m);
  768. if(setudmamode(c, 5) == -1){
  769. dprint("%s: can't set udma mode\n", name);
  770. goto lose;
  771. }
  772. if(identify(d) == -1){
  773. dprint("%s: identify failure\n", name);
  774. goto lose;
  775. }
  776. if(m->feat & Dpower && setfeatures(c, 0x85) == -1){
  777. m->feat &= ~Dpower;
  778. if(ahcirecover(c) == -1) {
  779. dprint("%s: ahcirecover failed\n", name);
  780. goto lose;
  781. }
  782. }
  783. ilock(d);
  784. d->state = Dready;
  785. iunlock(d);
  786. qunlock(c->m);
  787. s = "";
  788. if(m->feat & Dllba)
  789. s = "L";
  790. idprint("%s: %sLBA %lld sectors\n", d->unit->name, s, d->sectors);
  791. idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial,
  792. d->mediachange? "[mediachange]": "");
  793. return 0;
  794. lose:
  795. qunlock(&d->portm);
  796. return -1;
  797. }
  798. enum {
  799. Nms = 256,
  800. Mphywait = 2*1024/Nms - 1,
  801. Midwait = 16*1024/Nms - 1,
  802. Mcomrwait = 64*1024/Nms - 1,
  803. };
  804. static void
  805. westerndigitalhung(Drive *d)
  806. {
  807. if((d->portm.feat & Datapi) == 0 && d->active &&
  808. TK2MS(m->ticks - d->intick) > 5000){
  809. dprint("%s: drive hung; resetting [%lux] ci=%lx\n",
  810. d->unit->name, d->port->task, d->port->ci);
  811. d->state = Dreset;
  812. }
  813. }
  814. static ushort olds[NCtlr*NCtlrdrv];
  815. static int
  816. doportreset(Drive *d)
  817. {
  818. int i;
  819. i = -1;
  820. qlock(&d->portm);
  821. if(ahciportreset(&d->portc) == -1)
  822. dprint("ahciportreset fails\n");
  823. else
  824. i = 0;
  825. qunlock(&d->portm);
  826. dprint("portreset → %s [task %lux]\n", diskstates[d->state],
  827. d->port->task);
  828. return i;
  829. }
  830. static void
  831. checkdrive(Drive *d, int i)
  832. {
  833. ushort s;
  834. char *name;
  835. ilock(d);
  836. name = d->unit->name;
  837. s = d->port->sstatus;
  838. if(s != olds[i]){
  839. dprint("%s: status: %#ux -> %#ux: %s\n", name, olds[i],
  840. s, diskstates[d->state]);
  841. olds[i] = s;
  842. d->wait = 0;
  843. }
  844. westerndigitalhung(d);
  845. switch(d->state){
  846. case Dnull:
  847. break;
  848. case Dmissing:
  849. case Dnew:
  850. switch(s & 0x107){
  851. case 1:
  852. ahciwakeup(d->port);
  853. case 0:
  854. break;
  855. default:
  856. dprint("%s: unknown status %04ux\n", name, s);
  857. case 0x100:
  858. if(++d->wait&Mphywait)
  859. break;
  860. reset:
  861. if(++d->mode > DMsataii)
  862. d->mode = 0;
  863. if(d->mode == DMsatai){ /* we tried everything */
  864. d->state = Dportreset;
  865. goto portreset;
  866. }
  867. dprint("%s: reset; new mode %s\n", name,
  868. modename[d->mode]);
  869. iunlock(d);
  870. resetdisk(d);
  871. ilock(d);
  872. break;
  873. case 0x103:
  874. if((++d->wait&Midwait) == 0){
  875. dprint("%s: slow reset %#ux task=%#lux; %d\n",
  876. name, s, d->port->task, d->wait);
  877. goto reset;
  878. }
  879. s = d->port->task&0xff;
  880. if(s == 0x7f || ((d->port->sig>>16) != 0xeb14 &&
  881. (s & ~0x17) != (1<<6)))
  882. break;
  883. iunlock(d);
  884. newdrive(d);
  885. ilock(d);
  886. break;
  887. }
  888. break;
  889. case Doffline:
  890. if(d->wait++ & Mcomrwait)
  891. break;
  892. case Derror:
  893. case Dreset:
  894. dprint("%s: reset [%s]: mode %d; status %#ux\n",
  895. name, diskstates[d->state], d->mode, s);
  896. iunlock(d);
  897. resetdisk(d);
  898. ilock(d);
  899. break;
  900. case Dportreset:
  901. portreset:
  902. if(d->wait++ & 0xff && (s & 0x100) == 0)
  903. break;
  904. dprint("%s: portreset [%s]: mode %d; status %04ux\n",
  905. name, diskstates[d->state], d->mode, s);
  906. d->portm.flag |= Ferror;
  907. clearci(d->port);
  908. if((s & 7) == 0){
  909. d->state = Dmissing;
  910. break;
  911. }
  912. iunlock(d);
  913. doportreset(d);
  914. ilock(d);
  915. break;
  916. }
  917. iunlock(d);
  918. }
  919. static void
  920. iainterrupt(Ureg*, void *a)
  921. {
  922. int i;
  923. ulong cause, m;
  924. Ctlr *c;
  925. Drive *d;
  926. c = a;
  927. ilock(c);
  928. /* check drive here! */
  929. cause = c->hba->isr;
  930. for(i = 0; i < c->ndrive; i++){
  931. m = 1 << i;
  932. if((cause & m) == 0)
  933. continue;
  934. d = c->rawdrive + i;
  935. ilock(d);
  936. if(d->port->isr && c->hba->pi & m)
  937. updatedrive(d);
  938. c->hba->isr = m;
  939. iunlock(d);
  940. }
  941. iunlock(c);
  942. }
  943. static int
  944. iaverify(SDunit *u)
  945. {
  946. int i;
  947. Ctlr *c;
  948. Drive *d;
  949. c = u->dev->ctlr;
  950. d = c->drive[u->subno];
  951. ilock(c);
  952. ilock(d);
  953. d->unit = u;
  954. iunlock(d);
  955. iunlock(c);
  956. for(i = 0; i < 10; i++){
  957. checkdrive(d, d->driveno);
  958. switch(d->state){
  959. case Dmissing:
  960. if(i < 4 || d->port->sstatus & 0x733)
  961. break;
  962. /* fall through */
  963. case Dnull:
  964. case Dready:
  965. case Doffline:
  966. print("sdiahci: drive %d in state %s after %d resets\n",
  967. d->driveno, diskstates[d->state], i);
  968. return 1;
  969. }
  970. delay(100);
  971. }
  972. print("sdiahci: drive %d won't come up; in state %s after %d resets\n",
  973. d->driveno, diskstates[d->state], i);
  974. return 1;
  975. }
  976. static int
  977. iaenable(SDev *s)
  978. {
  979. Ctlr *c;
  980. c = s->ctlr;
  981. ilock(c);
  982. if(!c->enabled) {
  983. if(c->ndrive == 0)
  984. panic("iaenable: zero s->ctlr->ndrive");
  985. pcisetbme(c->pci);
  986. setvec(c->pci->intl+VectorPIC, iainterrupt, c);
  987. /* supposed to squelch leftover interrupts here. */
  988. ahcienable(c->hba);
  989. c->enabled = 1;
  990. }
  991. iunlock(c);
  992. return 1;
  993. }
  994. static int
  995. iadisable(SDev *s)
  996. {
  997. Ctlr *c;
  998. c = s->ctlr;
  999. ilock(c);
  1000. ahcidisable(c->hba);
  1001. // intrdisable(c->irq, iainterrupt, c, c->tbdf, name);
  1002. c->enabled = 0;
  1003. iunlock(c);
  1004. return 1;
  1005. }
  1006. static int
  1007. iaonline(SDunit *unit)
  1008. {
  1009. int r;
  1010. Ctlr *c;
  1011. Drive *d;
  1012. c = unit->dev->ctlr;
  1013. d = c->drive[unit->subno];
  1014. r = 0;
  1015. if(d->portm.feat & Datapi && d->mediachange){
  1016. r = scsionline(unit);
  1017. if(r > 0)
  1018. d->mediachange = 0;
  1019. return r;
  1020. }
  1021. ilock(d);
  1022. if(d->mediachange){
  1023. r = 2;
  1024. d->mediachange = 0;
  1025. /* devsd resets this after online is called; why? */
  1026. unit->sectors = d->sectors;
  1027. unit->secsize = 512;
  1028. } else if(d->state == Dready)
  1029. r = 1;
  1030. iunlock(d);
  1031. return r;
  1032. }
  1033. /* returns locked list! */
  1034. static Alist*
  1035. ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba)
  1036. {
  1037. uchar *c, acmd, dir, llba;
  1038. Alist *l;
  1039. Actab *t;
  1040. Aprdt *p;
  1041. static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35 };
  1042. dir = *cmd != 0x28;
  1043. llba = m->feat & Dllba? 1: 0;
  1044. acmd = tab[dir][llba];
  1045. qlock(m);
  1046. l = m->list;
  1047. t = m->ctab;
  1048. c = t->cfis;
  1049. c[0] = 0x27;
  1050. c[1] = 0x80;
  1051. c[2] = acmd;
  1052. c[3] = 0;
  1053. c[4] = lba; /* sector lba low 7:0 */
  1054. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1055. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1056. c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */
  1057. if(llba == 0)
  1058. c[7] |= (lba>>24) & 7;
  1059. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1060. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1061. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1062. c[11] = 0; /* features (exp); */
  1063. c[12] = n; /* sector count */
  1064. c[13] = n >> 8; /* sector count (exp) */
  1065. c[14] = 0; /* r */
  1066. c[15] = 0; /* control */
  1067. *(ulong*)(c+16) = 0;
  1068. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1069. if(dir == Write)
  1070. l->flags |= Lwrite;
  1071. l->len = 0;
  1072. l->ctab = PCIWADDR(t);
  1073. l->ctabhi = 0;
  1074. p = &t->prdt;
  1075. p->dba = PCIWADDR(data);
  1076. p->dbahi = 0;
  1077. p->count = 1<<31 | (512*n - 2) | 1;
  1078. return l;
  1079. }
  1080. static Alist*
  1081. ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n)
  1082. {
  1083. int fill, len;
  1084. uchar *c;
  1085. Actab *t;
  1086. Alist *l;
  1087. Aprdt *p;
  1088. qlock(m);
  1089. l = m->list;
  1090. t = m->ctab;
  1091. c = t->cfis;
  1092. fill = m->feat & Datapi16? 16: 12;
  1093. if((len = r->clen) > fill)
  1094. len = fill;
  1095. memmove(t->atapi, r->cmd, len);
  1096. memset(t->atapi + len, 0, fill - len);
  1097. c[0] = 0x27;
  1098. c[1] = 0x80;
  1099. c[2] = 0xa0;
  1100. if(n != 0)
  1101. c[3] = 1; /* dma */
  1102. else
  1103. c[3] = 0; /* features (exp); */
  1104. c[4] = 0; /* sector lba low 7:0 */
  1105. c[5] = n; /* cylinder low lba mid 15:8 */
  1106. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1107. c[7] = 0xa0; /* obsolete device bits */
  1108. *(ulong*)(c+8) = 0;
  1109. *(ulong*)(c+12) = 0;
  1110. *(ulong*)(c+16) = 0;
  1111. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1112. if(r->write != 0 && data)
  1113. l->flags |= Lwrite;
  1114. l->len = 0;
  1115. l->ctab = PCIWADDR(t);
  1116. l->ctabhi = 0;
  1117. if(data == 0)
  1118. return l;
  1119. p = &t->prdt;
  1120. p->dba = PCIWADDR(data);
  1121. p->dbahi = 0;
  1122. p->count = 1<<31 | (n - 2) | 1;
  1123. return l;
  1124. }
  1125. static int
  1126. waitready(Drive *d)
  1127. {
  1128. ulong s, t, i;
  1129. for(i = 0; i < 120; i++){
  1130. ilock(d);
  1131. s = d->port->sstatus;
  1132. t = d->port->task;
  1133. iunlock(d);
  1134. if((s & 0x100) == 0)
  1135. return -1;
  1136. if(d->state == Dready && (s & 7) == 3)
  1137. return 0;
  1138. if((i + 1) % 30 == 0)
  1139. print("%s: waitready: [%s] task=%lux sstat=%lux\n",
  1140. d->unit->name, diskstates[d->state], t, s);
  1141. esleep(1000);
  1142. }
  1143. print("%s: not responding; offline\n", d->unit->name);
  1144. ilock(d);
  1145. d->state = Doffline;
  1146. iunlock(d);
  1147. return -1;
  1148. }
  1149. static int
  1150. iariopkt(SDreq *r, Drive *d)
  1151. {
  1152. int n, count, try, max, flag, task;
  1153. char *name;
  1154. uchar *cmd, *data;
  1155. Aport *p;
  1156. Asleep as;
  1157. cmd = r->cmd;
  1158. name = d->unit->name;
  1159. p = d->port;
  1160. aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write],
  1161. r->dlen, r->data);
  1162. // if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1163. // return sdmodesense(r, cmd, d->info, sizeof d->info);
  1164. r->rlen = 0;
  1165. count = r->dlen;
  1166. max = 65536;
  1167. try = 0;
  1168. retry:
  1169. if(waitready(d) == -1)
  1170. return SDeio;
  1171. data = r->data;
  1172. n = count;
  1173. if(n > max)
  1174. n = max;
  1175. d->active++;
  1176. ahcibuildpkt(&d->portm, r, data, n);
  1177. ilock(d);
  1178. d->portm.flag = 0;
  1179. iunlock(d);
  1180. p->ci = 1;
  1181. as.p = p;
  1182. as.i = 1;
  1183. d->intick = m->ticks;
  1184. while(ahciclear(&as) == 0)
  1185. ;
  1186. ilock(d);
  1187. flag = d->portm.flag;
  1188. task = d->port->task;
  1189. iunlock(d);
  1190. if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){
  1191. d->port->ci = 0; /* @? */
  1192. ahcirecover(&d->portc);
  1193. task = d->port->task;
  1194. }
  1195. d->active--;
  1196. qunlock(&d->portm);
  1197. if(flag == 0){
  1198. if(++try == 10){
  1199. print("%s: bad disk\n", name);
  1200. r->status = SDcheck;
  1201. return SDcheck;
  1202. }
  1203. print("%s: retry\n", name);
  1204. esleep(1000);
  1205. goto retry;
  1206. }
  1207. if(flag & Ferror){
  1208. if((task & Eidnf) == 0)
  1209. print("%s: i/o error %ux\n", name, task);
  1210. r->status = SDcheck;
  1211. return SDcheck;
  1212. }
  1213. data += n;
  1214. r->rlen = data - (uchar*)r->data;
  1215. r->status = SDok;
  1216. return SDok;
  1217. }
  1218. static int
  1219. iario(SDreq *r)
  1220. {
  1221. int n, count, max, flag, task;
  1222. vlong lba;
  1223. char *name;
  1224. uchar *cmd, *data;
  1225. Aport *p;
  1226. Asleep as;
  1227. Ctlr *c;
  1228. Drive *d;
  1229. SDunit *unit;
  1230. unit = r->unit;
  1231. c = unit->dev->ctlr;
  1232. d = c->drive[unit->subno];
  1233. if(d->portm.feat & Datapi)
  1234. return iariopkt(r, d);
  1235. cmd = r->cmd;
  1236. name = d->unit->name;
  1237. p = d->port;
  1238. // if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){
  1239. // r->status = i;
  1240. // return i;
  1241. // }
  1242. if(*cmd != 0x28 && *cmd != 0x2a){
  1243. print("%s: bad cmd 0x%.2ux\n", name, cmd[0]);
  1244. r->status = SDcheck;
  1245. return SDcheck;
  1246. }
  1247. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1248. count = cmd[7]<<8 | cmd[8];
  1249. if(r->data == nil)
  1250. return SDok;
  1251. if(r->dlen < count * unit->secsize)
  1252. count = r->dlen / unit->secsize;
  1253. max = 128;
  1254. if(waitready(d) == -1)
  1255. return SDeio;
  1256. data = r->data;
  1257. while(count > 0){
  1258. n = count;
  1259. if(n > max)
  1260. n = max;
  1261. d->active++;
  1262. ahcibuild(&d->portm, cmd, data, n, lba);
  1263. ilock(d);
  1264. d->portm.flag = 0;
  1265. iunlock(d);
  1266. p->ci = 1;
  1267. as.p = p;
  1268. as.i = 1;
  1269. d->intick = m->ticks;
  1270. while(ahciclear(&as) == 0)
  1271. ;
  1272. ilock(d);
  1273. flag = d->portm.flag;
  1274. task = d->port->task;
  1275. iunlock(d);
  1276. if(task & (Efatal<<8) ||
  1277. task & (ASbsy|ASdrq) && d->state == Dready){
  1278. d->port->ci = 0; /* @? */
  1279. ahcirecover(&d->portc);
  1280. task = d->port->task;
  1281. }
  1282. d->active--;
  1283. qunlock(&d->portm);
  1284. if(flag == 0 || flag & Ferror){
  1285. print("%s: i/o error %ux @%lld\n", name, task, lba);
  1286. r->status = SDeio;
  1287. return SDeio;
  1288. }
  1289. count -= n;
  1290. lba += n;
  1291. data += n * unit->secsize;
  1292. }
  1293. r->rlen = data - (uchar*)r->data;
  1294. r->status = SDok;
  1295. return SDok;
  1296. }
  1297. /*
  1298. * configure drives 0-5 as ahci sata (c.f. errata)
  1299. */
  1300. static int
  1301. iaahcimode(Pcidev *p)
  1302. {
  1303. dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91),
  1304. pcicfgr8(p, 92), pcicfgr8(p, 93));
  1305. pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */
  1306. // pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */
  1307. return 0;
  1308. }
  1309. static void
  1310. iasetupahci(Ctlr *c)
  1311. {
  1312. /* disable cmd block decoding. */
  1313. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1314. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1315. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1316. c->lmmio[0xc/4] = (1<<6) - 1; /* five ports (supposedly ro pi reg) */
  1317. /* enable ahci mode; from ich9 datasheet */
  1318. pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5);
  1319. }
  1320. static SDev*
  1321. iapnp(void)
  1322. {
  1323. int i, n, nunit, type;
  1324. ulong io;
  1325. Ctlr *c;
  1326. Drive *d;
  1327. Pcidev *p;
  1328. SDev *head, *tail, *s;
  1329. static int done;
  1330. if (done || getconf("*noahciload") != nil)
  1331. return nil;
  1332. done = 1;
  1333. p = nil;
  1334. head = tail = nil;
  1335. loop:
  1336. while((p = pcimatch(p, 0, 0)) != nil){
  1337. /* 0x27c4 is the intel 82801 in compatibility (not sata) mode */
  1338. if(p->vid == 0x8086 && (p->did & 0xfffc) == 0x2680)
  1339. type = Tesb;
  1340. else if(p->vid == 0x8086 &&
  1341. (p->did == 0x27c5 || p->did == 0x27c0))
  1342. type = Tich; /* 82801g[bh]m?; compat mode fails */
  1343. else if(p->vid == 0x8086 && (p->did & 0xfeff) == 0x2829)
  1344. type = Tich; /* ich8 */
  1345. else if(p->vid == 0x8086 && (p->did & 0xfffe) == 0x2922)
  1346. type = Tich; /* ich8 */
  1347. else if(p->vid == 0x1002 && p->did == 0x4380)
  1348. type = Tsb600;
  1349. else
  1350. continue;
  1351. if(niactlr == NCtlr){
  1352. print("iapnp: %s: too many controllers\n", tname[type]);
  1353. break;
  1354. }
  1355. c = iactlr + niactlr;
  1356. s = sdevs + niactlr;
  1357. memset(c, 0, sizeof *c);
  1358. memset(s, 0, sizeof *s);
  1359. c->pci = p;
  1360. c->type = type;
  1361. io = p->mem[Abar].bar & ~0xf;
  1362. io = upamalloc(io, p->mem[Abar].size, 0);
  1363. if(io == 0){
  1364. print("%s: address %#lux in use, did %#ux\n",
  1365. tname[c->type], io, p->did);
  1366. continue;
  1367. }
  1368. /* ugly hack: get this in compatibility mode; see memory.c:271 */
  1369. if(io == 0x40000000) {
  1370. print("%s: did %#ux is in non-sata mode. bar %#lux\n",
  1371. tname[c->type], p->did, p->mem[Abar].bar);
  1372. continue;
  1373. }
  1374. c->mmio = KADDR(io);
  1375. c->lmmio = (ulong*)c->mmio;
  1376. if(Intel(c->type) && p->did != 0x2681)
  1377. iasetupahci(c);
  1378. nunit = ahciconf(c);
  1379. // ahcihbareset((Ahba*)c->mmio);
  1380. if(Intel(c->type) && iaahcimode(p) == -1)
  1381. break;
  1382. if(nunit < 1){
  1383. // vunmap(c->mmio, p->mem[Abar].size);
  1384. continue;
  1385. }
  1386. niactlr++;
  1387. i = (c->hba->cap>>21) & 1;
  1388. print("%s: sata-%s with %d ports\n", tname[c->type],
  1389. "I\0II"+i*2, nunit);
  1390. s->ifc = &sdiahciifc;
  1391. s->ctlr = c;
  1392. s->nunit = nunit;
  1393. s->idno = 'E';
  1394. c->sdev = s;
  1395. c->ndrive = nunit;
  1396. /* map the drives -- they don't all need to be enabled. */
  1397. memset(c->rawdrive, 0, sizeof c->rawdrive);
  1398. n = 0;
  1399. for(i = 0; i < NCtlrdrv; i++) {
  1400. d = c->rawdrive+i;
  1401. d->portno = i;
  1402. d->driveno = -1;
  1403. d->sectors = 0;
  1404. d->ctlr = c;
  1405. if((c->hba->pi & (1<<i)) == 0)
  1406. continue;
  1407. // d->state = Dnew;
  1408. d->port = (Aport*)(c->mmio + 0x80*i + 0x100);
  1409. d->portc.p = d->port;
  1410. d->portc.m = &d->portm;
  1411. d->driveno = n++;
  1412. c->drive[d->driveno] = d;
  1413. }
  1414. for(i = 0; i < n; i++)
  1415. if(ahciidle(c->drive[i]->port) == -1){
  1416. print("%s: port %d wedged; abort\n",
  1417. tname[c->type], i);
  1418. goto loop;
  1419. }
  1420. for(i = 0; i < n; i++){
  1421. c->drive[i]->mode = DMsatai;
  1422. configdrive(c->drive[i]);
  1423. }
  1424. if(head)
  1425. tail->next = s;
  1426. else
  1427. head = s;
  1428. tail = s;
  1429. }
  1430. return head;
  1431. }
  1432. static SDev*
  1433. iaid(SDev* sdev)
  1434. {
  1435. int i;
  1436. Ctlr *c;
  1437. for(; sdev; sdev = sdev->next){
  1438. if(sdev->ifc != &sdiahciifc)
  1439. continue;
  1440. c = sdev->ctlr;
  1441. for(i = 0; i < NCtlr; i++)
  1442. if(c == iactlr + i)
  1443. sdev->idno = 'E' + i;
  1444. }
  1445. return nil;
  1446. }
  1447. SDifc sdiahciifc = {
  1448. "iahci",
  1449. iapnp,
  1450. nil, /* legacy */
  1451. iaid,
  1452. iaenable,
  1453. iadisable,
  1454. iaverify,
  1455. iaonline,
  1456. iario,
  1457. nil,
  1458. nil,
  1459. scsibio,
  1460. };