devarch.c 19 KB

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  1. #include "u.h"
  2. #include "../port/lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "ureg.h"
  8. #include "../port/error.h"
  9. typedef struct IOMap IOMap;
  10. struct IOMap
  11. {
  12. IOMap *next;
  13. int reserved;
  14. char tag[13];
  15. ulong start;
  16. ulong end;
  17. };
  18. static struct
  19. {
  20. Lock;
  21. IOMap *m;
  22. IOMap *free;
  23. IOMap maps[32]; /* some initial free maps */
  24. QLock ql; /* lock for reading map */
  25. } iomap;
  26. enum {
  27. Qdir = 0,
  28. Qioalloc = 1,
  29. Qiob,
  30. Qiow,
  31. Qiol,
  32. Qbase,
  33. Qmax = 16,
  34. };
  35. typedef long Rdwrfn(Chan*, void*, long, vlong);
  36. static Rdwrfn *readfn[Qmax];
  37. static Rdwrfn *writefn[Qmax];
  38. static Dirtab archdir[Qmax] = {
  39. ".", { Qdir, 0, QTDIR }, 0, 0555,
  40. "ioalloc", { Qioalloc, 0 }, 0, 0444,
  41. "iob", { Qiob, 0 }, 0, 0660,
  42. "iow", { Qiow, 0 }, 0, 0660,
  43. "iol", { Qiol, 0 }, 0, 0660,
  44. };
  45. Lock archwlock; /* the lock is only for changing archdir */
  46. int narchdir = Qbase;
  47. int (*_pcmspecial)(char*, ISAConf*);
  48. void (*_pcmspecialclose)(int);
  49. static int doi8253set = 1;
  50. /*
  51. * Add a file to the #P listing. Once added, you can't delete it.
  52. * You can't add a file with the same name as one already there,
  53. * and you get a pointer to the Dirtab entry so you can do things
  54. * like change the Qid version. Changing the Qid path is disallowed.
  55. */
  56. Dirtab*
  57. addarchfile(char *name, int perm, Rdwrfn *rdfn, Rdwrfn *wrfn)
  58. {
  59. int i;
  60. Dirtab d;
  61. Dirtab *dp;
  62. memset(&d, 0, sizeof d);
  63. strcpy(d.name, name);
  64. d.perm = perm;
  65. lock(&archwlock);
  66. if(narchdir >= Qmax){
  67. unlock(&archwlock);
  68. return nil;
  69. }
  70. for(i=0; i<narchdir; i++)
  71. if(strcmp(archdir[i].name, name) == 0){
  72. unlock(&archwlock);
  73. return nil;
  74. }
  75. d.qid.path = narchdir;
  76. archdir[narchdir] = d;
  77. readfn[narchdir] = rdfn;
  78. writefn[narchdir] = wrfn;
  79. dp = &archdir[narchdir++];
  80. unlock(&archwlock);
  81. return dp;
  82. }
  83. void
  84. ioinit(void)
  85. {
  86. char *excluded;
  87. int i;
  88. for(i = 0; i < nelem(iomap.maps)-1; i++)
  89. iomap.maps[i].next = &iomap.maps[i+1];
  90. iomap.maps[i].next = nil;
  91. iomap.free = iomap.maps;
  92. /*
  93. * This is necessary to make the IBM X20 boot.
  94. * Have not tracked down the reason.
  95. * i82557 is at 0x1000, the dummy entry is needed for swappable devs.
  96. */
  97. ioalloc(0x0fff, 1, 0, "dummy");
  98. if ((excluded = getconf("ioexclude")) != nil) {
  99. char *s;
  100. s = excluded;
  101. while (s && *s != '\0' && *s != '\n') {
  102. char *ends;
  103. int io_s, io_e;
  104. io_s = (int)strtol(s, &ends, 0);
  105. if (ends == nil || ends == s || *ends != '-') {
  106. print("ioinit: cannot parse option string\n");
  107. break;
  108. }
  109. s = ++ends;
  110. io_e = (int)strtol(s, &ends, 0);
  111. if (ends && *ends == ',')
  112. *ends++ = '\0';
  113. s = ends;
  114. ioalloc(io_s, io_e - io_s + 1, 0, "pre-allocated");
  115. }
  116. }
  117. }
  118. /*
  119. * Reserve a range to be ioalloced later.
  120. * This is in particular useful for exchangable cards, such
  121. * as pcmcia and cardbus cards.
  122. */
  123. int
  124. ioreserve(int, int size, int align, char *tag)
  125. {
  126. IOMap *m, **l;
  127. int i, port;
  128. lock(&iomap);
  129. /* find a free port above 0x400 and below 0x1000 */
  130. port = 0x400;
  131. for(l = &iomap.m; *l; l = &(*l)->next){
  132. m = *l;
  133. if (m->start < 0x400) continue;
  134. i = m->start - port;
  135. if(i > size)
  136. break;
  137. if(align > 0)
  138. port = ((port+align-1)/align)*align;
  139. else
  140. port = m->end;
  141. }
  142. if(*l == nil){
  143. unlock(&iomap);
  144. return -1;
  145. }
  146. m = iomap.free;
  147. if(m == nil){
  148. print("ioalloc: out of maps");
  149. unlock(&iomap);
  150. return port;
  151. }
  152. iomap.free = m->next;
  153. m->next = *l;
  154. m->start = port;
  155. m->end = port + size;
  156. m->reserved = 1;
  157. strncpy(m->tag, tag, sizeof(m->tag));
  158. m->tag[sizeof(m->tag)-1] = 0;
  159. *l = m;
  160. archdir[0].qid.vers++;
  161. unlock(&iomap);
  162. return m->start;
  163. }
  164. /*
  165. * alloc some io port space and remember who it was
  166. * alloced to. if port < 0, find a free region.
  167. */
  168. int
  169. ioalloc(int port, int size, int align, char *tag)
  170. {
  171. IOMap *m, **l;
  172. int i;
  173. lock(&iomap);
  174. if(port < 0){
  175. /* find a free port above 0x400 and below 0x1000 */
  176. port = 0x400;
  177. for(l = &iomap.m; *l; l = &(*l)->next){
  178. m = *l;
  179. if (m->start < 0x400) continue;
  180. i = m->start - port;
  181. if(i > size)
  182. break;
  183. if(align > 0)
  184. port = ((port+align-1)/align)*align;
  185. else
  186. port = m->end;
  187. }
  188. if(*l == nil){
  189. unlock(&iomap);
  190. return -1;
  191. }
  192. } else {
  193. /* Only 64KB I/O space on the x86. */
  194. if((port+size) > 0x10000){
  195. unlock(&iomap);
  196. return -1;
  197. }
  198. /* see if the space clashes with previously allocated ports */
  199. for(l = &iomap.m; *l; l = &(*l)->next){
  200. m = *l;
  201. if(m->end <= port)
  202. continue;
  203. if(m->reserved && m->start == port && m->end == port + size) {
  204. m->reserved = 0;
  205. unlock(&iomap);
  206. return m->start;
  207. }
  208. if(m->start >= port+size)
  209. break;
  210. unlock(&iomap);
  211. return -1;
  212. }
  213. }
  214. m = iomap.free;
  215. if(m == nil){
  216. print("ioalloc: out of maps");
  217. unlock(&iomap);
  218. return port;
  219. }
  220. iomap.free = m->next;
  221. m->next = *l;
  222. m->start = port;
  223. m->end = port + size;
  224. strncpy(m->tag, tag, sizeof(m->tag));
  225. m->tag[sizeof(m->tag)-1] = 0;
  226. *l = m;
  227. archdir[0].qid.vers++;
  228. unlock(&iomap);
  229. return m->start;
  230. }
  231. void
  232. iofree(int port)
  233. {
  234. IOMap *m, **l;
  235. lock(&iomap);
  236. for(l = &iomap.m; *l; l = &(*l)->next){
  237. if((*l)->start == port){
  238. m = *l;
  239. *l = m->next;
  240. m->next = iomap.free;
  241. iomap.free = m;
  242. break;
  243. }
  244. if((*l)->start > port)
  245. break;
  246. }
  247. archdir[0].qid.vers++;
  248. unlock(&iomap);
  249. }
  250. int
  251. iounused(int start, int end)
  252. {
  253. IOMap *m;
  254. for(m = iomap.m; m; m = m->next){
  255. if(start >= m->start && start < m->end
  256. || start <= m->start && end > m->start)
  257. return 0;
  258. }
  259. return 1;
  260. }
  261. static void
  262. checkport(int start, int end)
  263. {
  264. /* standard vga regs are OK */
  265. if(start >= 0x2b0 && end <= 0x2df+1)
  266. return;
  267. if(start >= 0x3c0 && end <= 0x3da+1)
  268. return;
  269. if(iounused(start, end))
  270. return;
  271. error(Eperm);
  272. }
  273. static Chan*
  274. archattach(char* spec)
  275. {
  276. return devattach('P', spec);
  277. }
  278. Walkqid*
  279. archwalk(Chan* c, Chan *nc, char** name, int nname)
  280. {
  281. return devwalk(c, nc, name, nname, archdir, narchdir, devgen);
  282. }
  283. static int
  284. archstat(Chan* c, uchar* dp, int n)
  285. {
  286. return devstat(c, dp, n, archdir, narchdir, devgen);
  287. }
  288. static Chan*
  289. archopen(Chan* c, int omode)
  290. {
  291. return devopen(c, omode, archdir, narchdir, devgen);
  292. }
  293. static void
  294. archclose(Chan*)
  295. {
  296. }
  297. enum
  298. {
  299. Linelen= 31,
  300. };
  301. static long
  302. archread(Chan *c, void *a, long n, vlong offset)
  303. {
  304. char *buf, *p;
  305. int port;
  306. ushort *sp;
  307. ulong *lp;
  308. IOMap *m;
  309. Rdwrfn *fn;
  310. switch((ulong)c->qid.path){
  311. case Qdir:
  312. return devdirread(c, a, n, archdir, narchdir, devgen);
  313. case Qiob:
  314. port = offset;
  315. checkport(offset, offset+n);
  316. for(p = a; port < offset+n; port++)
  317. *p++ = inb(port);
  318. return n;
  319. case Qiow:
  320. if(n & 1)
  321. error(Ebadarg);
  322. checkport(offset, offset+n);
  323. sp = a;
  324. for(port = offset; port < offset+n; port += 2)
  325. *sp++ = ins(port);
  326. return n;
  327. case Qiol:
  328. if(n & 3)
  329. error(Ebadarg);
  330. checkport(offset, offset+n);
  331. lp = a;
  332. for(port = offset; port < offset+n; port += 4)
  333. *lp++ = inl(port);
  334. return n;
  335. case Qioalloc:
  336. break;
  337. default:
  338. if(c->qid.path < narchdir && (fn = readfn[c->qid.path]))
  339. return fn(c, a, n, offset);
  340. error(Eperm);
  341. break;
  342. }
  343. if((buf = malloc(n)) == nil)
  344. error(Enomem);
  345. p = buf;
  346. n = n/Linelen;
  347. offset = offset/Linelen;
  348. lock(&iomap);
  349. for(m = iomap.m; n > 0 && m != nil; m = m->next){
  350. if(offset-- > 0)
  351. continue;
  352. sprint(p, "%8lux %8lux %-12.12s\n", m->start, m->end-1, m->tag);
  353. p += Linelen;
  354. n--;
  355. }
  356. unlock(&iomap);
  357. n = p - buf;
  358. memmove(a, buf, n);
  359. free(buf);
  360. return n;
  361. }
  362. static long
  363. archwrite(Chan *c, void *a, long n, vlong offset)
  364. {
  365. char *p;
  366. int port;
  367. ushort *sp;
  368. ulong *lp;
  369. Rdwrfn *fn;
  370. switch((ulong)c->qid.path){
  371. case Qiob:
  372. p = a;
  373. checkport(offset, offset+n);
  374. for(port = offset; port < offset+n; port++)
  375. outb(port, *p++);
  376. return n;
  377. case Qiow:
  378. if(n & 1)
  379. error(Ebadarg);
  380. checkport(offset, offset+n);
  381. sp = a;
  382. for(port = offset; port < offset+n; port += 2)
  383. outs(port, *sp++);
  384. return n;
  385. case Qiol:
  386. if(n & 3)
  387. error(Ebadarg);
  388. checkport(offset, offset+n);
  389. lp = a;
  390. for(port = offset; port < offset+n; port += 4)
  391. outl(port, *lp++);
  392. return n;
  393. default:
  394. if(c->qid.path < narchdir && (fn = writefn[c->qid.path]))
  395. return fn(c, a, n, offset);
  396. error(Eperm);
  397. break;
  398. }
  399. return 0;
  400. }
  401. Dev archdevtab = {
  402. 'P',
  403. "arch",
  404. devreset,
  405. devinit,
  406. devshutdown,
  407. archattach,
  408. archwalk,
  409. archstat,
  410. archopen,
  411. devcreate,
  412. archclose,
  413. archread,
  414. devbread,
  415. archwrite,
  416. devbwrite,
  417. devremove,
  418. devwstat,
  419. };
  420. /*
  421. * the following is a generic version of the
  422. * architecture specific stuff
  423. */
  424. static int
  425. unimplemented(int)
  426. {
  427. return 0;
  428. }
  429. static void
  430. nop(void)
  431. {
  432. }
  433. /*
  434. * 386 has no compare-and-swap instruction.
  435. * Run it with interrupts turned off instead.
  436. */
  437. static int
  438. cmpswap386(long *addr, long old, long new)
  439. {
  440. int r, s;
  441. s = splhi();
  442. if(r = (*addr == old))
  443. *addr = new;
  444. splx(s);
  445. return r;
  446. }
  447. /*
  448. * On a uniprocessor, you'd think that coherence could be nop,
  449. * but it can't. We still need a barrier when using coherence() in
  450. * device drivers.
  451. *
  452. * On VMware, it's safe (and a huge win) to set this to nop.
  453. * Aux/vmware does this via the #P/archctl file.
  454. */
  455. void (*coherence)(void) = nop;
  456. int (*cmpswap)(long*, long, long) = cmpswap386;
  457. PCArch* arch;
  458. extern PCArch* knownarch[];
  459. PCArch archgeneric = {
  460. .id= "generic",
  461. .ident= 0,
  462. .reset= i8042reset,
  463. .serialpower= unimplemented,
  464. .modempower= unimplemented,
  465. .intrinit= i8259init,
  466. .intrenable= i8259enable,
  467. .intrvecno= i8259vecno,
  468. .intrdisable= i8259disable,
  469. .intron= i8259on,
  470. .introff= i8259off,
  471. .clockenable= i8253enable,
  472. .fastclock= i8253read,
  473. .timerset= i8253timerset,
  474. };
  475. typedef struct X86type X86type;
  476. struct X86type {
  477. int family;
  478. int model;
  479. int aalcycles;
  480. char* name;
  481. };
  482. static X86type x86intel[] =
  483. {
  484. { 4, 0, 22, "486DX", }, /* known chips */
  485. { 4, 1, 22, "486DX50", },
  486. { 4, 2, 22, "486SX", },
  487. { 4, 3, 22, "486DX2", },
  488. { 4, 4, 22, "486SL", },
  489. { 4, 5, 22, "486SX2", },
  490. { 4, 7, 22, "DX2WB", }, /* P24D */
  491. { 4, 8, 22, "DX4", }, /* P24C */
  492. { 4, 9, 22, "DX4WB", }, /* P24CT */
  493. { 5, 0, 23, "P5", },
  494. { 5, 1, 23, "P5", },
  495. { 5, 2, 23, "P54C", },
  496. { 5, 3, 23, "P24T", },
  497. { 5, 4, 23, "P55C MMX", },
  498. { 5, 7, 23, "P54C VRT", },
  499. { 6, 1, 16, "PentiumPro", },/* trial and error */
  500. { 6, 3, 16, "PentiumII", },
  501. { 6, 5, 16, "PentiumII/Xeon", },
  502. { 6, 6, 16, "Celeron", },
  503. { 6, 7, 16, "PentiumIII/Xeon", },
  504. { 6, 8, 16, "PentiumIII/Xeon", },
  505. { 6, 0xB, 16, "PentiumIII/Xeon", },
  506. { 6, 0xF, 16, "Xeon5000-series", },
  507. { 0xF, 1, 16, "P4", }, /* P4 */
  508. { 0xF, 2, 16, "PentiumIV/Xeon", },
  509. { 3, -1, 32, "386", }, /* family defaults */
  510. { 4, -1, 22, "486", },
  511. { 5, -1, 23, "P5", },
  512. { 6, -1, 16, "P6", },
  513. { 0xF, -1, 16, "P4", }, /* P4 */
  514. { -1, -1, 16, "unknown", }, /* total default */
  515. };
  516. /*
  517. * The AMD processors all implement the CPUID instruction.
  518. * The later ones also return the processor name via functions
  519. * 0x80000002, 0x80000003 and 0x80000004 in registers AX, BX, CX
  520. * and DX:
  521. * K5 "AMD-K5(tm) Processor"
  522. * K6 "AMD-K6tm w/ multimedia extensions"
  523. * K6 3D "AMD-K6(tm) 3D processor"
  524. * K6 3D+ ?
  525. */
  526. static X86type x86amd[] =
  527. {
  528. { 5, 0, 23, "AMD-K5", }, /* guesswork */
  529. { 5, 1, 23, "AMD-K5", }, /* guesswork */
  530. { 5, 2, 23, "AMD-K5", }, /* guesswork */
  531. { 5, 3, 23, "AMD-K5", }, /* guesswork */
  532. { 5, 6, 11, "AMD-K6", }, /* trial and error */
  533. { 5, 7, 11, "AMD-K6", }, /* trial and error */
  534. { 5, 8, 11, "AMD-K6-2", }, /* trial and error */
  535. { 5, 9, 11, "AMD-K6-III", },/* trial and error */
  536. { 6, 1, 11, "AMD-Athlon", },/* trial and error */
  537. { 6, 2, 11, "AMD-Athlon", },/* trial and error */
  538. { 4, -1, 22, "Am486", }, /* guesswork */
  539. { 5, -1, 23, "AMD-K5/K6", }, /* guesswork */
  540. { 6, -1, 11, "AMD-Athlon", },/* guesswork */
  541. { 0xF, -1, 11, "AMD64", }, /* guesswork */
  542. { -1, -1, 11, "unknown", }, /* total default */
  543. };
  544. /*
  545. * WinChip 240MHz
  546. */
  547. static X86type x86winchip[] =
  548. {
  549. {5, 4, 23, "Winchip",}, /* guesswork */
  550. {6, 7, 23, "Via C3 Samuel 2 or Ezra",},
  551. {6, 8, 23, "Via C3 Ezra-T",},
  552. {6, 9, 23, "Via C3 Eden-N",},
  553. { -1, -1, 23, "unknown", }, /* total default */
  554. };
  555. /*
  556. * SiS 55x
  557. */
  558. static X86type x86sis[] =
  559. {
  560. {5, 0, 23, "SiS 55x",}, /* guesswork */
  561. { -1, -1, 23, "unknown", }, /* total default */
  562. };
  563. static X86type *cputype;
  564. static void simplecycles(uvlong*);
  565. void (*cycles)(uvlong*) = simplecycles;
  566. void _cycles(uvlong*); /* in l.s */
  567. static void
  568. simplecycles(uvlong*x)
  569. {
  570. *x = m->ticks;
  571. }
  572. void
  573. cpuidprint(void)
  574. {
  575. int i;
  576. char buf[128];
  577. i = sprint(buf, "cpu%d: %dMHz ", m->machno, m->cpumhz);
  578. if(m->cpuidid[0])
  579. i += sprint(buf+i, "%12.12s ", m->cpuidid);
  580. seprint(buf+i, buf + sizeof buf - 1,
  581. "%s (cpuid: AX 0x%4.4uX DX 0x%4.4uX)\n",
  582. m->cpuidtype, m->cpuidax, m->cpuiddx);
  583. print(buf);
  584. }
  585. /*
  586. * figure out:
  587. * - cpu type
  588. * - whether or not we have a TSC (cycle counter)
  589. * - whether or not it supports page size extensions
  590. * (if so turn it on)
  591. * - whether or not it supports machine check exceptions
  592. * (if so turn it on)
  593. * - whether or not it supports the page global flag
  594. * (if so turn it on)
  595. */
  596. int
  597. cpuidentify(void)
  598. {
  599. char *p;
  600. int family, model, nomce;
  601. X86type *t, *tab;
  602. ulong cr4;
  603. vlong mca, mct;
  604. cpuid(m->cpuidid, &m->cpuidax, &m->cpuiddx);
  605. if(strncmp(m->cpuidid, "AuthenticAMD", 12) == 0)
  606. tab = x86amd;
  607. else if(strncmp(m->cpuidid, "CentaurHauls", 12) == 0)
  608. tab = x86winchip;
  609. else if(strncmp(m->cpuidid, "SiS SiS SiS ", 12) == 0)
  610. tab = x86sis;
  611. else
  612. tab = x86intel;
  613. family = X86FAMILY(m->cpuidax);
  614. model = X86MODEL(m->cpuidax);
  615. for(t=tab; t->name; t++)
  616. if((t->family == family && t->model == model)
  617. || (t->family == family && t->model == -1)
  618. || (t->family == -1))
  619. break;
  620. m->cpuidtype = t->name;
  621. /*
  622. * if there is one, set tsc to a known value
  623. */
  624. if(m->cpuiddx & Tsc){
  625. m->havetsc = 1;
  626. cycles = _cycles;
  627. if(m->cpuiddx & Cpumsr)
  628. wrmsr(0x10, 0);
  629. }
  630. /*
  631. * use i8253 to guess our cpu speed
  632. */
  633. guesscpuhz(t->aalcycles);
  634. /*
  635. * If machine check exception, page size extensions or page global bit
  636. * are supported enable them in CR4 and clear any other set extensions.
  637. * If machine check was enabled clear out any lingering status.
  638. */
  639. if(m->cpuiddx & (Pge|Mce|0x8)){
  640. cr4 = 0;
  641. if(m->cpuiddx & 0x08)
  642. cr4 |= 0x10; /* page size extensions */
  643. if(p = getconf("*nomce"))
  644. nomce = strtoul(p, 0, 0);
  645. else
  646. nomce = 0;
  647. if((m->cpuiddx & Mce) && !nomce){
  648. cr4 |= 0x40; /* machine check enable */
  649. if(family == 5){
  650. rdmsr(0x00, &mca);
  651. rdmsr(0x01, &mct);
  652. }
  653. }
  654. /*
  655. * Detect whether the chip supports the global bit
  656. * in page directory and page table entries. When set
  657. * in a particular entry, it means ``don't bother removing
  658. * this from the TLB when CR3 changes.''
  659. *
  660. * We flag all kernel pages with this bit. Doing so lessens the
  661. * overhead of switching processes on bare hardware,
  662. * even more so on VMware. See mmu.c:/^memglobal.
  663. *
  664. * For future reference, should we ever need to do a
  665. * full TLB flush, it can be accomplished by clearing
  666. * the PGE bit in CR4, writing to CR3, and then
  667. * restoring the PGE bit.
  668. */
  669. if(m->cpuiddx & Pge){
  670. cr4 |= 0x80; /* page global enable bit */
  671. m->havepge = 1;
  672. }
  673. putcr4(cr4);
  674. if(m->cpuiddx & Mce)
  675. rdmsr(0x01, &mct);
  676. }
  677. cputype = t;
  678. return t->family;
  679. }
  680. static long
  681. cputyperead(Chan*, void *a, long n, vlong offset)
  682. {
  683. char str[32];
  684. ulong mhz;
  685. mhz = (m->cpuhz+999999)/1000000;
  686. snprint(str, sizeof(str), "%s %lud\n", cputype->name, mhz);
  687. return readstr(offset, a, n, str);
  688. }
  689. static long
  690. archctlread(Chan*, void *a, long nn, vlong offset)
  691. {
  692. char buf[256];
  693. int n;
  694. n = snprint(buf, sizeof buf, "cpu %s %lud%s\n",
  695. cputype->name, (ulong)(m->cpuhz+999999)/1000000,
  696. m->havepge ? " pge" : "");
  697. n += snprint(buf+n, sizeof buf-n, "pge %s\n", getcr4()&0x80 ? "on" : "off");
  698. n += snprint(buf+n, sizeof buf-n, "coherence ");
  699. if(coherence == mb386)
  700. n += snprint(buf+n, sizeof buf-n, "mb386\n");
  701. else if(coherence == mb586)
  702. n += snprint(buf+n, sizeof buf-n, "mb586\n");
  703. else if(coherence == mfence)
  704. n += snprint(buf+n, sizeof buf-n, "mfence\n");
  705. else if(coherence == nop)
  706. n += snprint(buf+n, sizeof buf-n, "nop\n");
  707. else
  708. n += snprint(buf+n, sizeof buf-n, "0x%p\n", coherence);
  709. n += snprint(buf+n, sizeof buf-n, "cmpswap ");
  710. if(cmpswap == cmpswap386)
  711. n += snprint(buf+n, sizeof buf-n, "cmpswap386\n");
  712. else if(cmpswap == cmpswap486)
  713. n += snprint(buf+n, sizeof buf-n, "cmpswap486\n");
  714. else
  715. n += snprint(buf+n, sizeof buf-n, "0x%p\n", cmpswap);
  716. n += snprint(buf+n, sizeof buf-n, "i8253set %s\n", doi8253set ? "on" : "off");
  717. buf[n] = 0;
  718. return readstr(offset, a, nn, buf);
  719. }
  720. enum
  721. {
  722. CMpge,
  723. CMcoherence,
  724. CMi8253set,
  725. };
  726. static Cmdtab archctlmsg[] =
  727. {
  728. CMpge, "pge", 2,
  729. CMcoherence, "coherence", 2,
  730. CMi8253set, "i8253set", 2,
  731. };
  732. static long
  733. archctlwrite(Chan*, void *a, long n, vlong)
  734. {
  735. Cmdbuf *cb;
  736. Cmdtab *ct;
  737. cb = parsecmd(a, n);
  738. if(waserror()){
  739. free(cb);
  740. nexterror();
  741. }
  742. ct = lookupcmd(cb, archctlmsg, nelem(archctlmsg));
  743. switch(ct->index){
  744. case CMpge:
  745. if(!m->havepge)
  746. error("processor does not support pge");
  747. if(strcmp(cb->f[1], "on") == 0)
  748. putcr4(getcr4() | 0x80);
  749. else if(strcmp(cb->f[1], "off") == 0)
  750. putcr4(getcr4() & ~0x80);
  751. else
  752. cmderror(cb, "invalid pge ctl");
  753. break;
  754. case CMcoherence:
  755. if(strcmp(cb->f[1], "mb386") == 0)
  756. coherence = mb386;
  757. else if(strcmp(cb->f[1], "mb586") == 0){
  758. if(X86FAMILY(m->cpuidax) < 5)
  759. error("invalid coherence ctl on this cpu family");
  760. coherence = mb586;
  761. }else if(strcmp(cb->f[1], "mfence") == 0){
  762. if((m->cpuiddx & Sse2) == 0)
  763. error("invalid coherence ctl on this cpu family");
  764. coherence = mfence;
  765. }else if(strcmp(cb->f[1], "nop") == 0){
  766. /* only safe on vmware */
  767. if(conf.nmach > 1)
  768. error("cannot disable coherence on a multiprocessor");
  769. coherence = nop;
  770. }else
  771. cmderror(cb, "invalid coherence ctl");
  772. break;
  773. case CMi8253set:
  774. if(strcmp(cb->f[1], "on") == 0)
  775. doi8253set = 1;
  776. else if(strcmp(cb->f[1], "off") == 0){
  777. doi8253set = 0;
  778. (*arch->timerset)(0);
  779. }else
  780. cmderror(cb, "invalid i2853set ctl");
  781. break;
  782. }
  783. free(cb);
  784. poperror();
  785. return n;
  786. }
  787. void
  788. archinit(void)
  789. {
  790. PCArch **p;
  791. arch = 0;
  792. for(p = knownarch; *p; p++){
  793. if((*p)->ident && (*p)->ident() == 0){
  794. arch = *p;
  795. break;
  796. }
  797. }
  798. if(arch == 0)
  799. arch = &archgeneric;
  800. else{
  801. if(arch->id == 0)
  802. arch->id = archgeneric.id;
  803. if(arch->reset == 0)
  804. arch->reset = archgeneric.reset;
  805. if(arch->serialpower == 0)
  806. arch->serialpower = archgeneric.serialpower;
  807. if(arch->modempower == 0)
  808. arch->modempower = archgeneric.modempower;
  809. if(arch->intrinit == 0)
  810. arch->intrinit = archgeneric.intrinit;
  811. if(arch->intrenable == 0)
  812. arch->intrenable = archgeneric.intrenable;
  813. }
  814. /*
  815. * Decide whether to use copy-on-reference (386 and mp).
  816. * We get another chance to set it in mpinit() for a
  817. * multiprocessor.
  818. */
  819. if(X86FAMILY(m->cpuidax) == 3)
  820. conf.copymode = 1;
  821. if(X86FAMILY(m->cpuidax) >= 4)
  822. cmpswap = cmpswap486;
  823. if(X86FAMILY(m->cpuidax) >= 5)
  824. coherence = mb586;
  825. if(m->cpuiddx & Sse2)
  826. coherence = mfence;
  827. addarchfile("cputype", 0444, cputyperead, nil);
  828. addarchfile("archctl", 0664, archctlread, archctlwrite);
  829. }
  830. /*
  831. * call either the pcmcia or pccard device setup
  832. */
  833. int
  834. pcmspecial(char *idstr, ISAConf *isa)
  835. {
  836. return (_pcmspecial != nil)? _pcmspecial(idstr, isa): -1;
  837. }
  838. /*
  839. * call either the pcmcia or pccard device teardown
  840. */
  841. void
  842. pcmspecialclose(int a)
  843. {
  844. if (_pcmspecialclose != nil)
  845. _pcmspecialclose(a);
  846. }
  847. /*
  848. * return value and speed of timer set in arch->clockenable
  849. */
  850. uvlong
  851. fastticks(uvlong *hz)
  852. {
  853. return (*arch->fastclock)(hz);
  854. }
  855. ulong
  856. µs(void)
  857. {
  858. return fastticks2us((*arch->fastclock)(nil));
  859. }
  860. /*
  861. * set next timer interrupt
  862. */
  863. void
  864. timerset(uvlong x)
  865. {
  866. if(doi8253set)
  867. (*arch->timerset)(x);
  868. }