ether82557.c 30 KB

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  1. /*
  2. * Intel 82557 Fast Ethernet PCI Bus LAN Controller
  3. * as found on the Intel EtherExpress PRO/100B. This chip is full
  4. * of smarts, unfortunately they're not all in the right place.
  5. * To do:
  6. * the PCI scanning code could be made common to other adapters;
  7. * auto-negotiation, full-duplex;
  8. * optionally use memory-mapped registers;
  9. * detach for PCI reset problems (also towards loadable drivers).
  10. */
  11. #include "u.h"
  12. #include "../port/lib.h"
  13. #include "mem.h"
  14. #include "dat.h"
  15. #include "fns.h"
  16. #include "io.h"
  17. #include "../port/error.h"
  18. #include "../port/netif.h"
  19. #include "etherif.h"
  20. enum {
  21. Nrfd = 64, /* receive frame area */
  22. Ncb = 64, /* maximum control blocks queued */
  23. NullPointer = 0xFFFFFFFF, /* 82557 NULL pointer */
  24. };
  25. enum { /* CSR */
  26. Status = 0x00, /* byte or word (word includes Ack) */
  27. Ack = 0x01, /* byte */
  28. CommandR = 0x02, /* byte or word (word includes Interrupt) */
  29. Interrupt = 0x03, /* byte */
  30. General = 0x04, /* dword */
  31. Port = 0x08, /* dword */
  32. Fcr = 0x0C, /* Flash control register */
  33. Ecr = 0x0E, /* EEPROM control register */
  34. Mcr = 0x10, /* MDI control register */
  35. Gstatus = 0x1D, /* General status register */
  36. };
  37. enum { /* Status */
  38. RUidle = 0x0000,
  39. RUsuspended = 0x0004,
  40. RUnoresources = 0x0008,
  41. RUready = 0x0010,
  42. RUrbd = 0x0020, /* bit */
  43. RUstatus = 0x003F, /* mask */
  44. CUidle = 0x0000,
  45. CUsuspended = 0x0040,
  46. CUactive = 0x0080,
  47. CUstatus = 0x00C0, /* mask */
  48. StatSWI = 0x0400, /* SoftWare generated Interrupt */
  49. StatMDI = 0x0800, /* MDI r/w done */
  50. StatRNR = 0x1000, /* Receive unit Not Ready */
  51. StatCNA = 0x2000, /* Command unit Not Active (Active->Idle) */
  52. StatFR = 0x4000, /* Finished Receiving */
  53. StatCX = 0x8000, /* Command eXecuted */
  54. StatTNO = 0x8000, /* Transmit NOT OK */
  55. };
  56. enum { /* Command (byte) */
  57. CUnop = 0x00,
  58. CUstart = 0x10,
  59. CUresume = 0x20,
  60. LoadDCA = 0x40, /* Load Dump Counters Address */
  61. DumpSC = 0x50, /* Dump Statistical Counters */
  62. LoadCUB = 0x60, /* Load CU Base */
  63. ResetSA = 0x70, /* Dump and Reset Statistical Counters */
  64. RUstart = 0x01,
  65. RUresume = 0x02,
  66. RUabort = 0x04,
  67. LoadHDS = 0x05, /* Load Header Data Size */
  68. LoadRUB = 0x06, /* Load RU Base */
  69. RBDresume = 0x07, /* Resume frame reception */
  70. };
  71. enum { /* Interrupt (byte) */
  72. InterruptM = 0x01, /* interrupt Mask */
  73. InterruptSI = 0x02, /* Software generated Interrupt */
  74. };
  75. enum { /* Ecr */
  76. EEsk = 0x01, /* serial clock */
  77. EEcs = 0x02, /* chip select */
  78. EEdi = 0x04, /* serial data in */
  79. EEdo = 0x08, /* serial data out */
  80. EEstart = 0x04, /* start bit */
  81. EEread = 0x02, /* read opcode */
  82. };
  83. enum { /* Mcr */
  84. MDIread = 0x08000000, /* read opcode */
  85. MDIwrite = 0x04000000, /* write opcode */
  86. MDIready = 0x10000000, /* ready bit */
  87. MDIie = 0x20000000, /* interrupt enable */
  88. };
  89. typedef struct Rfd {
  90. int field;
  91. ulong link;
  92. ulong rbd;
  93. ushort count;
  94. ushort size;
  95. uchar data[1700];
  96. } Rfd;
  97. enum { /* field */
  98. RfdCollision = 0x00000001,
  99. RfdIA = 0x00000002, /* IA match */
  100. RfdRxerr = 0x00000010, /* PHY character error */
  101. RfdType = 0x00000020, /* Type frame */
  102. RfdRunt = 0x00000080,
  103. RfdOverrun = 0x00000100,
  104. RfdBuffer = 0x00000200,
  105. RfdAlignment = 0x00000400,
  106. RfdCRC = 0x00000800,
  107. RfdOK = 0x00002000, /* frame received OK */
  108. RfdC = 0x00008000, /* reception Complete */
  109. RfdSF = 0x00080000, /* Simplified or Flexible (1) Rfd */
  110. RfdH = 0x00100000, /* Header RFD */
  111. RfdI = 0x20000000, /* Interrupt after completion */
  112. RfdS = 0x40000000, /* Suspend after completion */
  113. RfdEL = 0x80000000, /* End of List */
  114. };
  115. enum { /* count */
  116. RfdF = 0x4000,
  117. RfdEOF = 0x8000,
  118. };
  119. typedef struct Cb Cb;
  120. typedef struct Cb {
  121. ushort status;
  122. ushort command;
  123. ulong link;
  124. union {
  125. uchar data[24]; /* CbIAS + CbConfigure */
  126. struct {
  127. ulong tbd;
  128. ushort count;
  129. uchar threshold;
  130. uchar number;
  131. ulong tba;
  132. ushort tbasz;
  133. ushort pad;
  134. };
  135. };
  136. Block* bp;
  137. Cb* next;
  138. } Cb;
  139. enum { /* action command */
  140. CbU = 0x1000, /* transmit underrun */
  141. CbOK = 0x2000, /* DMA completed OK */
  142. CbC = 0x8000, /* execution Complete */
  143. CbNOP = 0x0000,
  144. CbIAS = 0x0001, /* Individual Address Setup */
  145. CbConfigure = 0x0002,
  146. CbMAS = 0x0003, /* Multicast Address Setup */
  147. CbTransmit = 0x0004,
  148. CbDump = 0x0006,
  149. CbDiagnose = 0x0007,
  150. CbCommand = 0x0007, /* mask */
  151. CbSF = 0x0008, /* Flexible-mode CbTransmit */
  152. CbI = 0x2000, /* Interrupt after completion */
  153. CbS = 0x4000, /* Suspend after completion */
  154. CbEL = 0x8000, /* End of List */
  155. };
  156. enum { /* CbTransmit count */
  157. CbEOF = 0x8000,
  158. };
  159. typedef struct Ctlr Ctlr;
  160. typedef struct Ctlr {
  161. Lock slock; /* attach */
  162. int state;
  163. int port;
  164. Pcidev* pcidev;
  165. Ctlr* next;
  166. int active;
  167. int eepromsz; /* address size in bits */
  168. ushort* eeprom;
  169. Lock miilock;
  170. int tick;
  171. Lock rlock; /* registers */
  172. int command; /* last command issued */
  173. Block* rfdhead; /* receive side */
  174. Block* rfdtail;
  175. int nrfd;
  176. Lock cblock; /* transmit side */
  177. int action;
  178. int nop;
  179. uchar configdata[24];
  180. int threshold;
  181. int ncb;
  182. Cb* cbr;
  183. Cb* cbhead;
  184. Cb* cbtail;
  185. int cbq;
  186. int cbqmax;
  187. int cbqmaxhw;
  188. Lock dlock; /* dump statistical counters */
  189. ulong dump[17];
  190. } Ctlr;
  191. static Ctlr* ctlrhead;
  192. static Ctlr* ctlrtail;
  193. static uchar configdata[24] = {
  194. 0x16, /* byte count */
  195. 0x08, /* Rx/Tx FIFO limit */
  196. 0x00, /* adaptive IFS */
  197. 0x00,
  198. 0x00, /* Rx DMA maximum byte count */
  199. // 0x80, /* Tx DMA maximum byte count */
  200. 0x00, /* Tx DMA maximum byte count */
  201. 0x32, /* !late SCB, CNA interrupts */
  202. 0x03, /* discard short Rx frames */
  203. 0x00, /* 503/MII */
  204. 0x00,
  205. 0x2E, /* normal operation, NSAI */
  206. 0x00, /* linear priority */
  207. 0x60, /* inter-frame spacing */
  208. 0x00,
  209. 0xF2,
  210. 0xC8, /* 503, promiscuous mode off */
  211. 0x00,
  212. 0x40,
  213. 0xF3, /* transmit padding enable */
  214. 0x80, /* full duplex pin enable */
  215. 0x3F, /* no Multi IA */
  216. 0x05, /* no Multi Cast ALL */
  217. };
  218. #define csr8r(c, r) (inb((c)->port+(r)))
  219. #define csr16r(c, r) (ins((c)->port+(r)))
  220. #define csr32r(c, r) (inl((c)->port+(r)))
  221. #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b)))
  222. #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w)))
  223. #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l)))
  224. static void
  225. command(Ctlr* ctlr, int c, int v)
  226. {
  227. int timeo;
  228. ilock(&ctlr->rlock);
  229. /*
  230. * Only back-to-back CUresume can be done
  231. * without waiting for any previous command to complete.
  232. * This should be the common case.
  233. * Unfortunately there's a chip errata where back-to-back
  234. * CUresumes can be lost, the fix is to always wait.
  235. if(c == CUresume && ctlr->command == CUresume){
  236. csr8w(ctlr, CommandR, c);
  237. iunlock(&ctlr->rlock);
  238. return;
  239. }
  240. */
  241. for(timeo = 0; timeo < 100; timeo++){
  242. if(!csr8r(ctlr, CommandR))
  243. break;
  244. microdelay(1);
  245. }
  246. if(timeo >= 100){
  247. ctlr->command = -1;
  248. iunlock(&ctlr->rlock);
  249. iprint("i82557: command %#ux %#ux timeout\n", c, v);
  250. return;
  251. }
  252. switch(c){
  253. case CUstart:
  254. case LoadDCA:
  255. case LoadCUB:
  256. case RUstart:
  257. case LoadHDS:
  258. case LoadRUB:
  259. csr32w(ctlr, General, v);
  260. break;
  261. /*
  262. case CUnop:
  263. case CUresume:
  264. case DumpSC:
  265. case ResetSA:
  266. case RUresume:
  267. case RUabort:
  268. */
  269. default:
  270. break;
  271. }
  272. csr8w(ctlr, CommandR, c);
  273. ctlr->command = c;
  274. iunlock(&ctlr->rlock);
  275. }
  276. static Block*
  277. rfdalloc(ulong link)
  278. {
  279. Block *bp;
  280. Rfd *rfd;
  281. if(bp = iallocb(sizeof(Rfd))){
  282. rfd = (Rfd*)bp->rp;
  283. rfd->field = 0;
  284. rfd->link = link;
  285. rfd->rbd = NullPointer;
  286. rfd->count = 0;
  287. rfd->size = sizeof(Etherpkt);
  288. }
  289. return bp;
  290. }
  291. static void
  292. watchdog(void* arg)
  293. {
  294. Ether *ether;
  295. Ctlr *ctlr;
  296. static void txstart(Ether*);
  297. ether = arg;
  298. for(;;){
  299. tsleep(&up->sleep, return0, 0, 4000);
  300. /*
  301. * Hmmm. This doesn't seem right. Currently
  302. * the device can't be disabled but it may be in
  303. * the future.
  304. */
  305. ctlr = ether->ctlr;
  306. if(ctlr == nil || ctlr->state == 0){
  307. print("%s: exiting\n", up->text);
  308. pexit("disabled", 0);
  309. }
  310. ilock(&ctlr->cblock);
  311. if(ctlr->tick++){
  312. ctlr->action = CbMAS;
  313. txstart(ether);
  314. }
  315. iunlock(&ctlr->cblock);
  316. }
  317. }
  318. static void
  319. attach(Ether* ether)
  320. {
  321. Ctlr *ctlr;
  322. char name[KNAMELEN];
  323. ctlr = ether->ctlr;
  324. lock(&ctlr->slock);
  325. if(ctlr->state == 0){
  326. ilock(&ctlr->rlock);
  327. csr8w(ctlr, Interrupt, 0);
  328. iunlock(&ctlr->rlock);
  329. command(ctlr, RUstart, PADDR(ctlr->rfdhead->rp));
  330. ctlr->state = 1;
  331. /*
  332. * Start the watchdog timer for the receive lockup errata
  333. * unless the EEPROM compatibility word indicates it may be
  334. * omitted.
  335. */
  336. if((ctlr->eeprom[0x03] & 0x0003) != 0x0003){
  337. snprint(name, KNAMELEN, "#l%dwatchdog", ether->ctlrno);
  338. kproc(name, watchdog, ether);
  339. }
  340. }
  341. unlock(&ctlr->slock);
  342. }
  343. static long
  344. ifstat(Ether* ether, void* a, long n, ulong offset)
  345. {
  346. char *p;
  347. int i, len, phyaddr;
  348. Ctlr *ctlr;
  349. ulong dump[17];
  350. ctlr = ether->ctlr;
  351. lock(&ctlr->dlock);
  352. /*
  353. * Start the command then
  354. * wait for completion status,
  355. * should be 0xA005.
  356. */
  357. ctlr->dump[16] = 0;
  358. command(ctlr, DumpSC, 0);
  359. while(ctlr->dump[16] == 0)
  360. ;
  361. ether->oerrs = ctlr->dump[1]+ctlr->dump[2]+ctlr->dump[3];
  362. ether->crcs = ctlr->dump[10];
  363. ether->frames = ctlr->dump[11];
  364. ether->buffs = ctlr->dump[12]+ctlr->dump[15];
  365. ether->overflows = ctlr->dump[13];
  366. if(n == 0){
  367. unlock(&ctlr->dlock);
  368. return 0;
  369. }
  370. memmove(dump, ctlr->dump, sizeof(dump));
  371. unlock(&ctlr->dlock);
  372. p = malloc(READSTR);
  373. len = snprint(p, READSTR, "transmit good frames: %lud\n", dump[0]);
  374. len += snprint(p+len, READSTR-len, "transmit maximum collisions errors: %lud\n", dump[1]);
  375. len += snprint(p+len, READSTR-len, "transmit late collisions errors: %lud\n", dump[2]);
  376. len += snprint(p+len, READSTR-len, "transmit underrun errors: %lud\n", dump[3]);
  377. len += snprint(p+len, READSTR-len, "transmit lost carrier sense: %lud\n", dump[4]);
  378. len += snprint(p+len, READSTR-len, "transmit deferred: %lud\n", dump[5]);
  379. len += snprint(p+len, READSTR-len, "transmit single collisions: %lud\n", dump[6]);
  380. len += snprint(p+len, READSTR-len, "transmit multiple collisions: %lud\n", dump[7]);
  381. len += snprint(p+len, READSTR-len, "transmit total collisions: %lud\n", dump[8]);
  382. len += snprint(p+len, READSTR-len, "receive good frames: %lud\n", dump[9]);
  383. len += snprint(p+len, READSTR-len, "receive CRC errors: %lud\n", dump[10]);
  384. len += snprint(p+len, READSTR-len, "receive alignment errors: %lud\n", dump[11]);
  385. len += snprint(p+len, READSTR-len, "receive resource errors: %lud\n", dump[12]);
  386. len += snprint(p+len, READSTR-len, "receive overrun errors: %lud\n", dump[13]);
  387. len += snprint(p+len, READSTR-len, "receive collision detect errors: %lud\n", dump[14]);
  388. len += snprint(p+len, READSTR-len, "receive short frame errors: %lud\n", dump[15]);
  389. len += snprint(p+len, READSTR-len, "nop: %d\n", ctlr->nop);
  390. if(ctlr->cbqmax > ctlr->cbqmaxhw)
  391. ctlr->cbqmaxhw = ctlr->cbqmax;
  392. len += snprint(p+len, READSTR-len, "cbqmax: %d\n", ctlr->cbqmax);
  393. ctlr->cbqmax = 0;
  394. len += snprint(p+len, READSTR-len, "threshold: %d\n", ctlr->threshold);
  395. len += snprint(p+len, READSTR-len, "eeprom:");
  396. for(i = 0; i < (1<<ctlr->eepromsz); i++){
  397. if(i && ((i & 0x07) == 0))
  398. len += snprint(p+len, READSTR-len, "\n ");
  399. len += snprint(p+len, READSTR-len, " %4.4ux", ctlr->eeprom[i]);
  400. }
  401. if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)){
  402. phyaddr = ctlr->eeprom[6] & 0x00FF;
  403. len += snprint(p+len, READSTR-len, "\nphy %2d:", phyaddr);
  404. for(i = 0; i < 6; i++){
  405. static int miir(Ctlr*, int, int);
  406. len += snprint(p+len, READSTR-len, " %4.4ux",
  407. miir(ctlr, phyaddr, i));
  408. }
  409. }
  410. snprint(p+len, READSTR-len, "\n");
  411. n = readstr(offset, a, n, p);
  412. free(p);
  413. return n;
  414. }
  415. static void
  416. txstart(Ether* ether)
  417. {
  418. Ctlr *ctlr;
  419. Block *bp;
  420. Cb *cb;
  421. ctlr = ether->ctlr;
  422. while(ctlr->cbq < (ctlr->ncb-1)){
  423. cb = ctlr->cbhead->next;
  424. if(ctlr->action == 0){
  425. bp = qget(ether->oq);
  426. if(bp == nil)
  427. break;
  428. cb->command = CbS|CbSF|CbTransmit;
  429. cb->tbd = PADDR(&cb->tba);
  430. cb->count = 0;
  431. cb->threshold = ctlr->threshold;
  432. cb->number = 1;
  433. cb->tba = PADDR(bp->rp);
  434. cb->bp = bp;
  435. cb->tbasz = BLEN(bp);
  436. }
  437. else if(ctlr->action == CbConfigure){
  438. cb->command = CbS|CbConfigure;
  439. memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata));
  440. ctlr->action = 0;
  441. }
  442. else if(ctlr->action == CbIAS){
  443. cb->command = CbS|CbIAS;
  444. memmove(cb->data, ether->ea, Eaddrlen);
  445. ctlr->action = 0;
  446. }
  447. else if(ctlr->action == CbMAS){
  448. cb->command = CbS|CbMAS;
  449. memset(cb->data, 0, sizeof(cb->data));
  450. ctlr->action = 0;
  451. }
  452. else{
  453. print("#l%d: action %#ux\n", ether->ctlrno, ctlr->action);
  454. ctlr->action = 0;
  455. break;
  456. }
  457. cb->status = 0;
  458. coherence();
  459. ctlr->cbhead->command &= ~CbS;
  460. ctlr->cbhead = cb;
  461. ctlr->cbq++;
  462. }
  463. /*
  464. * Workaround for some broken HUB chips
  465. * when connected at 10Mb/s half-duplex.
  466. */
  467. if(ctlr->nop){
  468. command(ctlr, CUnop, 0);
  469. microdelay(1);
  470. }
  471. command(ctlr, CUresume, 0);
  472. if(ctlr->cbq > ctlr->cbqmax)
  473. ctlr->cbqmax = ctlr->cbq;
  474. }
  475. static void
  476. configure(Ether* ether, int promiscuous)
  477. {
  478. Ctlr *ctlr;
  479. ctlr = ether->ctlr;
  480. ilock(&ctlr->cblock);
  481. if(promiscuous){
  482. ctlr->configdata[6] |= 0x80; /* Save Bad Frames */
  483. //ctlr->configdata[6] &= ~0x40; /* !Discard Overrun Rx Frames */
  484. ctlr->configdata[7] &= ~0x01; /* !Discard Short Rx Frames */
  485. ctlr->configdata[15] |= 0x01; /* Promiscuous mode */
  486. ctlr->configdata[18] &= ~0x01; /* (!Padding enable?), !stripping enable */
  487. ctlr->configdata[21] |= 0x08; /* Multi Cast ALL */
  488. }
  489. else{
  490. ctlr->configdata[6] &= ~0x80;
  491. //ctlr->configdata[6] |= 0x40;
  492. ctlr->configdata[7] |= 0x01;
  493. ctlr->configdata[15] &= ~0x01;
  494. ctlr->configdata[18] |= 0x01; /* 0x03? */
  495. ctlr->configdata[21] &= ~0x08;
  496. }
  497. ctlr->action = CbConfigure;
  498. txstart(ether);
  499. iunlock(&ctlr->cblock);
  500. }
  501. static void
  502. promiscuous(void* arg, int on)
  503. {
  504. configure(arg, on);
  505. }
  506. static void
  507. multicast(void* ether, uchar *addr, int add)
  508. {
  509. USED(addr);
  510. /*
  511. * TODO: if (add) add addr to list of mcast addrs in controller
  512. * else remove addr from list of mcast addrs in controller
  513. * enable multicast input (see CbMAS) instead of promiscuous mode.
  514. */
  515. if (add)
  516. configure(ether, 1);
  517. }
  518. static void
  519. transmit(Ether* ether)
  520. {
  521. Ctlr *ctlr;
  522. ctlr = ether->ctlr;
  523. ilock(&ctlr->cblock);
  524. txstart(ether);
  525. iunlock(&ctlr->cblock);
  526. }
  527. static void
  528. receive(Ether* ether)
  529. {
  530. Rfd *rfd;
  531. Ctlr *ctlr;
  532. int count;
  533. Block *bp, *pbp, *xbp;
  534. ctlr = ether->ctlr;
  535. bp = ctlr->rfdhead;
  536. for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){
  537. /*
  538. * If it's an OK receive frame
  539. * 1) save the count
  540. * 2) if it's small, try to allocate a block and copy
  541. * the data, then adjust the necessary fields for reuse;
  542. * 3) if it's big, try to allocate a new Rfd and if
  543. * successful
  544. * adjust the received buffer pointers for the
  545. * actual data received;
  546. * initialise the replacement buffer to point to
  547. * the next in the ring;
  548. * initialise bp to point to the replacement;
  549. * 4) if there's a good packet, pass it on for disposal.
  550. */
  551. if(rfd->field & RfdOK){
  552. pbp = nil;
  553. count = rfd->count & 0x3FFF;
  554. if((count < ETHERMAXTU/4) && (pbp = iallocb(count))){
  555. memmove(pbp->rp, bp->rp+offsetof(Rfd, data[0]), count);
  556. pbp->wp = pbp->rp + count;
  557. rfd->count = 0;
  558. rfd->field = 0;
  559. }
  560. else if(xbp = rfdalloc(rfd->link)){
  561. bp->rp += offsetof(Rfd, data[0]);
  562. bp->wp = bp->rp + count;
  563. xbp->next = bp->next;
  564. bp->next = 0;
  565. pbp = bp;
  566. bp = xbp;
  567. }
  568. if(pbp != nil)
  569. etheriq(ether, pbp, 1);
  570. }
  571. else{
  572. rfd->count = 0;
  573. rfd->field = 0;
  574. }
  575. /*
  576. * The ring tail pointer follows the head with with one
  577. * unused buffer in between to defeat hardware prefetch;
  578. * once the tail pointer has been bumped on to the next
  579. * and the new tail has the Suspend bit set, it can be
  580. * removed from the old tail buffer.
  581. * As a replacement for the current head buffer may have
  582. * been allocated above, ensure that the new tail points
  583. * to it (next and link).
  584. */
  585. rfd = (Rfd*)ctlr->rfdtail->rp;
  586. ctlr->rfdtail = ctlr->rfdtail->next;
  587. ctlr->rfdtail->next = bp;
  588. ((Rfd*)ctlr->rfdtail->rp)->link = PADDR(bp->rp);
  589. ((Rfd*)ctlr->rfdtail->rp)->field |= RfdS;
  590. coherence();
  591. rfd->field &= ~RfdS;
  592. /*
  593. * Finally done with the current (possibly replaced)
  594. * head, move on to the next and maintain the sentinel
  595. * between tail and head.
  596. */
  597. ctlr->rfdhead = bp->next;
  598. bp = ctlr->rfdhead;
  599. }
  600. }
  601. static void
  602. interrupt(Ureg*, void* arg)
  603. {
  604. Cb* cb;
  605. Ctlr *ctlr;
  606. Ether *ether;
  607. int status;
  608. ether = arg;
  609. ctlr = ether->ctlr;
  610. for(;;){
  611. ilock(&ctlr->rlock);
  612. status = csr16r(ctlr, Status);
  613. csr8w(ctlr, Ack, (status>>8) & 0xFF);
  614. iunlock(&ctlr->rlock);
  615. if(!(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI)))
  616. break;
  617. /*
  618. * If the watchdog timer for the receiver lockup errata is running,
  619. * let it know the receiver is active.
  620. */
  621. if(status & (StatFR|StatRNR)){
  622. ilock(&ctlr->cblock);
  623. ctlr->tick = 0;
  624. iunlock(&ctlr->cblock);
  625. }
  626. if(status & StatFR){
  627. receive(ether);
  628. status &= ~StatFR;
  629. }
  630. if(status & StatRNR){
  631. command(ctlr, RUresume, 0);
  632. status &= ~StatRNR;
  633. }
  634. if(status & StatCNA){
  635. ilock(&ctlr->cblock);
  636. cb = ctlr->cbtail;
  637. while(ctlr->cbq){
  638. if(!(cb->status & CbC))
  639. break;
  640. if(cb->bp){
  641. freeb(cb->bp);
  642. cb->bp = nil;
  643. }
  644. if((cb->status & CbU) && ctlr->threshold < 0xE0)
  645. ctlr->threshold++;
  646. ctlr->cbq--;
  647. cb = cb->next;
  648. }
  649. ctlr->cbtail = cb;
  650. txstart(ether);
  651. iunlock(&ctlr->cblock);
  652. status &= ~StatCNA;
  653. }
  654. if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))
  655. panic("#l%d: status %#ux\n", ether->ctlrno, status);
  656. }
  657. }
  658. static void
  659. ctlrinit(Ctlr* ctlr)
  660. {
  661. int i;
  662. Block *bp;
  663. Rfd *rfd;
  664. ulong link;
  665. /*
  666. * Create the Receive Frame Area (RFA) as a ring of allocated
  667. * buffers.
  668. * A sentinel buffer is maintained between the last buffer in
  669. * the ring (marked with RfdS) and the head buffer to defeat the
  670. * hardware prefetch of the next RFD and allow dynamic buffer
  671. * allocation.
  672. */
  673. link = NullPointer;
  674. for(i = 0; i < Nrfd; i++){
  675. bp = rfdalloc(link);
  676. if(ctlr->rfdhead == nil)
  677. ctlr->rfdtail = bp;
  678. bp->next = ctlr->rfdhead;
  679. ctlr->rfdhead = bp;
  680. link = PADDR(bp->rp);
  681. }
  682. ctlr->rfdtail->next = ctlr->rfdhead;
  683. rfd = (Rfd*)ctlr->rfdtail->rp;
  684. rfd->link = PADDR(ctlr->rfdhead->rp);
  685. rfd->field |= RfdS;
  686. ctlr->rfdhead = ctlr->rfdhead->next;
  687. /*
  688. * Create a ring of control blocks for the
  689. * transmit side.
  690. */
  691. ilock(&ctlr->cblock);
  692. ctlr->cbr = malloc(ctlr->ncb*sizeof(Cb));
  693. for(i = 0; i < ctlr->ncb; i++){
  694. ctlr->cbr[i].status = CbC|CbOK;
  695. ctlr->cbr[i].command = CbS|CbNOP;
  696. ctlr->cbr[i].link = PADDR(&ctlr->cbr[NEXT(i, ctlr->ncb)].status);
  697. ctlr->cbr[i].next = &ctlr->cbr[NEXT(i, ctlr->ncb)];
  698. }
  699. ctlr->cbhead = ctlr->cbr;
  700. ctlr->cbtail = ctlr->cbr;
  701. ctlr->cbq = 0;
  702. memmove(ctlr->configdata, configdata, sizeof(configdata));
  703. ctlr->threshold = 80;
  704. ctlr->tick = 0;
  705. iunlock(&ctlr->cblock);
  706. }
  707. static int
  708. miir(Ctlr* ctlr, int phyadd, int regadd)
  709. {
  710. int mcr, timo;
  711. lock(&ctlr->miilock);
  712. csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16));
  713. mcr = 0;
  714. for(timo = 64; timo; timo--){
  715. mcr = csr32r(ctlr, Mcr);
  716. if(mcr & MDIready)
  717. break;
  718. microdelay(1);
  719. }
  720. unlock(&ctlr->miilock);
  721. if(mcr & MDIready)
  722. return mcr & 0xFFFF;
  723. return -1;
  724. }
  725. static int
  726. miiw(Ctlr* ctlr, int phyadd, int regadd, int data)
  727. {
  728. int mcr, timo;
  729. lock(&ctlr->miilock);
  730. csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF));
  731. mcr = 0;
  732. for(timo = 64; timo; timo--){
  733. mcr = csr32r(ctlr, Mcr);
  734. if(mcr & MDIready)
  735. break;
  736. microdelay(1);
  737. }
  738. unlock(&ctlr->miilock);
  739. if(mcr & MDIready)
  740. return 0;
  741. return -1;
  742. }
  743. static int
  744. hy93c46r(Ctlr* ctlr, int r)
  745. {
  746. int data, i, op, size;
  747. /*
  748. * Hyundai HY93C46 or equivalent serial EEPROM.
  749. * This sequence for reading a 16-bit register 'r'
  750. * in the EEPROM is taken straight from Section
  751. * 3.3.4.2 of the Intel 82557 User's Guide.
  752. */
  753. reread:
  754. csr16w(ctlr, Ecr, EEcs);
  755. op = EEstart|EEread;
  756. for(i = 2; i >= 0; i--){
  757. data = (((op>>i) & 0x01)<<2)|EEcs;
  758. csr16w(ctlr, Ecr, data);
  759. csr16w(ctlr, Ecr, data|EEsk);
  760. microdelay(1);
  761. csr16w(ctlr, Ecr, data);
  762. microdelay(1);
  763. }
  764. /*
  765. * First time through must work out the EEPROM size.
  766. */
  767. if((size = ctlr->eepromsz) == 0)
  768. size = 8;
  769. for(size = size-1; size >= 0; size--){
  770. data = (((r>>size) & 0x01)<<2)|EEcs;
  771. csr16w(ctlr, Ecr, data);
  772. csr16w(ctlr, Ecr, data|EEsk);
  773. delay(1);
  774. csr16w(ctlr, Ecr, data);
  775. microdelay(1);
  776. if(!(csr16r(ctlr, Ecr) & EEdo))
  777. break;
  778. }
  779. data = 0;
  780. for(i = 15; i >= 0; i--){
  781. csr16w(ctlr, Ecr, EEcs|EEsk);
  782. microdelay(1);
  783. if(csr16r(ctlr, Ecr) & EEdo)
  784. data |= (1<<i);
  785. csr16w(ctlr, Ecr, EEcs);
  786. microdelay(1);
  787. }
  788. csr16w(ctlr, Ecr, 0);
  789. if(ctlr->eepromsz == 0){
  790. ctlr->eepromsz = 8-size;
  791. ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort));
  792. goto reread;
  793. }
  794. return data;
  795. }
  796. static void
  797. i82557pci(void)
  798. {
  799. Pcidev *p;
  800. Ctlr *ctlr;
  801. int i, nop, port;
  802. p = nil;
  803. nop = 0;
  804. while(p = pcimatch(p, 0x8086, 0)){
  805. switch(p->did){
  806. default:
  807. continue;
  808. case 0x1031: /* Intel 82562EM */
  809. case 0x1050: /* Intel 82562EZ */
  810. case 0x1039: /* Intel 82801BD PRO/100 VE */
  811. case 0x103A: /* Intel 82562 PRO/100 VE */
  812. case 0x103D: /* Intel 82562 PRO/100 VE */
  813. case 0x1064: /* Intel 82562 PRO/100 VE */
  814. case 0x2449: /* Intel 82562ET */
  815. nop = 1;
  816. /*FALLTHROUGH*/
  817. case 0x1209: /* Intel 82559ER */
  818. case 0x1229: /* Intel 8255[789] */
  819. case 0x1030: /* Intel 82559 InBusiness 10/100 */
  820. break;
  821. }
  822. if(pcigetpms(p) > 0){
  823. pcisetpms(p, 0);
  824. for(i = 0; i < 6; i++)
  825. pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar);
  826. pcicfgw8(p, PciINTL, p->intl);
  827. pcicfgw8(p, PciLTR, p->ltr);
  828. pcicfgw8(p, PciCLS, p->cls);
  829. pcicfgw16(p, PciPCR, p->pcr);
  830. }
  831. /*
  832. * bar[0] is the memory-mapped register address (4KB),
  833. * bar[1] is the I/O port register address (32 bytes) and
  834. * bar[2] is for the flash ROM (1MB).
  835. */
  836. port = p->mem[1].bar & ~0x01;
  837. if(ioalloc(port, p->mem[1].size, 0, "i82557") < 0){
  838. print("i82557: port %#ux in use\n", port);
  839. continue;
  840. }
  841. ctlr = malloc(sizeof(Ctlr));
  842. ctlr->port = port;
  843. ctlr->pcidev = p;
  844. ctlr->nop = nop;
  845. if(ctlrhead != nil)
  846. ctlrtail->next = ctlr;
  847. else
  848. ctlrhead = ctlr;
  849. ctlrtail = ctlr;
  850. pcisetbme(p);
  851. }
  852. }
  853. static char* mediatable[9] = {
  854. "10BASE-T", /* TP */
  855. "10BASE-2", /* BNC */
  856. "10BASE-5", /* AUI */
  857. "100BASE-TX",
  858. "10BASE-TFD",
  859. "100BASE-TXFD",
  860. "100BASE-T4",
  861. "100BASE-FX",
  862. "100BASE-FXFD",
  863. };
  864. static int
  865. scanphy(Ctlr* ctlr)
  866. {
  867. int i, oui, x;
  868. for(i = 0; i < 32; i++){
  869. if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF)
  870. continue;
  871. oui <<= 6;
  872. x = miir(ctlr, i, 3);
  873. oui |= x>>10;
  874. //print("phy%d: oui %#ux reg1 %#ux\n", i, oui, miir(ctlr, i, 1));
  875. ctlr->eeprom[6] = i;
  876. if(oui == 0xAA00)
  877. ctlr->eeprom[6] |= 0x07<<8;
  878. else if(oui == 0x80017){
  879. if(x & 0x01)
  880. ctlr->eeprom[6] |= 0x0A<<8;
  881. else
  882. ctlr->eeprom[6] |= 0x04<<8;
  883. }
  884. return i;
  885. }
  886. return -1;
  887. }
  888. static void
  889. shutdown(Ether* ether)
  890. {
  891. Ctlr *ctlr = ether->ctlr;
  892. print("ether82557 shutting down\n");
  893. csr32w(ctlr, Port, 0);
  894. delay(1);
  895. csr8w(ctlr, Interrupt, InterruptM);
  896. }
  897. static int
  898. reset(Ether* ether)
  899. {
  900. int anar, anlpar, bmcr, bmsr, i, k, medium, phyaddr, x;
  901. unsigned short sum;
  902. uchar ea[Eaddrlen];
  903. Ctlr *ctlr;
  904. if(ctlrhead == nil)
  905. i82557pci();
  906. /*
  907. * Any adapter matches if no ether->port is supplied,
  908. * otherwise the ports must match.
  909. */
  910. for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
  911. if(ctlr->active)
  912. continue;
  913. if(ether->port == 0 || ether->port == ctlr->port){
  914. ctlr->active = 1;
  915. break;
  916. }
  917. }
  918. if(ctlr == nil)
  919. return -1;
  920. /*
  921. * Initialise the Ctlr structure.
  922. * Perform a software reset after which should ensure busmastering
  923. * is still enabled. The EtherExpress PRO/100B appears to leave
  924. * the PCI configuration alone (see the 'To do' list above) so punt
  925. * for now.
  926. * Load the RUB and CUB registers for linear addressing (0).
  927. */
  928. ether->ctlr = ctlr;
  929. ether->port = ctlr->port;
  930. ether->irq = ctlr->pcidev->intl;
  931. ether->tbdf = ctlr->pcidev->tbdf;
  932. ilock(&ctlr->rlock);
  933. csr32w(ctlr, Port, 0);
  934. delay(1);
  935. csr8w(ctlr, Interrupt, InterruptM);
  936. iunlock(&ctlr->rlock);
  937. command(ctlr, LoadRUB, 0);
  938. command(ctlr, LoadCUB, 0);
  939. command(ctlr, LoadDCA, PADDR(ctlr->dump));
  940. /*
  941. * Initialise the receive frame, transmit ring and configuration areas.
  942. */
  943. ctlr->ncb = Ncb;
  944. ctlrinit(ctlr);
  945. /*
  946. * Read the EEPROM.
  947. * Do a dummy read first to get the size
  948. * and allocate ctlr->eeprom.
  949. */
  950. hy93c46r(ctlr, 0);
  951. sum = 0;
  952. for(i = 0; i < (1<<ctlr->eepromsz); i++){
  953. x = hy93c46r(ctlr, i);
  954. ctlr->eeprom[i] = x;
  955. sum += x;
  956. }
  957. if(sum != 0xBABA)
  958. print("#l%d: EEPROM checksum - %#4.4ux\n", ether->ctlrno, sum);
  959. /*
  960. * Eeprom[6] indicates whether there is a PHY and whether
  961. * it's not 10Mb-only, in which case use the given PHY address
  962. * to set any PHY specific options and determine the speed.
  963. * Unfortunately, sometimes the EEPROM is blank except for
  964. * the ether address and checksum; in this case look at the
  965. * controller type and if it's am 82558 or 82559 it has an
  966. * embedded PHY so scan for that.
  967. * If no PHY, assume 82503 (serial) operation.
  968. */
  969. if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000))
  970. phyaddr = ctlr->eeprom[6] & 0x00FF;
  971. else
  972. switch(ctlr->pcidev->rid){
  973. case 0x01: /* 82557 A-step */
  974. case 0x02: /* 82557 B-step */
  975. case 0x03: /* 82557 C-step */
  976. default:
  977. phyaddr = -1;
  978. break;
  979. case 0x04: /* 82558 A-step */
  980. case 0x05: /* 82558 B-step */
  981. case 0x06: /* 82559 A-step */
  982. case 0x07: /* 82559 B-step */
  983. case 0x08: /* 82559 C-step */
  984. case 0x09: /* 82559ER A-step */
  985. phyaddr = scanphy(ctlr);
  986. break;
  987. }
  988. if(phyaddr >= 0){
  989. /*
  990. * Resolve the highest common ability of the two
  991. * link partners. In descending order:
  992. * 0x0100 100BASE-TX Full Duplex
  993. * 0x0200 100BASE-T4
  994. * 0x0080 100BASE-TX
  995. * 0x0040 10BASE-T Full Duplex
  996. * 0x0020 10BASE-T
  997. */
  998. anar = miir(ctlr, phyaddr, 0x04);
  999. anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
  1000. anar &= anlpar;
  1001. bmcr = 0;
  1002. if(anar & 0x380)
  1003. bmcr = 0x2000;
  1004. if(anar & 0x0140)
  1005. bmcr |= 0x0100;
  1006. switch((ctlr->eeprom[6]>>8) & 0x001F){
  1007. case 0x04: /* DP83840 */
  1008. case 0x0A: /* DP83840A */
  1009. /*
  1010. * The DP83840[A] requires some tweaking for
  1011. * reliable operation.
  1012. * The manual says bit 10 should be unconditionally
  1013. * set although it supposedly only affects full-duplex
  1014. * operation (an & 0x0140).
  1015. */
  1016. x = miir(ctlr, phyaddr, 0x17) & ~0x0520;
  1017. x |= 0x0420;
  1018. for(i = 0; i < ether->nopt; i++){
  1019. if(cistrcmp(ether->opt[i], "congestioncontrol"))
  1020. continue;
  1021. x |= 0x0100;
  1022. break;
  1023. }
  1024. miiw(ctlr, phyaddr, 0x17, x);
  1025. /*
  1026. * If the link partner can't autonegotiate, determine
  1027. * the speed from elsewhere.
  1028. */
  1029. if(anlpar == 0){
  1030. miir(ctlr, phyaddr, 0x01);
  1031. bmsr = miir(ctlr, phyaddr, 0x01);
  1032. x = miir(ctlr, phyaddr, 0x19);
  1033. if((bmsr & 0x0004) && !(x & 0x0040))
  1034. bmcr = 0x2000;
  1035. }
  1036. break;
  1037. case 0x07: /* Intel 82555 */
  1038. /*
  1039. * Auto-negotiation may fail if the other end is
  1040. * a DP83840A and the cable is short.
  1041. */
  1042. miir(ctlr, phyaddr, 0x01);
  1043. bmsr = miir(ctlr, phyaddr, 0x01);
  1044. if((miir(ctlr, phyaddr, 0) & 0x1000) && !(bmsr & 0x0020)){
  1045. miiw(ctlr, phyaddr, 0x1A, 0x2010);
  1046. x = miir(ctlr, phyaddr, 0);
  1047. miiw(ctlr, phyaddr, 0, 0x0200|x);
  1048. for(i = 0; i < 3000; i++){
  1049. delay(1);
  1050. if(miir(ctlr, phyaddr, 0x01) & 0x0020)
  1051. break;
  1052. }
  1053. miiw(ctlr, phyaddr, 0x1A, 0x2000);
  1054. anar = miir(ctlr, phyaddr, 0x04);
  1055. anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0;
  1056. anar &= anlpar;
  1057. bmcr = 0;
  1058. if(anar & 0x380)
  1059. bmcr = 0x2000;
  1060. if(anar & 0x0140)
  1061. bmcr |= 0x0100;
  1062. }
  1063. break;
  1064. }
  1065. /*
  1066. * Force speed and duplex if no auto-negotiation.
  1067. */
  1068. if(anlpar == 0){
  1069. medium = -1;
  1070. for(i = 0; i < ether->nopt; i++){
  1071. for(k = 0; k < nelem(mediatable); k++){
  1072. if(cistrcmp(mediatable[k], ether->opt[i]))
  1073. continue;
  1074. medium = k;
  1075. break;
  1076. }
  1077. switch(medium){
  1078. default:
  1079. break;
  1080. case 0x00: /* 10BASE-T */
  1081. case 0x01: /* 10BASE-2 */
  1082. case 0x02: /* 10BASE-5 */
  1083. bmcr &= ~(0x2000|0x0100);
  1084. ctlr->configdata[19] &= ~0x40;
  1085. break;
  1086. case 0x03: /* 100BASE-TX */
  1087. case 0x06: /* 100BASE-T4 */
  1088. case 0x07: /* 100BASE-FX */
  1089. ctlr->configdata[19] &= ~0x40;
  1090. bmcr |= 0x2000;
  1091. break;
  1092. case 0x04: /* 10BASE-TFD */
  1093. bmcr = (bmcr & ~0x2000)|0x0100;
  1094. ctlr->configdata[19] |= 0x40;
  1095. break;
  1096. case 0x05: /* 100BASE-TXFD */
  1097. case 0x08: /* 100BASE-FXFD */
  1098. bmcr |= 0x2000|0x0100;
  1099. ctlr->configdata[19] |= 0x40;
  1100. break;
  1101. }
  1102. }
  1103. if(medium != -1)
  1104. miiw(ctlr, phyaddr, 0x00, bmcr);
  1105. }
  1106. if(bmcr & 0x2000)
  1107. ether->mbps = 100;
  1108. ctlr->configdata[8] = 1;
  1109. ctlr->configdata[15] &= ~0x80;
  1110. }
  1111. else{
  1112. ctlr->configdata[8] = 0;
  1113. ctlr->configdata[15] |= 0x80;
  1114. }
  1115. /*
  1116. * Workaround for some broken HUB chips when connected at 10Mb/s
  1117. * half-duplex.
  1118. * This is a band-aid, but as there's no dynamic auto-negotiation
  1119. * code at the moment, only deactivate the workaround code in txstart
  1120. * if the link is 100Mb/s.
  1121. */
  1122. if(ether->mbps != 10)
  1123. ctlr->nop = 0;
  1124. /*
  1125. * Load the chip configuration and start it off.
  1126. */
  1127. if(ether->oq == 0)
  1128. ether->oq = qopen(256*1024, Qmsg, 0, 0);
  1129. configure(ether, 0);
  1130. command(ctlr, CUstart, PADDR(&ctlr->cbr->status));
  1131. /*
  1132. * Check if the adapter's station address is to be overridden.
  1133. * If not, read it from the EEPROM and set in ether->ea prior to loading
  1134. * the station address with the Individual Address Setup command.
  1135. */
  1136. memset(ea, 0, Eaddrlen);
  1137. if(memcmp(ea, ether->ea, Eaddrlen) == 0){
  1138. for(i = 0; i < Eaddrlen/2; i++){
  1139. x = ctlr->eeprom[i];
  1140. ether->ea[2*i] = x;
  1141. ether->ea[2*i+1] = x>>8;
  1142. }
  1143. }
  1144. ilock(&ctlr->cblock);
  1145. ctlr->action = CbIAS;
  1146. txstart(ether);
  1147. iunlock(&ctlr->cblock);
  1148. /*
  1149. * Linkage to the generic ethernet driver.
  1150. */
  1151. ether->attach = attach;
  1152. ether->transmit = transmit;
  1153. ether->interrupt = interrupt;
  1154. ether->ifstat = ifstat;
  1155. ether->shutdown = shutdown;
  1156. ether->promiscuous = promiscuous;
  1157. ether->multicast = multicast;
  1158. ether->arg = ether;
  1159. return 0;
  1160. }
  1161. void
  1162. ether82557link(void)
  1163. {
  1164. addethercard("i82557", reset);
  1165. }