etherigbe.c 44 KB

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  1. /*
  2. * Intel 8254[340]NN Gigabit Ethernet Controller
  3. * as found on the Intel PRO/1000 series of adapters:
  4. * 82543GC Intel PRO/1000 T
  5. * 82544EI Intel PRO/1000 XT
  6. * 82540EM Intel PRO/1000 MT
  7. * 82541[GP]I
  8. * 82547GI
  9. * 82546GB
  10. * 82546EB
  11. * To Do:
  12. * finish autonegotiation code;
  13. * integrate fiber stuff back in (this ONLY handles
  14. * the CAT5 cards at the moment);
  15. * add checksum-offload;
  16. * add tuning control via ctl file;
  17. * this driver is little-endian specific.
  18. */
  19. #include "u.h"
  20. #include "../port/lib.h"
  21. #include "mem.h"
  22. #include "dat.h"
  23. #include "fns.h"
  24. #include "io.h"
  25. #include "../port/error.h"
  26. #include "../port/netif.h"
  27. #include "etherif.h"
  28. #include "ethermii.h"
  29. enum {
  30. i82542 = (0x1000<<16)|0x8086,
  31. i82543gc = (0x1004<<16)|0x8086,
  32. i82544ei = (0x1008<<16)|0x8086,
  33. i82547ei = (0x1019<<16)|0x8086,
  34. i82540em = (0x100E<<16)|0x8086,
  35. i82540eplp = (0x101E<<16)|0x8086,
  36. i82545gmc = (0x1026<<16)|0x8086,
  37. i82547gi = (0x1075<<16)|0x8086,
  38. i82541gi = (0x1076<<16)|0x8086,
  39. i82541gi2 = (0x1077<<16)|0x8086,
  40. i82546gb = (0x1079<<16)|0x8086,
  41. i82541pi = (0x107c<<16)|0x8086,
  42. i82546eb = (0x1010<<16)|0x8086,
  43. };
  44. enum {
  45. Ctrl = 0x00000000, /* Device Control */
  46. Ctrldup = 0x00000004, /* Device Control Duplicate */
  47. Status = 0x00000008, /* Device Status */
  48. Eecd = 0x00000010, /* EEPROM/Flash Control/Data */
  49. Ctrlext = 0x00000018, /* Extended Device Control */
  50. Mdic = 0x00000020, /* MDI Control */
  51. Fcal = 0x00000028, /* Flow Control Address Low */
  52. Fcah = 0x0000002C, /* Flow Control Address High */
  53. Fct = 0x00000030, /* Flow Control Type */
  54. Icr = 0x000000C0, /* Interrupt Cause Read */
  55. Ics = 0x000000C8, /* Interrupt Cause Set */
  56. Ims = 0x000000D0, /* Interrupt Mask Set/Read */
  57. Imc = 0x000000D8, /* Interrupt mask Clear */
  58. Rctl = 0x00000100, /* Receive Control */
  59. Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
  60. Txcw = 0x00000178, /* Transmit Configuration Word */
  61. Rxcw = 0x00000180, /* Receive Configuration Word */
  62. /* on the oldest cards (8254[23]), the Mta register is at 0x200 */
  63. Tctl = 0x00000400, /* Transmit Control */
  64. Tipg = 0x00000410, /* Transmit IPG */
  65. Tbt = 0x00000448, /* Transmit Burst Timer */
  66. Ait = 0x00000458, /* Adaptive IFS Throttle */
  67. Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
  68. Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
  69. Rdfh = 0x00002410, /* Receive data fifo head */
  70. Rdft = 0x00002418, /* Receive data fifo tail */
  71. Rdfhs = 0x00002420, /* Receive data fifo head saved */
  72. Rdfts = 0x00002428, /* Receive data fifo tail saved */
  73. Rdfpc = 0x00002430, /* Receive data fifo packet count */
  74. Rdbal = 0x00002800, /* Rd Base Address Low */
  75. Rdbah = 0x00002804, /* Rd Base Address High */
  76. Rdlen = 0x00002808, /* Receive Descriptor Length */
  77. Rdh = 0x00002810, /* Receive Descriptor Head */
  78. Rdt = 0x00002818, /* Receive Descriptor Tail */
  79. Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
  80. Rxdctl = 0x00002828, /* Receive Descriptor Control */
  81. Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
  82. Txdmac = 0x00003000, /* Transfer DMA Control */
  83. Ett = 0x00003008, /* Early Transmit Control */
  84. Tdfh = 0x00003410, /* Transmit data fifo head */
  85. Tdft = 0x00003418, /* Transmit data fifo tail */
  86. Tdfhs = 0x00003420, /* Transmit data Fifo Head saved */
  87. Tdfts = 0x00003428, /* Transmit data fifo tail saved */
  88. Tdfpc = 0x00003430, /* Trasnmit data Fifo packet count */
  89. Tdbal = 0x00003800, /* Td Base Address Low */
  90. Tdbah = 0x00003804, /* Td Base Address High */
  91. Tdlen = 0x00003808, /* Transmit Descriptor Length */
  92. Tdh = 0x00003810, /* Transmit Descriptor Head */
  93. Tdt = 0x00003818, /* Transmit Descriptor Tail */
  94. Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
  95. Txdctl = 0x00003828, /* Transmit Descriptor Control */
  96. Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
  97. Statistics = 0x00004000, /* Start of Statistics Area */
  98. Gorcl = 0x88/4, /* Good Octets Received Count */
  99. Gotcl = 0x90/4, /* Good Octets Transmitted Count */
  100. Torl = 0xC0/4, /* Total Octets Received */
  101. Totl = 0xC8/4, /* Total Octets Transmitted */
  102. Nstatistics = 64,
  103. Rxcsum = 0x00005000, /* Receive Checksum Control */
  104. Mta = 0x00005200, /* Multicast Table Array */
  105. Ral = 0x00005400, /* Receive Address Low */
  106. Rah = 0x00005404, /* Receive Address High */
  107. Manc = 0x00005820, /* Management Control */
  108. };
  109. enum { /* Ctrl */
  110. Bem = 0x00000002, /* Big Endian Mode */
  111. Prior = 0x00000004, /* Priority on the PCI bus */
  112. Lrst = 0x00000008, /* Link Reset */
  113. Asde = 0x00000020, /* Auto-Speed Detection Enable */
  114. Slu = 0x00000040, /* Set Link Up */
  115. Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */
  116. SspeedMASK = 0x00000300, /* Speed Selection */
  117. SspeedSHIFT = 8,
  118. Sspeed10 = 0x00000000, /* 10Mb/s */
  119. Sspeed100 = 0x00000100, /* 100Mb/s */
  120. Sspeed1000 = 0x00000200, /* 1000Mb/s */
  121. Frcspd = 0x00000800, /* Force Speed */
  122. Frcdplx = 0x00001000, /* Force Duplex */
  123. SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
  124. SwdpinsloSHIFT = 18,
  125. SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
  126. SwdpioloSHIFT = 22,
  127. Devrst = 0x04000000, /* Device Reset */
  128. Rfce = 0x08000000, /* Receive Flow Control Enable */
  129. Tfce = 0x10000000, /* Transmit Flow Control Enable */
  130. Vme = 0x40000000, /* VLAN Mode Enable */
  131. };
  132. enum { /* Status */
  133. Lu = 0x00000002, /* Link Up */
  134. Tckok = 0x00000004, /* Transmit clock is running */
  135. Rbcok = 0x00000008, /* Receive clock is running */
  136. Txoff = 0x00000010, /* Transmission Paused */
  137. Tbimode = 0x00000020, /* TBI Mode Indication */
  138. LspeedMASK = 0x000000C0, /* Link Speed Setting */
  139. LspeedSHIFT = 6,
  140. Lspeed10 = 0x00000000, /* 10Mb/s */
  141. Lspeed100 = 0x00000040, /* 100Mb/s */
  142. Lspeed1000 = 0x00000080, /* 1000Mb/s */
  143. Mtxckok = 0x00000400, /* MTX clock is running */
  144. Pci66 = 0x00000800, /* PCI Bus speed indication */
  145. Bus64 = 0x00001000, /* PCI Bus width indication */
  146. Pcixmode = 0x00002000, /* PCI-X mode */
  147. PcixspeedMASK = 0x0000C000, /* PCI-X bus speed */
  148. PcixspeedSHIFT = 14,
  149. Pcix66 = 0x00000000, /* 50-66MHz */
  150. Pcix100 = 0x00004000, /* 66-100MHz */
  151. Pcix133 = 0x00008000, /* 100-133MHz */
  152. };
  153. enum { /* Ctrl and Status */
  154. Fd = 0x00000001, /* Full-Duplex */
  155. AsdvMASK = 0x00000300,
  156. AsdvSHIFT = 8,
  157. Asdv10 = 0x00000000, /* 10Mb/s */
  158. Asdv100 = 0x00000100, /* 100Mb/s */
  159. Asdv1000 = 0x00000200, /* 1000Mb/s */
  160. };
  161. enum { /* Eecd */
  162. Sk = 0x00000001, /* Clock input to the EEPROM */
  163. Cs = 0x00000002, /* Chip Select */
  164. Di = 0x00000004, /* Data Input to the EEPROM */
  165. Do = 0x00000008, /* Data Output from the EEPROM */
  166. Areq = 0x00000040, /* EEPROM Access Request */
  167. Agnt = 0x00000080, /* EEPROM Access Grant */
  168. Eepresent = 0x00000100, /* EEPROM Present */
  169. Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */
  170. Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */
  171. Spi = 0x00002000, /* EEPROM is SPI not Microwire */
  172. };
  173. enum { /* Ctrlext */
  174. Gpien = 0x0000000F, /* General Purpose Interrupt Enables */
  175. SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */
  176. SwdpinshiSHIFT = 4,
  177. SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */
  178. SwdpiohiSHIFT = 8,
  179. Asdchk = 0x00001000, /* ASD Check */
  180. Eerst = 0x00002000, /* EEPROM Reset */
  181. Ips = 0x00004000, /* Invert Power State */
  182. Spdbyps = 0x00008000, /* Speed Select Bypass */
  183. };
  184. enum { /* EEPROM content offsets */
  185. Ea = 0x00, /* Ethernet Address */
  186. Cf = 0x03, /* Compatibility Field */
  187. Pba = 0x08, /* Printed Board Assembly number */
  188. Icw1 = 0x0A, /* Initialization Control Word 1 */
  189. Sid = 0x0B, /* Subsystem ID */
  190. Svid = 0x0C, /* Subsystem Vendor ID */
  191. Did = 0x0D, /* Device ID */
  192. Vid = 0x0E, /* Vendor ID */
  193. Icw2 = 0x0F, /* Initialization Control Word 2 */
  194. };
  195. enum { /* Mdic */
  196. MDIdMASK = 0x0000FFFF, /* Data */
  197. MDIdSHIFT = 0,
  198. MDIrMASK = 0x001F0000, /* PHY Register Address */
  199. MDIrSHIFT = 16,
  200. MDIpMASK = 0x03E00000, /* PHY Address */
  201. MDIpSHIFT = 21,
  202. MDIwop = 0x04000000, /* Write Operation */
  203. MDIrop = 0x08000000, /* Read Operation */
  204. MDIready = 0x10000000, /* End of Transaction */
  205. MDIie = 0x20000000, /* Interrupt Enable */
  206. MDIe = 0x40000000, /* Error */
  207. };
  208. enum { /* Icr, Ics, Ims, Imc */
  209. Txdw = 0x00000001, /* Transmit Descriptor Written Back */
  210. Txqe = 0x00000002, /* Transmit Queue Empty */
  211. Lsc = 0x00000004, /* Link Status Change */
  212. Rxseq = 0x00000008, /* Receive Sequence Error */
  213. Rxdmt0 = 0x00000010, /* Rd Minimum Threshold Reached */
  214. Rxo = 0x00000040, /* Receiver Overrun */
  215. Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
  216. Mdac = 0x00000200, /* MDIO Access Completed */
  217. Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
  218. Gpi0 = 0x00000800, /* General Purpose Interrupts */
  219. Gpi1 = 0x00001000,
  220. Gpi2 = 0x00002000,
  221. Gpi3 = 0x00004000,
  222. };
  223. /*
  224. * The Mdic register isn't implemented on the 82543GC,
  225. * the software defined pins are used instead.
  226. * These definitions work for the Intel PRO/1000 T Server Adapter.
  227. * The direction pin bits are read from the EEPROM.
  228. */
  229. enum {
  230. Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */
  231. Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */
  232. Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */
  233. Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */
  234. Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */
  235. Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */
  236. };
  237. enum { /* Txcw */
  238. TxcwFd = 0x00000020, /* Full Duplex */
  239. TxcwHd = 0x00000040, /* Half Duplex */
  240. TxcwPauseMASK = 0x00000180, /* Pause */
  241. TxcwPauseSHIFT = 7,
  242. TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
  243. TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
  244. TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
  245. TxcwRfiSHIFT = 12,
  246. TxcwNpr = 0x00008000, /* Next Page Request */
  247. TxcwConfig = 0x40000000, /* Transmit COnfig Control */
  248. TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
  249. };
  250. enum { /* Rxcw */
  251. Rxword = 0x0000FFFF, /* Data from auto-negotiation process */
  252. Rxnocarrier = 0x04000000, /* Carrier Sense indication */
  253. Rxinvalid = 0x08000000, /* Invalid Symbol during configuration */
  254. Rxchange = 0x10000000, /* Change to the Rxword indication */
  255. Rxconfig = 0x20000000, /* /C/ order set reception indication */
  256. Rxsync = 0x40000000, /* Lost bit synchronization indication */
  257. Anc = 0x80000000, /* Auto Negotiation Complete */
  258. };
  259. enum { /* Rctl */
  260. Rrst = 0x00000001, /* Receiver Software Reset */
  261. Ren = 0x00000002, /* Receiver Enable */
  262. Sbp = 0x00000004, /* Store Bad Packets */
  263. Upe = 0x00000008, /* Unicast Promiscuous Enable */
  264. Mpe = 0x00000010, /* Multicast Promiscuous Enable */
  265. Lpe = 0x00000020, /* Long Packet Reception Enable */
  266. LbmMASK = 0x000000C0, /* Loopback Mode */
  267. LbmOFF = 0x00000000, /* No Loopback */
  268. LbmTBI = 0x00000040, /* TBI Loopback */
  269. LbmMII = 0x00000080, /* GMII/MII Loopback */
  270. LbmXCVR = 0x000000C0, /* Transceiver Loopback */
  271. RdtmsMASK = 0x00000300, /* Rd Minimum Threshold Size */
  272. RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
  273. RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
  274. RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
  275. MoMASK = 0x00003000, /* Multicast Offset */
  276. Mo47b36 = 0x00000000, /* bits [47:36] of received address */
  277. Mo46b35 = 0x00001000, /* bits [46:35] of received address */
  278. Mo45b34 = 0x00002000, /* bits [45:34] of received address */
  279. Mo43b32 = 0x00003000, /* bits [43:32] of received address */
  280. Bam = 0x00008000, /* Broadcast Accept Mode */
  281. BsizeMASK = 0x00030000, /* Receive Buffer Size */
  282. Bsize2048 = 0x00000000, /* Bsex = 0 */
  283. Bsize1024 = 0x00010000, /* Bsex = 0 */
  284. Bsize512 = 0x00020000, /* Bsex = 0 */
  285. Bsize256 = 0x00030000, /* Bsex = 0 */
  286. Bsize16384 = 0x00010000, /* Bsex = 1 */
  287. Vfe = 0x00040000, /* VLAN Filter Enable */
  288. Cfien = 0x00080000, /* Canonical Form Indicator Enable */
  289. Cfi = 0x00100000, /* Canonical Form Indicator value */
  290. Dpf = 0x00400000, /* Discard Pause Frames */
  291. Pmcf = 0x00800000, /* Pass MAC Control Frames */
  292. Bsex = 0x02000000, /* Buffer Size Extension */
  293. Secrc = 0x04000000, /* Strip CRC from incoming packet */
  294. };
  295. enum { /* Tctl */
  296. Trst = 0x00000001, /* Transmitter Software Reset */
  297. Ten = 0x00000002, /* Transmit Enable */
  298. Psp = 0x00000008, /* Pad Short Packets */
  299. CtMASK = 0x00000FF0, /* Collision Threshold */
  300. CtSHIFT = 4,
  301. ColdMASK = 0x003FF000, /* Collision Distance */
  302. ColdSHIFT = 12,
  303. Swxoff = 0x00400000, /* Sofware XOFF Transmission */
  304. Pbe = 0x00800000, /* Packet Burst Enable */
  305. Rtlc = 0x01000000, /* Re-transmit on Late Collision */
  306. Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
  307. };
  308. enum { /* [RT]xdctl */
  309. PthreshMASK = 0x0000003F, /* Prefetch Threshold */
  310. PthreshSHIFT = 0,
  311. HthreshMASK = 0x00003F00, /* Host Threshold */
  312. HthreshSHIFT = 8,
  313. WthreshMASK = 0x003F0000, /* Writeback Threshold */
  314. WthreshSHIFT = 16,
  315. Gran = 0x01000000, /* Granularity */
  316. LthreshMASK = 0xFE000000, /* Low Threshold */
  317. LthreshSHIFT = 25,
  318. };
  319. enum { /* Rxcsum */
  320. PcssMASK = 0x000000FF, /* Packet Checksum Start */
  321. PcssSHIFT = 0,
  322. Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
  323. Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
  324. };
  325. enum { /* Manc */
  326. Arpen = 0x00002000, /* Enable ARP Request Filtering */
  327. };
  328. enum { /* Receive Delay Timer Ring */
  329. DelayMASK = 0x0000FFFF, /* delay timer in 1.024nS increments */
  330. DelaySHIFT = 0,
  331. Fpd = 0x80000000, /* Flush partial Descriptor Block */
  332. };
  333. typedef struct Rd { /* Receive Descriptor */
  334. uint addr[2];
  335. ushort length;
  336. ushort checksum;
  337. uchar status;
  338. uchar errors;
  339. ushort special;
  340. } Rd;
  341. enum { /* Rd status */
  342. Rdd = 0x01, /* Descriptor Done */
  343. Reop = 0x02, /* End of Packet */
  344. Ixsm = 0x04, /* Ignore Checksum Indication */
  345. Vp = 0x08, /* Packet is 802.1Q (matched VET) */
  346. Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
  347. Ipcs = 0x40, /* IP Checksum Calculated on Packet */
  348. Pif = 0x80, /* Passed in-exact filter */
  349. };
  350. enum { /* Rd errors */
  351. Ce = 0x01, /* CRC Error or Alignment Error */
  352. Se = 0x02, /* Symbol Error */
  353. Seq = 0x04, /* Sequence Error */
  354. Cxe = 0x10, /* Carrier Extension Error */
  355. Tcpe = 0x20, /* TCP/UDP Checksum Error */
  356. Ipe = 0x40, /* IP Checksum Error */
  357. Rxe = 0x80, /* RX Data Error */
  358. };
  359. typedef struct Td Td;
  360. struct Td { /* Transmit Descriptor */
  361. union {
  362. uint addr[2]; /* Data */
  363. struct { /* Context */
  364. uchar ipcss;
  365. uchar ipcso;
  366. ushort ipcse;
  367. uchar tucss;
  368. uchar tucso;
  369. ushort tucse;
  370. };
  371. };
  372. uint control;
  373. uint status;
  374. };
  375. enum { /* Td control */
  376. LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
  377. LenSHIFT = 0,
  378. DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
  379. DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
  380. PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
  381. Teop = 0x01000000, /* End of Packet (DD) */
  382. PtypeIP = 0x02000000, /* IP Packet Type (CD) */
  383. Ifcs = 0x02000000, /* Insert FCS (DD) */
  384. Tse = 0x04000000, /* TCP Segmentation Enable */
  385. Rs = 0x08000000, /* Report Status */
  386. Rps = 0x10000000, /* Report Status Sent */
  387. Dext = 0x20000000, /* Descriptor Extension */
  388. Vle = 0x40000000, /* VLAN Packet Enable */
  389. Ide = 0x80000000, /* Interrupt Delay Enable */
  390. };
  391. enum { /* Td status */
  392. Tdd = 0x00000001, /* Descriptor Done */
  393. Ec = 0x00000002, /* Excess Collisions */
  394. Lc = 0x00000004, /* Late Collision */
  395. Tu = 0x00000008, /* Transmit Underrun */
  396. Iixsm = 0x00000100, /* Insert IP Checksum */
  397. Itxsm = 0x00000200, /* Insert TCP/UDP Checksum */
  398. HdrlenMASK = 0x0000FF00, /* Header Length (Tse) */
  399. HdrlenSHIFT = 8,
  400. VlanMASK = 0x0FFF0000, /* VLAN Identifier */
  401. VlanSHIFT = 16,
  402. Tcfi = 0x10000000, /* Canonical Form Indicator */
  403. PriMASK = 0xE0000000, /* User Priority */
  404. PriSHIFT = 29,
  405. MssMASK = 0xFFFF0000, /* Maximum Segment Size (Tse) */
  406. MssSHIFT = 16,
  407. };
  408. enum {
  409. Nrd = 256, /* multiple of 8 */
  410. Ntd = 64, /* multiple of 8 */
  411. Nrb = 1024, /* private receive buffers per Ctlr */
  412. Rbsz = 2048,
  413. };
  414. typedef struct Ctlr Ctlr;
  415. typedef struct Ctlr {
  416. int port;
  417. Pcidev* pcidev;
  418. Ctlr* next;
  419. Ether* edev;
  420. int active;
  421. int started;
  422. int id;
  423. int cls;
  424. ushort eeprom[0x40];
  425. QLock alock; /* attach */
  426. void* alloc; /* receive/transmit descriptors */
  427. int nrd;
  428. int ntd;
  429. int nrb; /* how many this Ctlr has in the pool */
  430. int* nic;
  431. Lock imlock;
  432. int im; /* interrupt mask */
  433. Mii* mii;
  434. Rendez lrendez;
  435. int lim;
  436. int link;
  437. QLock slock;
  438. uint statistics[Nstatistics];
  439. uint lsleep;
  440. uint lintr;
  441. uint rsleep;
  442. uint rintr;
  443. uint txdw;
  444. uint tintr;
  445. uint ixsm;
  446. uint ipcs;
  447. uint tcpcs;
  448. uchar ra[Eaddrlen]; /* receive address */
  449. ulong mta[128]; /* multicast table array */
  450. Rendez rrendez;
  451. int rim;
  452. int rdfree;
  453. Rd* rdba; /* receive descriptor base address */
  454. Block** rb; /* receive buffers */
  455. int rdh; /* receive descriptor head */
  456. int rdt; /* receive descriptor tail */
  457. int rdtr; /* receive delay timer ring value */
  458. Lock tlock;
  459. int tbusy;
  460. int tdfree;
  461. Td* tdba; /* transmit descriptor base address */
  462. Block** tb; /* transmit buffers */
  463. int tdh; /* transmit descriptor head */
  464. int tdt; /* transmit descriptor tail */
  465. int txcw;
  466. int fcrtl;
  467. int fcrth;
  468. } Ctlr;
  469. #define csr32r(c, r) (*((c)->nic+((r)/4)))
  470. #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
  471. static Ctlr* igbectlrhead;
  472. static Ctlr* igbectlrtail;
  473. static Lock igberblock; /* free receive Blocks */
  474. static Block* igberbpool; /* receive Blocks for all igbe controllers */
  475. static char* statistics[Nstatistics] = {
  476. "CRC Error",
  477. "Alignment Error",
  478. "Symbol Error",
  479. "RX Error",
  480. "Missed Packets",
  481. "Single Collision",
  482. "Excessive Collisions",
  483. "Multiple Collision",
  484. "Late Collisions",
  485. nil,
  486. "Collision",
  487. "Transmit Underrun",
  488. "Defer",
  489. "Transmit - No CRS",
  490. "Sequence Error",
  491. "Carrier Extension Error",
  492. "Receive Error Length",
  493. nil,
  494. "XON Received",
  495. "XON Transmitted",
  496. "XOFF Received",
  497. "XOFF Transmitted",
  498. "FC Received Unsupported",
  499. "Packets Received (64 Bytes)",
  500. "Packets Received (65-127 Bytes)",
  501. "Packets Received (128-255 Bytes)",
  502. "Packets Received (256-511 Bytes)",
  503. "Packets Received (512-1023 Bytes)",
  504. "Packets Received (1024-1522 Bytes)",
  505. "Good Packets Received",
  506. "Broadcast Packets Received",
  507. "Multicast Packets Received",
  508. "Good Packets Transmitted",
  509. nil,
  510. "Good Octets Received",
  511. nil,
  512. "Good Octets Transmitted",
  513. nil,
  514. nil,
  515. nil,
  516. "Receive No Buffers",
  517. "Receive Undersize",
  518. "Receive Fragment",
  519. "Receive Oversize",
  520. "Receive Jabber",
  521. nil,
  522. nil,
  523. nil,
  524. "Total Octets Received",
  525. nil,
  526. "Total Octets Transmitted",
  527. nil,
  528. "Total Packets Received",
  529. "Total Packets Transmitted",
  530. "Packets Transmitted (64 Bytes)",
  531. "Packets Transmitted (65-127 Bytes)",
  532. "Packets Transmitted (128-255 Bytes)",
  533. "Packets Transmitted (256-511 Bytes)",
  534. "Packets Transmitted (512-1023 Bytes)",
  535. "Packets Transmitted (1024-1522 Bytes)",
  536. "Multicast Packets Transmitted",
  537. "Broadcast Packets Transmitted",
  538. "TCP Segmentation Context Transmitted",
  539. "TCP Segmentation Context Fail",
  540. };
  541. static long
  542. igbeifstat(Ether* edev, void* a, long n, ulong offset)
  543. {
  544. Ctlr *ctlr;
  545. char *p, *s;
  546. int i, l, r;
  547. uvlong tuvl, ruvl;
  548. ctlr = edev->ctlr;
  549. qlock(&ctlr->slock);
  550. p = malloc(2*READSTR);
  551. l = 0;
  552. for(i = 0; i < Nstatistics; i++){
  553. r = csr32r(ctlr, Statistics+i*4);
  554. if((s = statistics[i]) == nil)
  555. continue;
  556. switch(i){
  557. case Gorcl:
  558. case Gotcl:
  559. case Torl:
  560. case Totl:
  561. ruvl = r;
  562. ruvl += ((uvlong)csr32r(ctlr, Statistics+(i+1)*4))<<32;
  563. tuvl = ruvl;
  564. tuvl += ctlr->statistics[i];
  565. tuvl += ((uvlong)ctlr->statistics[i+1])<<32;
  566. if(tuvl == 0)
  567. continue;
  568. ctlr->statistics[i] = tuvl;
  569. ctlr->statistics[i+1] = tuvl>>32;
  570. l += snprint(p+l, 2*READSTR-l, "%s: %llud %llud\n",
  571. s, tuvl, ruvl);
  572. i++;
  573. break;
  574. default:
  575. ctlr->statistics[i] += r;
  576. if(ctlr->statistics[i] == 0)
  577. continue;
  578. l += snprint(p+l, 2*READSTR-l, "%s: %ud %ud\n",
  579. s, ctlr->statistics[i], r);
  580. break;
  581. }
  582. }
  583. l += snprint(p+l, 2*READSTR-l, "lintr: %ud %ud\n",
  584. ctlr->lintr, ctlr->lsleep);
  585. l += snprint(p+l, 2*READSTR-l, "rintr: %ud %ud\n",
  586. ctlr->rintr, ctlr->rsleep);
  587. l += snprint(p+l, 2*READSTR-l, "tintr: %ud %ud\n",
  588. ctlr->tintr, ctlr->txdw);
  589. l += snprint(p+l, 2*READSTR-l, "ixcs: %ud %ud %ud\n",
  590. ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs);
  591. l += snprint(p+l, 2*READSTR-l, "rdtr: %ud\n", ctlr->rdtr);
  592. l += snprint(p+l, 2*READSTR-l, "Ctrlext: %08x\n", csr32r(ctlr, Ctrlext));
  593. l += snprint(p+l, 2*READSTR-l, "eeprom:");
  594. for(i = 0; i < 0x40; i++){
  595. if(i && ((i & 0x07) == 0))
  596. l += snprint(p+l, 2*READSTR-l, "\n ");
  597. l += snprint(p+l, 2*READSTR-l, " %4.4uX", ctlr->eeprom[i]);
  598. }
  599. l += snprint(p+l, 2*READSTR-l, "\n");
  600. if(ctlr->mii != nil && ctlr->mii->curphy != nil){
  601. l += snprint(p+l, 2*READSTR, "phy: ");
  602. for(i = 0; i < NMiiPhyr; i++){
  603. if(i && ((i & 0x07) == 0))
  604. l += snprint(p+l, 2*READSTR-l, "\n ");
  605. r = miimir(ctlr->mii, i);
  606. l += snprint(p+l, 2*READSTR-l, " %4.4uX", r);
  607. }
  608. snprint(p+l, 2*READSTR-l, "\n");
  609. }
  610. n = readstr(offset, a, n, p);
  611. free(p);
  612. qunlock(&ctlr->slock);
  613. return n;
  614. }
  615. enum {
  616. CMrdtr,
  617. };
  618. static Cmdtab igbectlmsg[] = {
  619. CMrdtr, "rdtr", 2,
  620. };
  621. static long
  622. igbectl(Ether* edev, void* buf, long n)
  623. {
  624. int v;
  625. char *p;
  626. Ctlr *ctlr;
  627. Cmdbuf *cb;
  628. Cmdtab *ct;
  629. if((ctlr = edev->ctlr) == nil)
  630. error(Enonexist);
  631. cb = parsecmd(buf, n);
  632. if(waserror()){
  633. free(cb);
  634. nexterror();
  635. }
  636. ct = lookupcmd(cb, igbectlmsg, nelem(igbectlmsg));
  637. switch(ct->index){
  638. case CMrdtr:
  639. v = strtol(cb->f[1], &p, 0);
  640. if(v < 0 || p == cb->f[1] || v > 0xFFFF)
  641. error(Ebadarg);
  642. ctlr->rdtr = v;;
  643. csr32w(ctlr, Rdtr, Fpd|v);
  644. break;
  645. }
  646. free(cb);
  647. poperror();
  648. return n;
  649. }
  650. static void
  651. igbepromiscuous(void* arg, int on)
  652. {
  653. int rctl;
  654. Ctlr *ctlr;
  655. Ether *edev;
  656. edev = arg;
  657. ctlr = edev->ctlr;
  658. rctl = csr32r(ctlr, Rctl);
  659. rctl &= ~MoMASK;
  660. rctl |= Mo47b36;
  661. if(on)
  662. rctl |= Upe|Mpe;
  663. else
  664. rctl &= ~(Upe|Mpe);
  665. csr32w(ctlr, Rctl, rctl|Mpe); /* temporarily keep Mpe on */
  666. }
  667. static void
  668. igbemulticast(void* arg, uchar* addr, int add)
  669. {
  670. int bit, x;
  671. Ctlr *ctlr;
  672. Ether *edev;
  673. edev = arg;
  674. ctlr = edev->ctlr;
  675. x = addr[5]>>1;
  676. bit = ((addr[5] & 1)<<4)|(addr[4]>>4);
  677. /*
  678. * multiple ether addresses can hash to the same filter bit,
  679. * so it's never safe to clear a filter bit.
  680. * if we want to clear filter bits, we need to keep track of
  681. * all the multicast addresses in use, clear all the filter bits,
  682. * then set the ones corresponding to in-use addresses.
  683. */
  684. if(add)
  685. ctlr->mta[x] |= 1<<bit;
  686. // else
  687. // ctlr->mta[x] &= ~(1<<bit);
  688. csr32w(ctlr, Mta+x*4, ctlr->mta[x]);
  689. }
  690. static Block*
  691. igberballoc(void)
  692. {
  693. Block *bp;
  694. ilock(&igberblock);
  695. if((bp = igberbpool) != nil){
  696. igberbpool = bp->next;
  697. bp->next = nil;
  698. }
  699. iunlock(&igberblock);
  700. return bp;
  701. }
  702. static void
  703. igberbfree(Block* bp)
  704. {
  705. bp->rp = bp->lim - Rbsz;
  706. bp->wp = bp->rp;
  707. ilock(&igberblock);
  708. bp->next = igberbpool;
  709. igberbpool = bp;
  710. iunlock(&igberblock);
  711. }
  712. static void
  713. igbeim(Ctlr* ctlr, int im)
  714. {
  715. ilock(&ctlr->imlock);
  716. ctlr->im |= im;
  717. csr32w(ctlr, Ims, ctlr->im);
  718. iunlock(&ctlr->imlock);
  719. }
  720. static int
  721. igbelim(void* ctlr)
  722. {
  723. return ((Ctlr*)ctlr)->lim != 0;
  724. }
  725. static void
  726. igbelproc(void* arg)
  727. {
  728. Ctlr *ctlr;
  729. Ether *edev;
  730. MiiPhy *phy;
  731. int ctrl, r;
  732. edev = arg;
  733. ctlr = edev->ctlr;
  734. for(;;){
  735. if(ctlr->mii == nil || ctlr->mii->curphy == nil)
  736. continue;
  737. /*
  738. * To do:
  739. * logic to manage status change,
  740. * this is incomplete but should work
  741. * one time to set up the hardware.
  742. *
  743. * MiiPhy.speed, etc. should be in Mii.
  744. */
  745. if(miistatus(ctlr->mii) < 0)
  746. //continue;
  747. goto enable;
  748. phy = ctlr->mii->curphy;
  749. ctrl = csr32r(ctlr, Ctrl);
  750. switch(ctlr->id){
  751. case i82543gc:
  752. case i82544ei:
  753. default:
  754. if(!(ctrl & Asde)){
  755. ctrl &= ~(SspeedMASK|Ilos|Fd);
  756. ctrl |= Frcdplx|Frcspd;
  757. if(phy->speed == 1000)
  758. ctrl |= Sspeed1000;
  759. else if(phy->speed == 100)
  760. ctrl |= Sspeed100;
  761. if(phy->fd)
  762. ctrl |= Fd;
  763. }
  764. break;
  765. case i82540em:
  766. case i82540eplp:
  767. case i82547gi:
  768. case i82541gi:
  769. case i82541gi2:
  770. case i82541pi:
  771. break;
  772. }
  773. /*
  774. * Collision Distance.
  775. */
  776. r = csr32r(ctlr, Tctl);
  777. r &= ~ColdMASK;
  778. if(phy->fd)
  779. r |= 64<<ColdSHIFT;
  780. else
  781. r |= 512<<ColdSHIFT;
  782. csr32w(ctlr, Tctl, r);
  783. /*
  784. * Flow control.
  785. */
  786. if(phy->rfc)
  787. ctrl |= Rfce;
  788. if(phy->tfc)
  789. ctrl |= Tfce;
  790. csr32w(ctlr, Ctrl, ctrl);
  791. enable:
  792. ctlr->lim = 0;
  793. igbeim(ctlr, Lsc);
  794. ctlr->lsleep++;
  795. sleep(&ctlr->lrendez, igbelim, ctlr);
  796. }
  797. }
  798. static void
  799. igbetxinit(Ctlr* ctlr)
  800. {
  801. int i, r;
  802. Block *bp;
  803. csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT));
  804. switch(ctlr->id){
  805. default:
  806. r = 6;
  807. break;
  808. case i82543gc:
  809. case i82544ei:
  810. case i82547ei:
  811. case i82540em:
  812. case i82540eplp:
  813. case i82541gi:
  814. case i82541gi2:
  815. case i82541pi:
  816. case i82545gmc:
  817. case i82546gb:
  818. case i82546eb:
  819. case i82547gi:
  820. r = 8;
  821. break;
  822. }
  823. csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
  824. csr32w(ctlr, Ait, 0);
  825. csr32w(ctlr, Txdmac, 0);
  826. csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
  827. csr32w(ctlr, Tdbah, 0);
  828. csr32w(ctlr, Tdlen, ctlr->ntd*sizeof(Td));
  829. ctlr->tdh = PREV(0, ctlr->ntd);
  830. csr32w(ctlr, Tdh, 0);
  831. ctlr->tdt = 0;
  832. csr32w(ctlr, Tdt, 0);
  833. for(i = 0; i < ctlr->ntd; i++){
  834. if((bp = ctlr->tb[i]) != nil){
  835. ctlr->tb[i] = nil;
  836. freeb(bp);
  837. }
  838. memset(&ctlr->tdba[i], 0, sizeof(Td));
  839. }
  840. ctlr->tdfree = ctlr->ntd;
  841. csr32w(ctlr, Tidv, 128);
  842. r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
  843. switch(ctlr->id){
  844. default:
  845. break;
  846. case i82540em:
  847. case i82540eplp:
  848. case i82547gi:
  849. case i82545gmc:
  850. case i82546gb:
  851. case i82546eb:
  852. case i82541gi:
  853. case i82541gi2:
  854. case i82541pi:
  855. r = csr32r(ctlr, Txdctl);
  856. r &= ~WthreshMASK;
  857. r |= Gran|(4<<WthreshSHIFT);
  858. csr32w(ctlr, Tadv, 64);
  859. break;
  860. }
  861. csr32w(ctlr, Txdctl, r);
  862. r = csr32r(ctlr, Tctl);
  863. r |= Ten;
  864. csr32w(ctlr, Tctl, r);
  865. }
  866. static void
  867. igbetransmit(Ether* edev)
  868. {
  869. Td *td;
  870. Block *bp;
  871. Ctlr *ctlr;
  872. int tdh, tdt;
  873. ctlr = edev->ctlr;
  874. ilock(&ctlr->tlock);
  875. /*
  876. * Free any completed packets
  877. */
  878. tdh = ctlr->tdh;
  879. while(NEXT(tdh, ctlr->ntd) != csr32r(ctlr, Tdh)){
  880. if((bp = ctlr->tb[tdh]) != nil){
  881. ctlr->tb[tdh] = nil;
  882. freeb(bp);
  883. }
  884. memset(&ctlr->tdba[tdh], 0, sizeof(Td));
  885. tdh = NEXT(tdh, ctlr->ntd);
  886. }
  887. ctlr->tdh = tdh;
  888. /*
  889. * Try to fill the ring back up.
  890. */
  891. tdt = ctlr->tdt;
  892. while(NEXT(tdt, ctlr->ntd) != tdh){
  893. if((bp = qget(edev->oq)) == nil)
  894. break;
  895. td = &ctlr->tdba[tdt];
  896. td->addr[0] = PCIWADDR(bp->rp);
  897. td->control = ((BLEN(bp) & LenMASK)<<LenSHIFT);
  898. td->control |= Dext|Ifcs|Teop|DtypeDD;
  899. ctlr->tb[tdt] = bp;
  900. tdt = NEXT(tdt, ctlr->ntd);
  901. if(NEXT(tdt, ctlr->ntd) == tdh){
  902. td->control |= Rs;
  903. ctlr->txdw++;
  904. ctlr->tdt = tdt;
  905. csr32w(ctlr, Tdt, tdt);
  906. igbeim(ctlr, Txdw);
  907. break;
  908. }
  909. ctlr->tdt = tdt;
  910. csr32w(ctlr, Tdt, tdt);
  911. }
  912. iunlock(&ctlr->tlock);
  913. }
  914. static void
  915. igbereplenish(Ctlr* ctlr)
  916. {
  917. Rd *rd;
  918. int rdt;
  919. Block *bp;
  920. rdt = ctlr->rdt;
  921. while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){
  922. rd = &ctlr->rdba[rdt];
  923. if(ctlr->rb[rdt] == nil){
  924. bp = igberballoc();
  925. if(bp == nil){
  926. iprint("#l%d: igbereplenish: no available buffers\n",
  927. ctlr->edev->ctlrno);
  928. break;
  929. }
  930. ctlr->rb[rdt] = bp;
  931. rd->addr[0] = PCIWADDR(bp->rp);
  932. rd->addr[1] = 0;
  933. }
  934. coherence();
  935. rd->status = 0;
  936. rdt = NEXT(rdt, ctlr->nrd);
  937. ctlr->rdfree++;
  938. }
  939. ctlr->rdt = rdt;
  940. csr32w(ctlr, Rdt, rdt);
  941. }
  942. static void
  943. igberxinit(Ctlr* ctlr)
  944. {
  945. int i;
  946. Block *bp;
  947. /* temporarily keep Mpe on */
  948. csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF|Mpe);
  949. csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
  950. csr32w(ctlr, Rdbah, 0);
  951. csr32w(ctlr, Rdlen, ctlr->nrd*sizeof(Rd));
  952. ctlr->rdh = 0;
  953. csr32w(ctlr, Rdh, 0);
  954. ctlr->rdt = 0;
  955. csr32w(ctlr, Rdt, 0);
  956. ctlr->rdtr = 0;
  957. csr32w(ctlr, Rdtr, Fpd|0);
  958. for(i = 0; i < ctlr->nrd; i++){
  959. if((bp = ctlr->rb[i]) != nil){
  960. ctlr->rb[i] = nil;
  961. freeb(bp);
  962. }
  963. }
  964. igbereplenish(ctlr);
  965. switch(ctlr->id){
  966. case i82540em:
  967. case i82540eplp:
  968. case i82541gi:
  969. case i82541gi2:
  970. case i82541pi:
  971. case i82545gmc:
  972. case i82546gb:
  973. case i82546eb:
  974. case i82547gi:
  975. csr32w(ctlr, Radv, 64);
  976. break;
  977. }
  978. csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
  979. /*
  980. * Enable checksum offload.
  981. */
  982. csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT));
  983. }
  984. static int
  985. igberim(void* ctlr)
  986. {
  987. return ((Ctlr*)ctlr)->rim != 0;
  988. }
  989. static void
  990. igberproc(void* arg)
  991. {
  992. Rd *rd;
  993. Block *bp;
  994. Ctlr *ctlr;
  995. int r, rdh;
  996. Ether *edev;
  997. edev = arg;
  998. ctlr = edev->ctlr;
  999. igberxinit(ctlr);
  1000. r = csr32r(ctlr, Rctl);
  1001. r |= Ren;
  1002. csr32w(ctlr, Rctl, r);
  1003. for(;;){
  1004. ctlr->rim = 0;
  1005. igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
  1006. ctlr->rsleep++;
  1007. sleep(&ctlr->rrendez, igberim, ctlr);
  1008. rdh = ctlr->rdh;
  1009. for(;;){
  1010. rd = &ctlr->rdba[rdh];
  1011. if(!(rd->status & Rdd))
  1012. break;
  1013. /*
  1014. * Accept eop packets with no errors.
  1015. * With no errors and the Ixsm bit set,
  1016. * the descriptor status Tpcs and Ipcs bits give
  1017. * an indication of whether the checksums were
  1018. * calculated and valid.
  1019. */
  1020. if((rd->status & Reop) && rd->errors == 0){
  1021. bp = ctlr->rb[rdh];
  1022. ctlr->rb[rdh] = nil;
  1023. bp->wp += rd->length;
  1024. bp->next = nil;
  1025. if(!(rd->status & Ixsm)){
  1026. ctlr->ixsm++;
  1027. if(rd->status & Ipcs){
  1028. /*
  1029. * IP checksum calculated
  1030. * (and valid as errors == 0).
  1031. */
  1032. ctlr->ipcs++;
  1033. bp->flag |= Bipck;
  1034. }
  1035. if(rd->status & Tcpcs){
  1036. /*
  1037. * TCP/UDP checksum calculated
  1038. * (and valid as errors == 0).
  1039. */
  1040. ctlr->tcpcs++;
  1041. bp->flag |= Btcpck|Budpck;
  1042. }
  1043. bp->checksum = rd->checksum;
  1044. bp->flag |= Bpktck;
  1045. }
  1046. etheriq(edev, bp, 1);
  1047. }
  1048. else if(ctlr->rb[rdh] != nil){
  1049. freeb(ctlr->rb[rdh]);
  1050. ctlr->rb[rdh] = nil;
  1051. }
  1052. memset(rd, 0, sizeof(Rd));
  1053. coherence();
  1054. ctlr->rdfree--;
  1055. rdh = NEXT(rdh, ctlr->nrd);
  1056. }
  1057. ctlr->rdh = rdh;
  1058. if(ctlr->rdfree < ctlr->nrd/2 || (ctlr->rim & Rxdmt0))
  1059. igbereplenish(ctlr);
  1060. }
  1061. }
  1062. static void
  1063. igbeattach(Ether* edev)
  1064. {
  1065. Block *bp;
  1066. Ctlr *ctlr;
  1067. char name[KNAMELEN];
  1068. ctlr = edev->ctlr;
  1069. ctlr->edev = edev; /* point back to Ether* */
  1070. qlock(&ctlr->alock);
  1071. if(ctlr->alloc != nil){
  1072. qunlock(&ctlr->alock);
  1073. return;
  1074. }
  1075. ctlr->nrd = ROUND(Nrd, 8);
  1076. ctlr->ntd = ROUND(Ntd, 8);
  1077. ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 127);
  1078. if(ctlr->alloc == nil){
  1079. qunlock(&ctlr->alock);
  1080. return;
  1081. }
  1082. ctlr->rdba = (Rd*)ROUNDUP((uintptr)ctlr->alloc, 128);
  1083. ctlr->tdba = (Td*)(ctlr->rdba+ctlr->nrd);
  1084. ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
  1085. ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
  1086. if(waserror()){
  1087. while(ctlr->nrb > 0){
  1088. bp = igberballoc();
  1089. bp->free = nil;
  1090. freeb(bp);
  1091. ctlr->nrb--;
  1092. }
  1093. free(ctlr->tb);
  1094. ctlr->tb = nil;
  1095. free(ctlr->rb);
  1096. ctlr->rb = nil;
  1097. free(ctlr->alloc);
  1098. ctlr->alloc = nil;
  1099. qunlock(&ctlr->alock);
  1100. nexterror();
  1101. }
  1102. for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){
  1103. if((bp = allocb(Rbsz)) == nil)
  1104. break;
  1105. bp->free = igberbfree;
  1106. freeb(bp);
  1107. }
  1108. snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno);
  1109. kproc(name, igbelproc, edev);
  1110. snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno);
  1111. kproc(name, igberproc, edev);
  1112. igbetxinit(ctlr);
  1113. qunlock(&ctlr->alock);
  1114. poperror();
  1115. }
  1116. static void
  1117. igbeinterrupt(Ureg*, void* arg)
  1118. {
  1119. Ctlr *ctlr;
  1120. Ether *edev;
  1121. int icr, im, txdw;
  1122. edev = arg;
  1123. ctlr = edev->ctlr;
  1124. ilock(&ctlr->imlock);
  1125. csr32w(ctlr, Imc, ~0);
  1126. im = ctlr->im;
  1127. txdw = 0;
  1128. while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){
  1129. if(icr & Lsc){
  1130. im &= ~Lsc;
  1131. ctlr->lim = icr & Lsc;
  1132. wakeup(&ctlr->lrendez);
  1133. ctlr->lintr++;
  1134. }
  1135. if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq)){
  1136. im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq);
  1137. ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq);
  1138. wakeup(&ctlr->rrendez);
  1139. ctlr->rintr++;
  1140. }
  1141. if(icr & Txdw){
  1142. im &= ~Txdw;
  1143. txdw++;
  1144. ctlr->tintr++;
  1145. }
  1146. }
  1147. ctlr->im = im;
  1148. csr32w(ctlr, Ims, im);
  1149. iunlock(&ctlr->imlock);
  1150. if(txdw)
  1151. igbetransmit(edev);
  1152. }
  1153. static int
  1154. i82543mdior(Ctlr* ctlr, int n)
  1155. {
  1156. int ctrl, data, i, r;
  1157. /*
  1158. * Read n bits from the Management Data I/O Interface.
  1159. */
  1160. ctrl = csr32r(ctlr, Ctrl);
  1161. r = (ctrl & ~Mddo)|Mdco;
  1162. data = 0;
  1163. for(i = n-1; i >= 0; i--){
  1164. if(csr32r(ctlr, Ctrl) & Mdd)
  1165. data |= (1<<i);
  1166. csr32w(ctlr, Ctrl, Mdc|r);
  1167. csr32w(ctlr, Ctrl, r);
  1168. }
  1169. csr32w(ctlr, Ctrl, ctrl);
  1170. return data;
  1171. }
  1172. static int
  1173. i82543mdiow(Ctlr* ctlr, int bits, int n)
  1174. {
  1175. int ctrl, i, r;
  1176. /*
  1177. * Write n bits to the Management Data I/O Interface.
  1178. */
  1179. ctrl = csr32r(ctlr, Ctrl);
  1180. r = Mdco|Mddo|ctrl;
  1181. for(i = n-1; i >= 0; i--){
  1182. if(bits & (1<<i))
  1183. r |= Mdd;
  1184. else
  1185. r &= ~Mdd;
  1186. csr32w(ctlr, Ctrl, Mdc|r);
  1187. csr32w(ctlr, Ctrl, r);
  1188. }
  1189. csr32w(ctlr, Ctrl, ctrl);
  1190. return 0;
  1191. }
  1192. static int
  1193. i82543miimir(Mii* mii, int pa, int ra)
  1194. {
  1195. int data;
  1196. Ctlr *ctlr;
  1197. ctlr = mii->ctlr;
  1198. /*
  1199. * MII Management Interface Read.
  1200. *
  1201. * Preamble;
  1202. * ST+OP+PHYAD+REGAD;
  1203. * TA + 16 data bits.
  1204. */
  1205. i82543mdiow(ctlr, 0xFFFFFFFF, 32);
  1206. i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
  1207. data = i82543mdior(ctlr, 18);
  1208. if(data & 0x10000)
  1209. return -1;
  1210. return data & 0xFFFF;
  1211. }
  1212. static int
  1213. i82543miimiw(Mii* mii, int pa, int ra, int data)
  1214. {
  1215. Ctlr *ctlr;
  1216. ctlr = mii->ctlr;
  1217. /*
  1218. * MII Management Interface Write.
  1219. *
  1220. * Preamble;
  1221. * ST+OP+PHYAD+REGAD+TA + 16 data bits;
  1222. * Z.
  1223. */
  1224. i82543mdiow(ctlr, 0xFFFFFFFF, 32);
  1225. data &= 0xFFFF;
  1226. data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
  1227. i82543mdiow(ctlr, data, 32);
  1228. return 0;
  1229. }
  1230. static int
  1231. igbemiimir(Mii* mii, int pa, int ra)
  1232. {
  1233. Ctlr *ctlr;
  1234. int mdic, timo;
  1235. ctlr = mii->ctlr;
  1236. csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
  1237. mdic = 0;
  1238. for(timo = 64; timo; timo--){
  1239. mdic = csr32r(ctlr, Mdic);
  1240. if(mdic & (MDIe|MDIready))
  1241. break;
  1242. microdelay(1);
  1243. }
  1244. if((mdic & (MDIe|MDIready)) == MDIready)
  1245. return mdic & 0xFFFF;
  1246. return -1;
  1247. }
  1248. static int
  1249. igbemiimiw(Mii* mii, int pa, int ra, int data)
  1250. {
  1251. Ctlr *ctlr;
  1252. int mdic, timo;
  1253. ctlr = mii->ctlr;
  1254. data &= MDIdMASK;
  1255. csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
  1256. mdic = 0;
  1257. for(timo = 64; timo; timo--){
  1258. mdic = csr32r(ctlr, Mdic);
  1259. if(mdic & (MDIe|MDIready))
  1260. break;
  1261. microdelay(1);
  1262. }
  1263. if((mdic & (MDIe|MDIready)) == MDIready)
  1264. return 0;
  1265. return -1;
  1266. }
  1267. static int
  1268. igbemii(Ctlr* ctlr)
  1269. {
  1270. MiiPhy *phy;
  1271. int ctrl, p, r;
  1272. r = csr32r(ctlr, Status);
  1273. if(r & Tbimode)
  1274. return -1;
  1275. if((ctlr->mii = malloc(sizeof(Mii))) == nil)
  1276. return -1;
  1277. ctlr->mii->ctlr = ctlr;
  1278. ctrl = csr32r(ctlr, Ctrl);
  1279. ctrl |= Slu;
  1280. switch(ctlr->id){
  1281. case i82543gc:
  1282. ctrl |= Frcdplx|Frcspd;
  1283. csr32w(ctlr, Ctrl, ctrl);
  1284. /*
  1285. * The reset pin direction (Mdro) should already
  1286. * be set from the EEPROM load.
  1287. * If it's not set this configuration is unexpected
  1288. * so bail.
  1289. */
  1290. r = csr32r(ctlr, Ctrlext);
  1291. if(!(r & Mdro))
  1292. return -1;
  1293. csr32w(ctlr, Ctrlext, r);
  1294. delay(20);
  1295. r = csr32r(ctlr, Ctrlext);
  1296. r &= ~Mdr;
  1297. csr32w(ctlr, Ctrlext, r);
  1298. delay(20);
  1299. r = csr32r(ctlr, Ctrlext);
  1300. r |= Mdr;
  1301. csr32w(ctlr, Ctrlext, r);
  1302. delay(20);
  1303. ctlr->mii->mir = i82543miimir;
  1304. ctlr->mii->miw = i82543miimiw;
  1305. break;
  1306. case i82544ei:
  1307. case i82547ei:
  1308. case i82540em:
  1309. case i82540eplp:
  1310. case i82547gi:
  1311. case i82541gi:
  1312. case i82541gi2:
  1313. case i82541pi:
  1314. case i82545gmc:
  1315. case i82546gb:
  1316. case i82546eb:
  1317. ctrl &= ~(Frcdplx|Frcspd);
  1318. csr32w(ctlr, Ctrl, ctrl);
  1319. ctlr->mii->mir = igbemiimir;
  1320. ctlr->mii->miw = igbemiimiw;
  1321. break;
  1322. default:
  1323. free(ctlr->mii);
  1324. ctlr->mii = nil;
  1325. return -1;
  1326. }
  1327. if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
  1328. free(ctlr->mii);
  1329. ctlr->mii = nil;
  1330. return -1;
  1331. }
  1332. USED(phy);
  1333. // print("oui %X phyno %d\n", phy->oui, phy->phyno);
  1334. /*
  1335. * 8254X-specific PHY registers not in 802.3:
  1336. * 0x10 PHY specific control
  1337. * 0x14 extended PHY specific control
  1338. * Set appropriate values then reset the PHY to have
  1339. * changes noted.
  1340. */
  1341. switch(ctlr->id){
  1342. case i82547gi:
  1343. case i82541gi:
  1344. case i82541gi2:
  1345. case i82541pi:
  1346. case i82545gmc:
  1347. case i82546gb:
  1348. case i82546eb:
  1349. break;
  1350. default:
  1351. r = miimir(ctlr->mii, 16);
  1352. r |= 0x0800; /* assert CRS on Tx */
  1353. r |= 0x0060; /* auto-crossover all speeds */
  1354. r |= 0x0002; /* polarity reversal enabled */
  1355. miimiw(ctlr->mii, 16, r);
  1356. r = miimir(ctlr->mii, 20);
  1357. r |= 0x0070; /* +25MHz clock */
  1358. r &= ~0x0F00;
  1359. r |= 0x0100; /* 1x downshift */
  1360. miimiw(ctlr->mii, 20, r);
  1361. miireset(ctlr->mii);
  1362. p = 0;
  1363. if(ctlr->txcw & TxcwPs)
  1364. p |= AnaP;
  1365. if(ctlr->txcw & TxcwAs)
  1366. p |= AnaAP;
  1367. miiane(ctlr->mii, ~0, p, ~0);
  1368. break;
  1369. }
  1370. return 0;
  1371. }
  1372. static int
  1373. at93c46io(Ctlr* ctlr, char* op, int data)
  1374. {
  1375. char *lp, *p;
  1376. int i, loop, eecd, r;
  1377. eecd = csr32r(ctlr, Eecd);
  1378. r = 0;
  1379. loop = -1;
  1380. lp = nil;
  1381. for(p = op; *p != '\0'; p++){
  1382. switch(*p){
  1383. default:
  1384. return -1;
  1385. case ' ':
  1386. continue;
  1387. case ':': /* start of loop */
  1388. loop = strtol(p+1, &lp, 0)-1;
  1389. lp--;
  1390. if(p == lp)
  1391. loop = 7;
  1392. p = lp;
  1393. continue;
  1394. case ';': /* end of loop */
  1395. if(lp == nil)
  1396. return -1;
  1397. loop--;
  1398. if(loop >= 0)
  1399. p = lp;
  1400. else
  1401. lp = nil;
  1402. continue;
  1403. case 'C': /* assert clock */
  1404. eecd |= Sk;
  1405. break;
  1406. case 'c': /* deassert clock */
  1407. eecd &= ~Sk;
  1408. break;
  1409. case 'D': /* next bit in 'data' byte */
  1410. if(loop < 0)
  1411. return -1;
  1412. if(data & (1<<loop))
  1413. eecd |= Di;
  1414. else
  1415. eecd &= ~Di;
  1416. break;
  1417. case 'O': /* collect data output */
  1418. i = (csr32r(ctlr, Eecd) & Do) != 0;
  1419. if(loop >= 0)
  1420. r |= (i<<loop);
  1421. else
  1422. r = i;
  1423. continue;
  1424. case 'I': /* assert data input */
  1425. eecd |= Di;
  1426. break;
  1427. case 'i': /* deassert data input */
  1428. eecd &= ~Di;
  1429. break;
  1430. case 'S': /* enable chip select */
  1431. eecd |= Cs;
  1432. break;
  1433. case 's': /* disable chip select */
  1434. eecd &= ~Cs;
  1435. break;
  1436. }
  1437. csr32w(ctlr, Eecd, eecd);
  1438. microdelay(50);
  1439. }
  1440. if(loop >= 0)
  1441. return -1;
  1442. return r;
  1443. }
  1444. static int
  1445. at93c46r(Ctlr* ctlr)
  1446. {
  1447. ushort sum;
  1448. char rop[20];
  1449. int addr, areq, bits, data, eecd, i;
  1450. eecd = csr32r(ctlr, Eecd);
  1451. if(eecd & Spi){
  1452. print("igbe: SPI EEPROM access not implemented\n");
  1453. return 0;
  1454. }
  1455. if(eecd & (Eeszaddr|Eesz256))
  1456. bits = 8;
  1457. else
  1458. bits = 6;
  1459. sum = 0;
  1460. switch(ctlr->id){
  1461. default:
  1462. areq = 0;
  1463. break;
  1464. case i82541gi:
  1465. case i82547gi:
  1466. case i82540em:
  1467. case i82540eplp:
  1468. case i82541pi:
  1469. case i82541gi2:
  1470. case i82545gmc:
  1471. case i82546gb:
  1472. case i82546eb:
  1473. areq = 1;
  1474. csr32w(ctlr, Eecd, eecd|Areq);
  1475. for(i = 0; i < 1000; i++){
  1476. if((eecd = csr32r(ctlr, Eecd)) & Agnt)
  1477. break;
  1478. microdelay(5);
  1479. }
  1480. if(!(eecd & Agnt)){
  1481. print("igbe: not granted EEPROM access\n");
  1482. goto release;
  1483. }
  1484. break;
  1485. }
  1486. snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
  1487. for(addr = 0; addr < 0x40; addr++){
  1488. /*
  1489. * Read a word at address 'addr' from the Atmel AT93C46
  1490. * 3-Wire Serial EEPROM or compatible. The EEPROM access is
  1491. * controlled by 4 bits in Eecd. See the AT93C46 datasheet
  1492. * for protocol details.
  1493. */
  1494. if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
  1495. print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
  1496. goto release;
  1497. }
  1498. data = at93c46io(ctlr, ":16COc;", 0);
  1499. at93c46io(ctlr, "sic", 0);
  1500. ctlr->eeprom[addr] = data;
  1501. sum += data;
  1502. }
  1503. release:
  1504. if(areq)
  1505. csr32w(ctlr, Eecd, eecd & ~Areq);
  1506. return sum;
  1507. }
  1508. static int
  1509. igbedetach(Ctlr* ctlr)
  1510. {
  1511. int r, timeo;
  1512. /*
  1513. * Perform a device reset to get the chip back to the
  1514. * power-on state, followed by an EEPROM reset to read
  1515. * the defaults for some internal registers.
  1516. */
  1517. csr32w(ctlr, Imc, ~0);
  1518. csr32w(ctlr, Rctl, 0);
  1519. csr32w(ctlr, Tctl, 0);
  1520. delay(10);
  1521. csr32w(ctlr, Ctrl, Devrst);
  1522. delay(1);
  1523. for(timeo = 0; timeo < 1000; timeo++){
  1524. if(!(csr32r(ctlr, Ctrl) & Devrst))
  1525. break;
  1526. delay(1);
  1527. }
  1528. if(csr32r(ctlr, Ctrl) & Devrst)
  1529. return -1;
  1530. r = csr32r(ctlr, Ctrlext);
  1531. csr32w(ctlr, Ctrlext, r|Eerst);
  1532. delay(1);
  1533. for(timeo = 0; timeo < 1000; timeo++){
  1534. if(!(csr32r(ctlr, Ctrlext) & Eerst))
  1535. break;
  1536. delay(1);
  1537. }
  1538. if(csr32r(ctlr, Ctrlext) & Eerst)
  1539. return -1;
  1540. switch(ctlr->id){
  1541. default:
  1542. break;
  1543. case i82540em:
  1544. case i82540eplp:
  1545. case i82541gi:
  1546. case i82541pi:
  1547. case i82547gi:
  1548. case i82541gi2:
  1549. case i82545gmc:
  1550. case i82546gb:
  1551. case i82546eb:
  1552. r = csr32r(ctlr, Manc);
  1553. r &= ~Arpen;
  1554. csr32w(ctlr, Manc, r);
  1555. break;
  1556. }
  1557. csr32w(ctlr, Imc, ~0);
  1558. delay(1);
  1559. for(timeo = 0; timeo < 1000; timeo++){
  1560. if(!csr32r(ctlr, Icr))
  1561. break;
  1562. delay(1);
  1563. }
  1564. if(csr32r(ctlr, Icr))
  1565. return -1;
  1566. return 0;
  1567. }
  1568. static void
  1569. igbeshutdown(Ether* ether)
  1570. {
  1571. igbedetach(ether->ctlr);
  1572. }
  1573. static int
  1574. igbereset(Ctlr* ctlr)
  1575. {
  1576. int ctrl, i, pause, r, swdpio, txcw;
  1577. if(igbedetach(ctlr))
  1578. return -1;
  1579. /*
  1580. * Read the EEPROM, validate the checksum
  1581. * then get the device back to a power-on state.
  1582. */
  1583. if((r = at93c46r(ctlr)) != 0xBABA){
  1584. print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
  1585. return -1;
  1586. }
  1587. /*
  1588. * Snarf and set up the receive addresses.
  1589. * There are 16 addresses. The first should be the MAC address.
  1590. * The others are cleared and not marked valid (MS bit of Rah).
  1591. */
  1592. if ((ctlr->id == i82546gb || ctlr->id == i82546eb) &&
  1593. BUSFNO(ctlr->pcidev->tbdf) == 1)
  1594. ctlr->eeprom[Ea+2] += 0x100; /* second interface */
  1595. for(i = Ea; i < Eaddrlen/2; i++){
  1596. if(i == Ea && ctlr->id == i82541gi && ctlr->eeprom[i] == 0xFFFF)
  1597. ctlr->eeprom[i] = 0xD000;
  1598. ctlr->ra[2*i] = ctlr->eeprom[i];
  1599. ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
  1600. }
  1601. r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
  1602. csr32w(ctlr, Ral, r);
  1603. r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
  1604. csr32w(ctlr, Rah, r);
  1605. for(i = 1; i < 16; i++){
  1606. csr32w(ctlr, Ral+i*8, 0);
  1607. csr32w(ctlr, Rah+i*8, 0);
  1608. }
  1609. /*
  1610. * Clear the Multicast Table Array.
  1611. * It's a 4096 bit vector accessed as 128 32-bit registers.
  1612. */
  1613. memset(ctlr->mta, 0, sizeof(ctlr->mta));
  1614. for(i = 0; i < 128; i++)
  1615. csr32w(ctlr, Mta+i*4, 0);
  1616. /*
  1617. * Just in case the Eerst didn't load the defaults
  1618. * (doesn't appear to fully on the 82543GC), do it manually.
  1619. */
  1620. if (ctlr->id == i82543gc) {
  1621. txcw = csr32r(ctlr, Txcw);
  1622. txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
  1623. ctrl = csr32r(ctlr, Ctrl);
  1624. ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
  1625. if(ctlr->eeprom[Icw1] & 0x0400){
  1626. ctrl |= Fd;
  1627. txcw |= TxcwFd;
  1628. }
  1629. if(ctlr->eeprom[Icw1] & 0x0200)
  1630. ctrl |= Lrst;
  1631. if(ctlr->eeprom[Icw1] & 0x0010)
  1632. ctrl |= Ilos;
  1633. if(ctlr->eeprom[Icw1] & 0x0800)
  1634. ctrl |= Frcspd;
  1635. swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
  1636. ctrl |= swdpio<<SwdpioloSHIFT;
  1637. csr32w(ctlr, Ctrl, ctrl);
  1638. ctrl = csr32r(ctlr, Ctrlext);
  1639. ctrl &= ~(Ips|SwdpiohiMASK);
  1640. swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
  1641. if(ctlr->eeprom[Icw1] & 0x1000)
  1642. ctrl |= Ips;
  1643. ctrl |= swdpio<<SwdpiohiSHIFT;
  1644. csr32w(ctlr, Ctrlext, ctrl);
  1645. if(ctlr->eeprom[Icw2] & 0x0800)
  1646. txcw |= TxcwAne;
  1647. pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
  1648. txcw |= pause<<TxcwPauseSHIFT;
  1649. switch(pause){
  1650. default:
  1651. ctlr->fcrtl = 0x00002000;
  1652. ctlr->fcrth = 0x00004000;
  1653. txcw |= TxcwAs|TxcwPs;
  1654. break;
  1655. case 0:
  1656. ctlr->fcrtl = 0x00002000;
  1657. ctlr->fcrth = 0x00004000;
  1658. break;
  1659. case 2:
  1660. ctlr->fcrtl = 0;
  1661. ctlr->fcrth = 0;
  1662. txcw |= TxcwAs;
  1663. break;
  1664. }
  1665. ctlr->txcw = txcw;
  1666. csr32w(ctlr, Txcw, txcw);
  1667. }
  1668. /*
  1669. * Flow control - values from the datasheet.
  1670. */
  1671. csr32w(ctlr, Fcal, 0x00C28001);
  1672. csr32w(ctlr, Fcah, 0x00000100);
  1673. csr32w(ctlr, Fct, 0x00008808);
  1674. csr32w(ctlr, Fcttv, 0x00000100);
  1675. csr32w(ctlr, Fcrtl, ctlr->fcrtl);
  1676. csr32w(ctlr, Fcrth, ctlr->fcrth);
  1677. if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0)
  1678. return -1;
  1679. return 0;
  1680. }
  1681. static void
  1682. igbepci(void)
  1683. {
  1684. int cls;
  1685. Pcidev *p;
  1686. Ctlr *ctlr;
  1687. void *mem;
  1688. p = nil;
  1689. while(p = pcimatch(p, 0, 0)){
  1690. if(p->ccrb != 0x02 || p->ccru != 0)
  1691. continue;
  1692. switch((p->did<<16)|p->vid){
  1693. default:
  1694. continue;
  1695. case i82543gc:
  1696. case i82544ei:
  1697. case i82547ei:
  1698. case i82540em:
  1699. case i82540eplp:
  1700. case i82541gi:
  1701. case i82547gi:
  1702. case i82541gi2:
  1703. case i82541pi:
  1704. case i82545gmc:
  1705. case i82546gb:
  1706. case i82546eb:
  1707. break;
  1708. }
  1709. mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
  1710. if(mem == nil){
  1711. print("igbe: can't map %8.8luX\n", p->mem[0].bar);
  1712. continue;
  1713. }
  1714. cls = pcicfgr8(p, PciCLS);
  1715. switch(cls){
  1716. default:
  1717. print("igbe: unexpected CLS - %d\n", cls*4);
  1718. break;
  1719. case 0x00:
  1720. case 0xFF:
  1721. print("igbe: unusable CLS\n");
  1722. continue;
  1723. case 0x08:
  1724. case 0x10:
  1725. break;
  1726. }
  1727. ctlr = malloc(sizeof(Ctlr));
  1728. ctlr->port = p->mem[0].bar & ~0x0F;
  1729. ctlr->pcidev = p;
  1730. ctlr->id = (p->did<<16)|p->vid;
  1731. ctlr->cls = cls*4;
  1732. ctlr->nic = mem;
  1733. if(igbereset(ctlr)){
  1734. free(ctlr);
  1735. vunmap(mem, p->mem[0].size);
  1736. continue;
  1737. }
  1738. pcisetbme(p);
  1739. if(igbectlrhead != nil)
  1740. igbectlrtail->next = ctlr;
  1741. else
  1742. igbectlrhead = ctlr;
  1743. igbectlrtail = ctlr;
  1744. }
  1745. }
  1746. static int
  1747. igbepnp(Ether* edev)
  1748. {
  1749. Ctlr *ctlr;
  1750. if(igbectlrhead == nil)
  1751. igbepci();
  1752. /*
  1753. * Any adapter matches if no edev->port is supplied,
  1754. * otherwise the ports must match.
  1755. */
  1756. for(ctlr = igbectlrhead; ctlr != nil; ctlr = ctlr->next){
  1757. if(ctlr->active)
  1758. continue;
  1759. if(edev->port == 0 || edev->port == ctlr->port){
  1760. ctlr->active = 1;
  1761. break;
  1762. }
  1763. }
  1764. if(ctlr == nil)
  1765. return -1;
  1766. edev->ctlr = ctlr;
  1767. edev->port = ctlr->port;
  1768. edev->irq = ctlr->pcidev->intl;
  1769. edev->tbdf = ctlr->pcidev->tbdf;
  1770. edev->mbps = 1000;
  1771. memmove(edev->ea, ctlr->ra, Eaddrlen);
  1772. /*
  1773. * Linkage to the generic ethernet driver.
  1774. */
  1775. edev->attach = igbeattach;
  1776. edev->transmit = igbetransmit;
  1777. edev->interrupt = igbeinterrupt;
  1778. edev->ifstat = igbeifstat;
  1779. edev->ctl = igbectl;
  1780. edev->arg = edev;
  1781. edev->promiscuous = igbepromiscuous;
  1782. edev->shutdown = igbeshutdown;
  1783. edev->multicast = igbemulticast;
  1784. return 0;
  1785. }
  1786. void
  1787. etherigbelink(void)
  1788. {
  1789. addethercard("i82543", igbepnp);
  1790. addethercard("igbe", igbepnp);
  1791. }