l.s 29 KB

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  1. #include "mem.h"
  2. #include "/sys/src/boot/pc/x16.h"
  3. #undef DELAY
  4. #define PADDR(a) ((a) & ~KZERO)
  5. #define KADDR(a) (KZERO|(a))
  6. /*
  7. * Some machine instructions not handled by 8[al].
  8. */
  9. #define OP16 BYTE $0x66
  10. #define DELAY BYTE $0xEB; BYTE $0x00 /* JMP .+2 */
  11. #define CPUID BYTE $0x0F; BYTE $0xA2 /* CPUID, argument in AX */
  12. #define WRMSR BYTE $0x0F; BYTE $0x30 /* WRMSR, argument in AX/DX (lo/hi) */
  13. #define RDTSC BYTE $0x0F; BYTE $0x31 /* RDTSC, result in AX/DX (lo/hi) */
  14. #define RDMSR BYTE $0x0F; BYTE $0x32 /* RDMSR, result in AX/DX (lo/hi) */
  15. #define HLT BYTE $0xF4
  16. #define INVLPG BYTE $0x0F; BYTE $0x01; BYTE $0x39 /* INVLPG (%ecx) */
  17. /*
  18. * Macros for calculating offsets within the page directory base
  19. * and page tables. Note that these are assembler-specific hence
  20. * the '<<2'.
  21. */
  22. #define PDO(a) (((((a))>>22) & 0x03FF)<<2)
  23. #define PTO(a) (((((a))>>12) & 0x03FF)<<2)
  24. /*
  25. * For backwards compatiblity with 9load - should go away when 9load is changed
  26. * 9load currently sets up the mmu, however the first 16MB of memory is identity
  27. * mapped, so behave as if the mmu was not setup
  28. */
  29. TEXT _startKADDR(SB), $0
  30. MOVL $_startPADDR(SB), AX
  31. ANDL $~KZERO, AX
  32. JMP* AX
  33. /*
  34. * Must be 4-byte aligned.
  35. */
  36. TEXT _multibootheader(SB), $0
  37. LONG $0x1BADB002 /* magic */
  38. LONG $0x00010003 /* flags */
  39. LONG $-(0x1BADB002 + 0x00010003) /* checksum */
  40. LONG $_multibootheader-KZERO(SB) /* header_addr */
  41. LONG $_startKADDR-KZERO(SB) /* load_addr */
  42. LONG $edata-KZERO(SB) /* load_end_addr */
  43. LONG $end-KZERO(SB) /* bss_end_addr */
  44. LONG $_startKADDR-KZERO(SB) /* entry_addr */
  45. LONG $0 /* mode_type */
  46. LONG $0 /* width */
  47. LONG $0 /* height */
  48. LONG $0 /* depth */
  49. /*
  50. * In protected mode with paging turned off and segment registers setup to linear map all memory.
  51. * Entered via a jump to PADDR(entry), the physical address of the virtual kernel entry point of KADDR(entry)
  52. * Make the basic page tables for processor 0. Four pages are needed for the basic set:
  53. * a page directory, a page table for mapping the first 4MB of physical memory to KZERO,
  54. * and virtual and physical pages for mapping the Mach structure.
  55. * The remaining PTEs will be allocated later when memory is sized.
  56. * An identity mmu map is also needed for the switch to virtual mode. This
  57. * identity mapping is removed once the MMU is going and the JMP has been made
  58. * to virtual memory.
  59. */
  60. TEXT _startPADDR(SB), $0
  61. CLI /* make sure interrupts are off */
  62. /* set up the gdt so we have sane plan 9 style gdts. */
  63. MOVL $tgdtptr(SB), AX
  64. ANDL $~KZERO, AX
  65. MOVL (AX), GDTR
  66. MOVW $1, AX
  67. MOVW AX, MSW
  68. /* clear prefetch queue (weird code to avoid optimizations) */
  69. DELAY
  70. /* set segs to something sane (avoid traps later) */
  71. MOVW $(1<<3), AX
  72. MOVW AX, DS
  73. MOVW AX, SS
  74. MOVW AX, ES
  75. MOVW AX, FS
  76. MOVW AX, GS
  77. /* JMP $(2<<3):$mode32bit(SB) /**/
  78. BYTE $0xEA
  79. LONG $mode32bit-KZERO(SB)
  80. WORD $(2<<3)
  81. /*
  82. * gdt to get us to 32-bit/segmented/unpaged mode
  83. */
  84. TEXT tgdt(SB), $0
  85. /* null descriptor */
  86. LONG $0
  87. LONG $0
  88. /* data segment descriptor for 4 gigabytes (PL 0) */
  89. LONG $(0xFFFF)
  90. LONG $(SEGG|SEGB|(0xF<<16)|SEGP|SEGPL(0)|SEGDATA|SEGW)
  91. /* exec segment descriptor for 4 gigabytes (PL 0) */
  92. LONG $(0xFFFF)
  93. LONG $(SEGG|SEGD|(0xF<<16)|SEGP|SEGPL(0)|SEGEXEC|SEGR)
  94. /*
  95. * pointer to initial gdt
  96. * Note the -KZERO which puts the physical address in the gdtptr.
  97. * that's needed as we start executing in physical addresses.
  98. */
  99. TEXT tgdtptr(SB), $0
  100. WORD $(3*8)
  101. LONG $tgdt-KZERO(SB)
  102. TEXT m0rgdtptr(SB), $0
  103. WORD $(NGDT*8-1)
  104. LONG $(CPU0GDT-KZERO)
  105. TEXT m0gdtptr(SB), $0
  106. WORD $(NGDT*8-1)
  107. LONG $CPU0GDT
  108. TEXT m0idtptr(SB), $0
  109. WORD $(256*8-1)
  110. LONG $IDTADDR
  111. TEXT mode32bit(SB), $0
  112. /* At this point, the GDT setup is done. */
  113. MOVL $PADDR(CPU0PDB), DI /* clear 4 pages for the tables etc. */
  114. XORL AX, AX
  115. MOVL $(4*BY2PG), CX
  116. SHRL $2, CX
  117. CLD
  118. REP; STOSL
  119. MOVL $PADDR(CPU0PDB), AX
  120. ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
  121. MOVL $PADDR(CPU0PTE), (AX) /* PTE's for KZERO */
  122. MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
  123. ORL BX, (AX)
  124. MOVL $PADDR(CPU0PTE), AX /* first page of page table */
  125. MOVL $1024, CX /* 1024 pages in 4MB */
  126. _setpte:
  127. MOVL BX, (AX)
  128. ADDL $(1<<PGSHIFT), BX
  129. ADDL $4, AX
  130. LOOP _setpte
  131. MOVL $PADDR(CPU0PTE), AX
  132. ADDL $PTO(MACHADDR), AX /* page table entry offset for MACHADDR */
  133. MOVL $PADDR(CPU0MACH), (AX) /* PTE for Mach */
  134. MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
  135. ORL BX, (AX)
  136. /*
  137. * Now ready to use the new map. Make sure the processor options are what is wanted.
  138. * It is necessary on some processors to immediately follow mode switching with a JMP instruction
  139. * to clear the prefetch queues.
  140. */
  141. MOVL $PADDR(CPU0PDB), CX /* load address of page directory */
  142. MOVL (PDO(KZERO))(CX), DX /* double-map KZERO at 0 */
  143. MOVL DX, (PDO(0))(CX)
  144. MOVL CX, CR3
  145. DELAY /* JMP .+2 */
  146. MOVL CR0, DX
  147. ORL $0x80010000, DX /* PG|WP */
  148. ANDL $~0x6000000A, DX /* ~(CD|NW|TS|MP) */
  149. MOVL $_startpg(SB), AX /* this is a virtual address */
  150. MOVL DX, CR0 /* turn on paging */
  151. JMP* AX /* jump to the virtual nirvana */
  152. /*
  153. * Basic machine environment set, can clear BSS and create a stack.
  154. * The stack starts at the top of the page containing the Mach structure.
  155. * The x86 architecture forces the use of the same virtual address for
  156. * each processor's Mach structure, so the global Mach pointer 'm' can
  157. * be initialised here.
  158. */
  159. TEXT _startpg(SB), $0
  160. MOVL $0, (PDO(0))(CX) /* undo double-map of KZERO at 0 */
  161. MOVL CX, CR3 /* load and flush the mmu */
  162. _clearbss:
  163. MOVL $edata(SB), DI
  164. XORL AX, AX
  165. MOVL $end(SB), CX
  166. SUBL DI, CX /* end-edata bytes */
  167. SHRL $2, CX /* end-edata doublewords */
  168. CLD
  169. REP; STOSL /* clear BSS */
  170. MOVL $MACHADDR, SP
  171. MOVL SP, m(SB) /* initialise global Mach pointer */
  172. MOVL $0, 0(SP) /* initialise m->machno */
  173. ADDL $(MACHSIZE-4), SP /* initialise stack */
  174. /*
  175. * Need to do one final thing to ensure a clean machine environment,
  176. * clear the EFLAGS register, which can only be done once there is a stack.
  177. */
  178. MOVL $0, AX
  179. PUSHL AX
  180. POPFL
  181. CALL main(SB)
  182. /*
  183. * Park a processor. Should never fall through a return from main to here,
  184. * should only be called by application processors when shutting down.
  185. */
  186. TEXT idle(SB), $0
  187. _idle:
  188. STI
  189. HLT
  190. JMP _idle
  191. /*
  192. * Save registers.
  193. */
  194. TEXT saveregs(SB), $0
  195. /* appease 8l */
  196. SUBL $32, SP
  197. POPL AX
  198. POPL AX
  199. POPL AX
  200. POPL AX
  201. POPL AX
  202. POPL AX
  203. POPL AX
  204. POPL AX
  205. PUSHL AX
  206. PUSHL BX
  207. PUSHL CX
  208. PUSHL DX
  209. PUSHL BP
  210. PUSHL DI
  211. PUSHL SI
  212. PUSHFL
  213. XCHGL 32(SP), AX /* swap return PC and saved flags */
  214. XCHGL 0(SP), AX
  215. XCHGL 32(SP), AX
  216. RET
  217. TEXT restoreregs(SB), $0
  218. /* appease 8l */
  219. PUSHL AX
  220. PUSHL AX
  221. PUSHL AX
  222. PUSHL AX
  223. PUSHL AX
  224. PUSHL AX
  225. PUSHL AX
  226. PUSHL AX
  227. ADDL $32, SP
  228. XCHGL 32(SP), AX /* swap return PC and saved flags */
  229. XCHGL 0(SP), AX
  230. XCHGL 32(SP), AX
  231. POPFL
  232. POPL SI
  233. POPL DI
  234. POPL BP
  235. POPL DX
  236. POPL CX
  237. POPL BX
  238. POPL AX
  239. RET
  240. /*
  241. * Assumed to be in protected mode at time of call.
  242. * Switch to real mode, execute an interrupt, and
  243. * then switch back to protected mode.
  244. *
  245. * Assumes:
  246. *
  247. * - no device interrupts are going to come in
  248. * - 0-16MB is identity mapped in page tables
  249. * - realmode() has copied us down from 0x100000 to 0x8000
  250. * - can use code segment 0x0800 in real mode
  251. * to get at l.s code
  252. * - l.s code is less than 1 page
  253. */
  254. #define RELOC (RMCODE-KTZERO)
  255. TEXT realmodeidtptr(SB), $0
  256. WORD $(4*256-1)
  257. LONG $0
  258. TEXT realmode0(SB), $0
  259. CALL saveregs(SB)
  260. /* switch to low code address */
  261. LEAL physcode-KZERO(SB), AX
  262. JMP *AX
  263. TEXT physcode(SB), $0
  264. /* switch to low stack */
  265. MOVL SP, AX
  266. MOVL $0x7C00, SP
  267. PUSHL AX
  268. /* change gdt to physical pointer */
  269. MOVL m0rgdtptr-KZERO(SB), GDTR
  270. /* load IDT with real-mode version*/
  271. MOVL realmodeidtptr-KZERO(SB), IDTR
  272. /* edit INT $0x00 instruction below */
  273. MOVL $(RMUADDR-KZERO+48), AX /* &rmu.trap */
  274. MOVL (AX), AX
  275. MOVB AX, realmodeintrinst+(-KZERO+1+RELOC)(SB)
  276. /* disable paging */
  277. MOVL CR0, AX
  278. ANDL $0x7FFFFFFF, AX
  279. MOVL AX, CR0
  280. /* JMP .+2 to clear prefetch queue*/
  281. BYTE $0xEB; BYTE $0x00
  282. /* jump to 16-bit code segment */
  283. /* JMPFAR SELECTOR(KESEG16, SELGDT, 0):$again16bit(SB) /**/
  284. BYTE $0xEA
  285. LONG $again16bit-KZERO(SB)
  286. WORD $SELECTOR(KESEG16, SELGDT, 0)
  287. TEXT again16bit(SB), $0
  288. /*
  289. * Now in 16-bit compatibility mode.
  290. * These are 32-bit instructions being interpreted
  291. * as 16-bit instructions. I'm being lazy and
  292. * not using the macros because I know when
  293. * the 16- and 32-bit instructions look the same
  294. * or close enough.
  295. */
  296. /* disable protected mode and jump to real mode cs */
  297. OPSIZE; MOVL CR0, AX
  298. OPSIZE; XORL BX, BX
  299. OPSIZE; INCL BX
  300. OPSIZE; XORL BX, AX
  301. OPSIZE; MOVL AX, CR0
  302. /* JMPFAR 0x0800:now16real */
  303. BYTE $0xEA
  304. WORD $now16real-KZERO(SB)
  305. WORD $0x0800
  306. TEXT now16real(SB), $0
  307. /* copy the registers for the bios call */
  308. LWI(0x0000, rAX)
  309. MOVW AX,SS
  310. LWI(RMUADDR, rBP)
  311. /* offsets are in Ureg */
  312. LXW(44, xBP, rAX)
  313. MOVW AX, DS
  314. LXW(40, xBP, rAX)
  315. MOVW AX, ES
  316. OPSIZE; LXW(0, xBP, rDI)
  317. OPSIZE; LXW(4, xBP, rSI)
  318. OPSIZE; LXW(16, xBP, rBX)
  319. OPSIZE; LXW(20, xBP, rDX)
  320. OPSIZE; LXW(24, xBP, rCX)
  321. OPSIZE; LXW(28, xBP, rAX)
  322. CLC
  323. TEXT realmodeintrinst(SB), $0
  324. INT $0x00
  325. /* save the registers after the call */
  326. LWI(0x7bfc, rSP)
  327. OPSIZE; PUSHFL
  328. OPSIZE; PUSHL AX
  329. LWI(0, rAX)
  330. MOVW AX,SS
  331. LWI(RMUADDR, rBP)
  332. OPSIZE; SXW(rDI, 0, xBP)
  333. OPSIZE; SXW(rSI, 4, xBP)
  334. OPSIZE; SXW(rBX, 16, xBP)
  335. OPSIZE; SXW(rDX, 20, xBP)
  336. OPSIZE; SXW(rCX, 24, xBP)
  337. OPSIZE; POPL AX
  338. OPSIZE; SXW(rAX, 28, xBP)
  339. MOVW DS, AX
  340. OPSIZE; SXW(rAX, 44, xBP)
  341. MOVW ES, AX
  342. OPSIZE; SXW(rAX, 40, xBP)
  343. OPSIZE; POPL AX
  344. OPSIZE; SXW(rAX, 64, xBP) /* flags */
  345. /* re-enter protected mode and jump to 32-bit code */
  346. OPSIZE; MOVL $1, AX
  347. OPSIZE; MOVL AX, CR0
  348. /* JMPFAR SELECTOR(KESEG, SELGDT, 0):$again32bit(SB) /**/
  349. OPSIZE
  350. BYTE $0xEA
  351. LONG $again32bit-KZERO(SB)
  352. WORD $SELECTOR(KESEG, SELGDT, 0)
  353. TEXT again32bit(SB), $0
  354. MOVW $SELECTOR(KDSEG, SELGDT, 0),AX
  355. MOVW AX,DS
  356. MOVW AX,SS
  357. MOVW AX,ES
  358. MOVW AX,FS
  359. MOVW AX,GS
  360. /* enable paging and jump to kzero-address code */
  361. MOVL CR0, AX
  362. ORL $0x80010000, AX /* PG|WP */
  363. MOVL AX, CR0
  364. LEAL again32kzero(SB), AX
  365. JMP* AX
  366. TEXT again32kzero(SB), $0
  367. /* breathe a sigh of relief - back in 32-bit protected mode */
  368. /* switch to old stack */
  369. PUSHL AX /* match popl below for 8l */
  370. MOVL $0x7BFC, SP
  371. POPL SP
  372. /* restore idt */
  373. MOVL m0idtptr(SB),IDTR
  374. /* restore gdt */
  375. MOVL m0gdtptr(SB), GDTR
  376. CALL restoreregs(SB)
  377. RET
  378. /*
  379. * BIOS32.
  380. */
  381. TEXT bios32call(SB), $0
  382. MOVL ci+0(FP), BP
  383. MOVL 0(BP), AX
  384. MOVL 4(BP), BX
  385. MOVL 8(BP), CX
  386. MOVL 12(BP), DX
  387. MOVL 16(BP), SI
  388. MOVL 20(BP), DI
  389. PUSHL BP
  390. MOVL 12(SP), BP /* ptr */
  391. BYTE $0xFF; BYTE $0x5D; BYTE $0x00 /* CALL FAR 0(BP) */
  392. POPL BP
  393. MOVL DI, 20(BP)
  394. MOVL SI, 16(BP)
  395. MOVL DX, 12(BP)
  396. MOVL CX, 8(BP)
  397. MOVL BX, 4(BP)
  398. MOVL AX, 0(BP)
  399. XORL AX, AX
  400. JCC _bios32xxret
  401. INCL AX
  402. _bios32xxret:
  403. RET
  404. /*
  405. * Port I/O.
  406. * in[bsl] input a byte|short|long
  407. * ins[bsl] input a string of bytes|shorts|longs
  408. * out[bsl] output a byte|short|long
  409. * outs[bsl] output a string of bytes|shorts|longs
  410. */
  411. TEXT inb(SB), $0
  412. MOVL port+0(FP), DX
  413. XORL AX, AX
  414. INB
  415. RET
  416. TEXT insb(SB), $0
  417. MOVL port+0(FP), DX
  418. MOVL address+4(FP), DI
  419. MOVL count+8(FP), CX
  420. CLD
  421. REP; INSB
  422. RET
  423. TEXT ins(SB), $0
  424. MOVL port+0(FP), DX
  425. XORL AX, AX
  426. OP16; INL
  427. RET
  428. TEXT inss(SB), $0
  429. MOVL port+0(FP), DX
  430. MOVL address+4(FP), DI
  431. MOVL count+8(FP), CX
  432. CLD
  433. REP; OP16; INSL
  434. RET
  435. TEXT inl(SB), $0
  436. MOVL port+0(FP), DX
  437. INL
  438. RET
  439. TEXT insl(SB), $0
  440. MOVL port+0(FP), DX
  441. MOVL address+4(FP), DI
  442. MOVL count+8(FP), CX
  443. CLD
  444. REP; INSL
  445. RET
  446. TEXT outb(SB), $0
  447. MOVL port+0(FP), DX
  448. MOVL byte+4(FP), AX
  449. OUTB
  450. RET
  451. TEXT outsb(SB), $0
  452. MOVL port+0(FP), DX
  453. MOVL address+4(FP), SI
  454. MOVL count+8(FP), CX
  455. CLD
  456. REP; OUTSB
  457. RET
  458. TEXT outs(SB), $0
  459. MOVL port+0(FP), DX
  460. MOVL short+4(FP), AX
  461. OP16; OUTL
  462. RET
  463. TEXT outss(SB), $0
  464. MOVL port+0(FP), DX
  465. MOVL address+4(FP), SI
  466. MOVL count+8(FP), CX
  467. CLD
  468. REP; OP16; OUTSL
  469. RET
  470. TEXT outl(SB), $0
  471. MOVL port+0(FP), DX
  472. MOVL long+4(FP), AX
  473. OUTL
  474. RET
  475. TEXT outsl(SB), $0
  476. MOVL port+0(FP), DX
  477. MOVL address+4(FP), SI
  478. MOVL count+8(FP), CX
  479. CLD
  480. REP; OUTSL
  481. RET
  482. /*
  483. * Read/write various system registers.
  484. * CR4 and the 'model specific registers' should only be read/written
  485. * after it has been determined the processor supports them
  486. */
  487. TEXT lgdt(SB), $0 /* GDTR - global descriptor table */
  488. MOVL gdtptr+0(FP), AX
  489. MOVL (AX), GDTR
  490. RET
  491. TEXT lidt(SB), $0 /* IDTR - interrupt descriptor table */
  492. MOVL idtptr+0(FP), AX
  493. MOVL (AX), IDTR
  494. RET
  495. TEXT ltr(SB), $0 /* TR - task register */
  496. MOVL tptr+0(FP), AX
  497. MOVW AX, TASK
  498. RET
  499. TEXT getcr0(SB), $0 /* CR0 - processor control */
  500. MOVL CR0, AX
  501. RET
  502. TEXT getcr2(SB), $0 /* CR2 - page fault linear address */
  503. MOVL CR2, AX
  504. RET
  505. TEXT getcr3(SB), $0 /* CR3 - page directory base */
  506. MOVL CR3, AX
  507. RET
  508. TEXT putcr3(SB), $0
  509. MOVL cr3+0(FP), AX
  510. MOVL AX, CR3
  511. RET
  512. TEXT getcr4(SB), $0 /* CR4 - extensions */
  513. MOVL CR4, AX
  514. RET
  515. TEXT putcr4(SB), $0
  516. MOVL cr4+0(FP), AX
  517. MOVL AX, CR4
  518. RET
  519. TEXT invlpg(SB), $0
  520. /* 486+ only */
  521. MOVL va+0(FP), CX
  522. INVLPG
  523. RET
  524. TEXT _cycles(SB), $0 /* time stamp counter */
  525. RDTSC
  526. MOVL vlong+0(FP), CX /* &vlong */
  527. MOVL AX, 0(CX) /* lo */
  528. MOVL DX, 4(CX) /* hi */
  529. RET
  530. /*
  531. * stub for:
  532. * time stamp counter; low-order 32 bits of 64-bit cycle counter
  533. * Runs at fasthz/4 cycles per second (m->clkin>>3)
  534. */
  535. TEXT lcycles(SB),1,$0
  536. RDTSC
  537. RET
  538. TEXT rdmsr(SB), $0 /* model-specific register */
  539. MOVL index+0(FP), CX
  540. RDMSR
  541. MOVL vlong+4(FP), CX /* &vlong */
  542. MOVL AX, 0(CX) /* lo */
  543. MOVL DX, 4(CX) /* hi */
  544. RET
  545. TEXT wrmsr(SB), $0
  546. MOVL index+0(FP), CX
  547. MOVL lo+4(FP), AX
  548. MOVL hi+8(FP), DX
  549. WRMSR
  550. RET
  551. /*
  552. * Try to determine the CPU type which requires fiddling with EFLAGS.
  553. * If the Id bit can be toggled then the CPUID instruction can be used
  554. * to determine CPU identity and features. First have to check if it's
  555. * a 386 (Ac bit can't be set). If it's not a 386 and the Id bit can't be
  556. * toggled then it's an older 486 of some kind.
  557. *
  558. * cpuid(id[], &ax, &dx);
  559. */
  560. TEXT cpuid(SB), $0
  561. MOVL $0x240000, AX
  562. PUSHL AX
  563. POPFL /* set Id|Ac */
  564. PUSHFL
  565. POPL BX /* retrieve value */
  566. MOVL $0, AX
  567. PUSHL AX
  568. POPFL /* clear Id|Ac, EFLAGS initialised */
  569. PUSHFL
  570. POPL AX /* retrieve value */
  571. XORL BX, AX
  572. TESTL $0x040000, AX /* Ac */
  573. JZ _cpu386 /* can't set this bit on 386 */
  574. TESTL $0x200000, AX /* Id */
  575. JZ _cpu486 /* can't toggle this bit on some 486 */
  576. MOVL $0, AX
  577. CPUID
  578. MOVL id+0(FP), BP
  579. MOVL BX, 0(BP) /* "Genu" "Auth" "Cyri" */
  580. MOVL DX, 4(BP) /* "ineI" "enti" "xIns" */
  581. MOVL CX, 8(BP) /* "ntel" "cAMD" "tead" */
  582. MOVL $1, AX
  583. CPUID
  584. JMP _cpuid
  585. _cpu486:
  586. MOVL $0x400, AX
  587. MOVL $0, DX
  588. JMP _cpuid
  589. _cpu386:
  590. MOVL $0x300, AX
  591. MOVL $0, DX
  592. _cpuid:
  593. MOVL ax+4(FP), BP
  594. MOVL AX, 0(BP)
  595. MOVL dx+8(FP), BP
  596. MOVL DX, 0(BP)
  597. RET
  598. /*
  599. * Basic timing loop to determine CPU frequency.
  600. */
  601. TEXT aamloop(SB), $0
  602. MOVL count+0(FP), CX
  603. _aamloop:
  604. AAM
  605. LOOP _aamloop
  606. RET
  607. /*
  608. * Floating point.
  609. * Note: the encodings for the FCLEX, FINIT, FSAVE, FSTCW, FSENV and FSTSW
  610. * instructions do NOT have the WAIT prefix byte (i.e. they act like their
  611. * FNxxx variations) so WAIT instructions must be explicitly placed in the
  612. * code as necessary.
  613. */
  614. #define FPOFF(l) ;\
  615. MOVL CR0, AX ;\
  616. ANDL $0xC, AX /* EM, TS */ ;\
  617. CMPL AX, $0x8 ;\
  618. JEQ l ;\
  619. WAIT ;\
  620. l: ;\
  621. MOVL CR0, AX ;\
  622. ANDL $~0x4, AX /* EM=0 */ ;\
  623. ORL $0x28, AX /* NE=1, TS=1 */ ;\
  624. MOVL AX, CR0
  625. #define FPON ;\
  626. MOVL CR0, AX ;\
  627. ANDL $~0xC, AX /* EM=0, TS=0 */ ;\
  628. MOVL AX, CR0
  629. TEXT fpoff(SB), $0 /* disable */
  630. FPOFF(l1)
  631. RET
  632. TEXT fpinit(SB), $0 /* enable and init */
  633. FPON
  634. FINIT
  635. WAIT
  636. /* setfcr(FPPDBL|FPRNR|FPINVAL|FPZDIV|FPOVFL) */
  637. /* note that low 6 bits are masks, not enables, on this chip */
  638. PUSHW $0x0232
  639. FLDCW 0(SP)
  640. POPW AX
  641. WAIT
  642. RET
  643. TEXT fpsave(SB), $0 /* save state and disable */
  644. MOVL p+0(FP), AX
  645. FSAVE 0(AX) /* no WAIT */
  646. FPOFF(l2)
  647. RET
  648. TEXT fprestore(SB), $0 /* enable and restore state */
  649. FPON
  650. MOVL p+0(FP), AX
  651. FRSTOR 0(AX)
  652. WAIT
  653. RET
  654. TEXT fpstatus(SB), $0 /* get floating point status */
  655. FSTSW AX
  656. RET
  657. TEXT fpenv(SB), $0 /* save state without waiting */
  658. MOVL p+0(FP), AX
  659. FSTENV 0(AX)
  660. RET
  661. TEXT fpclear(SB), $0 /* clear pending exceptions */
  662. FPON
  663. FCLEX /* no WAIT */
  664. FPOFF(l3)
  665. RET
  666. /*
  667. */
  668. TEXT splhi(SB), $0
  669. shi:
  670. PUSHFL
  671. POPL AX
  672. TESTL $0x200, AX
  673. JZ alreadyhi
  674. MOVL $(MACHADDR+0x04), CX /* save PC in m->splpc */
  675. MOVL (SP), BX
  676. MOVL BX, (CX)
  677. alreadyhi:
  678. CLI
  679. RET
  680. TEXT spllo(SB), $0
  681. slo:
  682. PUSHFL
  683. POPL AX
  684. TESTL $0x200, AX
  685. JNZ alreadylo
  686. MOVL $(MACHADDR+0x04), CX /* clear m->splpc */
  687. MOVL $0, (CX)
  688. alreadylo:
  689. STI
  690. RET
  691. TEXT splx(SB), $0
  692. MOVL s+0(FP), AX
  693. TESTL $0x200, AX
  694. JNZ slo
  695. JMP shi
  696. TEXT spldone(SB), $0
  697. RET
  698. TEXT islo(SB), $0
  699. PUSHFL
  700. POPL AX
  701. ANDL $0x200, AX /* interrupt enable flag */
  702. RET
  703. /*
  704. * Test-And-Set
  705. */
  706. TEXT tas(SB), $0
  707. MOVL $0xDEADDEAD, AX
  708. MOVL lock+0(FP), BX
  709. XCHGL AX, (BX) /* lock->key */
  710. RET
  711. TEXT _xinc(SB), $0 /* void _xinc(long*); */
  712. MOVL l+0(FP), AX
  713. LOCK; INCL 0(AX)
  714. RET
  715. TEXT _xdec(SB), $0 /* long _xdec(long*); */
  716. MOVL l+0(FP), BX
  717. XORL AX, AX
  718. LOCK; DECL 0(BX)
  719. JLT _xdeclt
  720. JGT _xdecgt
  721. RET
  722. _xdecgt:
  723. INCL AX
  724. RET
  725. _xdeclt:
  726. DECL AX
  727. RET
  728. TEXT mb386(SB), $0
  729. POPL AX /* return PC */
  730. PUSHFL
  731. PUSHL CS
  732. PUSHL AX
  733. IRETL
  734. TEXT mb586(SB), $0
  735. XORL AX, AX
  736. CPUID
  737. RET
  738. TEXT sfence(SB), $0
  739. BYTE $0x0f
  740. BYTE $0xae
  741. BYTE $0xf8
  742. RET
  743. TEXT lfence(SB), $0
  744. BYTE $0x0f
  745. BYTE $0xae
  746. BYTE $0xe8
  747. RET
  748. TEXT mfence(SB), $0
  749. BYTE $0x0f
  750. BYTE $0xae
  751. BYTE $0xf0
  752. RET
  753. TEXT xchgw(SB), $0
  754. MOVL v+4(FP), AX
  755. MOVL p+0(FP), BX
  756. XCHGW AX, (BX)
  757. RET
  758. TEXT cmpswap486(SB), $0
  759. MOVL addr+0(FP), BX
  760. MOVL old+4(FP), AX
  761. MOVL new+8(FP), CX
  762. LOCK
  763. BYTE $0x0F; BYTE $0xB1; BYTE $0x0B /* CMPXCHGL CX, (BX) */
  764. JNZ didnt
  765. MOVL $1, AX
  766. RET
  767. didnt:
  768. XORL AX,AX
  769. RET
  770. TEXT mul64fract(SB), $0
  771. /*
  772. * Multiply two 64-bit number s and keep the middle 64 bits from the 128-bit result
  773. * See ../port/tod.c for motivation.
  774. */
  775. MOVL r+0(FP), CX
  776. XORL BX, BX /* BX = 0 */
  777. MOVL a+8(FP), AX
  778. MULL b+16(FP) /* a1*b1 */
  779. MOVL AX, 4(CX) /* r2 = lo(a1*b1) */
  780. MOVL a+8(FP), AX
  781. MULL b+12(FP) /* a1*b0 */
  782. MOVL AX, 0(CX) /* r1 = lo(a1*b0) */
  783. ADDL DX, 4(CX) /* r2 += hi(a1*b0) */
  784. MOVL a+4(FP), AX
  785. MULL b+16(FP) /* a0*b1 */
  786. ADDL AX, 0(CX) /* r1 += lo(a0*b1) */
  787. ADCL DX, 4(CX) /* r2 += hi(a0*b1) + carry */
  788. MOVL a+4(FP), AX
  789. MULL b+12(FP) /* a0*b0 */
  790. ADDL DX, 0(CX) /* r1 += hi(a0*b0) */
  791. ADCL BX, 4(CX) /* r2 += carry */
  792. RET
  793. /*
  794. * label consists of a stack pointer and a PC
  795. */
  796. TEXT gotolabel(SB), $0
  797. MOVL label+0(FP), AX
  798. MOVL 0(AX), SP /* restore sp */
  799. MOVL 4(AX), AX /* put return pc on the stack */
  800. MOVL AX, 0(SP)
  801. MOVL $1, AX /* return 1 */
  802. RET
  803. TEXT setlabel(SB), $0
  804. MOVL label+0(FP), AX
  805. MOVL SP, 0(AX) /* store sp */
  806. MOVL 0(SP), BX /* store return pc */
  807. MOVL BX, 4(AX)
  808. MOVL $0, AX /* return 0 */
  809. RET
  810. /*
  811. * Attempt at power saving. -rsc
  812. */
  813. TEXT halt(SB), $0
  814. CLI
  815. CMPL nrdy(SB), $0
  816. JEQ _nothingready
  817. STI
  818. RET
  819. _nothingready:
  820. STI
  821. HLT
  822. RET
  823. /*
  824. * Interrupt/exception handling.
  825. * Each entry in the vector table calls either _strayintr or _strayintrx depending
  826. * on whether an error code has been automatically pushed onto the stack
  827. * (_strayintrx) or not, in which case a dummy entry must be pushed before retrieving
  828. * the trap type from the vector table entry and placing it on the stack as part
  829. * of the Ureg structure.
  830. * The size of each entry in the vector table (6 bytes) is known in trapinit().
  831. */
  832. TEXT _strayintr(SB), $0
  833. PUSHL AX /* save AX */
  834. MOVL 4(SP), AX /* return PC from vectortable(SB) */
  835. JMP intrcommon
  836. TEXT _strayintrx(SB), $0
  837. XCHGL AX, (SP) /* swap AX with vectortable CALL PC */
  838. intrcommon:
  839. PUSHL DS /* save DS */
  840. PUSHL $(KDSEL)
  841. POPL DS /* fix up DS */
  842. MOVBLZX (AX), AX /* trap type -> AX */
  843. XCHGL AX, 4(SP) /* exchange trap type with saved AX */
  844. PUSHL ES /* save ES */
  845. PUSHL $(KDSEL)
  846. POPL ES /* fix up ES */
  847. PUSHL FS /* save the rest of the Ureg struct */
  848. PUSHL GS
  849. PUSHAL
  850. PUSHL SP /* Ureg* argument to trap */
  851. CALL trap(SB)
  852. TEXT forkret(SB), $0
  853. POPL AX
  854. POPAL
  855. POPL GS
  856. POPL FS
  857. POPL ES
  858. POPL DS
  859. ADDL $8, SP /* pop error code and trap type */
  860. IRETL
  861. TEXT vectortable(SB), $0
  862. CALL _strayintr(SB); BYTE $0x00 /* divide error */
  863. CALL _strayintr(SB); BYTE $0x01 /* debug exception */
  864. CALL _strayintr(SB); BYTE $0x02 /* NMI interrupt */
  865. CALL _strayintr(SB); BYTE $0x03 /* breakpoint */
  866. CALL _strayintr(SB); BYTE $0x04 /* overflow */
  867. CALL _strayintr(SB); BYTE $0x05 /* bound */
  868. CALL _strayintr(SB); BYTE $0x06 /* invalid opcode */
  869. CALL _strayintr(SB); BYTE $0x07 /* no coprocessor available */
  870. CALL _strayintrx(SB); BYTE $0x08 /* double fault */
  871. CALL _strayintr(SB); BYTE $0x09 /* coprocessor segment overflow */
  872. CALL _strayintrx(SB); BYTE $0x0A /* invalid TSS */
  873. CALL _strayintrx(SB); BYTE $0x0B /* segment not available */
  874. CALL _strayintrx(SB); BYTE $0x0C /* stack exception */
  875. CALL _strayintrx(SB); BYTE $0x0D /* general protection error */
  876. CALL _strayintrx(SB); BYTE $0x0E /* page fault */
  877. CALL _strayintr(SB); BYTE $0x0F /* */
  878. CALL _strayintr(SB); BYTE $0x10 /* coprocessor error */
  879. CALL _strayintrx(SB); BYTE $0x11 /* alignment check */
  880. CALL _strayintr(SB); BYTE $0x12 /* machine check */
  881. CALL _strayintr(SB); BYTE $0x13
  882. CALL _strayintr(SB); BYTE $0x14
  883. CALL _strayintr(SB); BYTE $0x15
  884. CALL _strayintr(SB); BYTE $0x16
  885. CALL _strayintr(SB); BYTE $0x17
  886. CALL _strayintr(SB); BYTE $0x18
  887. CALL _strayintr(SB); BYTE $0x19
  888. CALL _strayintr(SB); BYTE $0x1A
  889. CALL _strayintr(SB); BYTE $0x1B
  890. CALL _strayintr(SB); BYTE $0x1C
  891. CALL _strayintr(SB); BYTE $0x1D
  892. CALL _strayintr(SB); BYTE $0x1E
  893. CALL _strayintr(SB); BYTE $0x1F
  894. CALL _strayintr(SB); BYTE $0x20 /* VectorLAPIC */
  895. CALL _strayintr(SB); BYTE $0x21
  896. CALL _strayintr(SB); BYTE $0x22
  897. CALL _strayintr(SB); BYTE $0x23
  898. CALL _strayintr(SB); BYTE $0x24
  899. CALL _strayintr(SB); BYTE $0x25
  900. CALL _strayintr(SB); BYTE $0x26
  901. CALL _strayintr(SB); BYTE $0x27
  902. CALL _strayintr(SB); BYTE $0x28
  903. CALL _strayintr(SB); BYTE $0x29
  904. CALL _strayintr(SB); BYTE $0x2A
  905. CALL _strayintr(SB); BYTE $0x2B
  906. CALL _strayintr(SB); BYTE $0x2C
  907. CALL _strayintr(SB); BYTE $0x2D
  908. CALL _strayintr(SB); BYTE $0x2E
  909. CALL _strayintr(SB); BYTE $0x2F
  910. CALL _strayintr(SB); BYTE $0x30
  911. CALL _strayintr(SB); BYTE $0x31
  912. CALL _strayintr(SB); BYTE $0x32
  913. CALL _strayintr(SB); BYTE $0x33
  914. CALL _strayintr(SB); BYTE $0x34
  915. CALL _strayintr(SB); BYTE $0x35
  916. CALL _strayintr(SB); BYTE $0x36
  917. CALL _strayintr(SB); BYTE $0x37
  918. CALL _strayintr(SB); BYTE $0x38
  919. CALL _strayintr(SB); BYTE $0x39
  920. CALL _strayintr(SB); BYTE $0x3A
  921. CALL _strayintr(SB); BYTE $0x3B
  922. CALL _strayintr(SB); BYTE $0x3C
  923. CALL _strayintr(SB); BYTE $0x3D
  924. CALL _strayintr(SB); BYTE $0x3E
  925. CALL _strayintr(SB); BYTE $0x3F
  926. CALL _syscallintr(SB); BYTE $0x40 /* VectorSYSCALL */
  927. CALL _strayintr(SB); BYTE $0x41
  928. CALL _strayintr(SB); BYTE $0x42
  929. CALL _strayintr(SB); BYTE $0x43
  930. CALL _strayintr(SB); BYTE $0x44
  931. CALL _strayintr(SB); BYTE $0x45
  932. CALL _strayintr(SB); BYTE $0x46
  933. CALL _strayintr(SB); BYTE $0x47
  934. CALL _strayintr(SB); BYTE $0x48
  935. CALL _strayintr(SB); BYTE $0x49
  936. CALL _strayintr(SB); BYTE $0x4A
  937. CALL _strayintr(SB); BYTE $0x4B
  938. CALL _strayintr(SB); BYTE $0x4C
  939. CALL _strayintr(SB); BYTE $0x4D
  940. CALL _strayintr(SB); BYTE $0x4E
  941. CALL _strayintr(SB); BYTE $0x4F
  942. CALL _strayintr(SB); BYTE $0x50
  943. CALL _strayintr(SB); BYTE $0x51
  944. CALL _strayintr(SB); BYTE $0x52
  945. CALL _strayintr(SB); BYTE $0x53
  946. CALL _strayintr(SB); BYTE $0x54
  947. CALL _strayintr(SB); BYTE $0x55
  948. CALL _strayintr(SB); BYTE $0x56
  949. CALL _strayintr(SB); BYTE $0x57
  950. CALL _strayintr(SB); BYTE $0x58
  951. CALL _strayintr(SB); BYTE $0x59
  952. CALL _strayintr(SB); BYTE $0x5A
  953. CALL _strayintr(SB); BYTE $0x5B
  954. CALL _strayintr(SB); BYTE $0x5C
  955. CALL _strayintr(SB); BYTE $0x5D
  956. CALL _strayintr(SB); BYTE $0x5E
  957. CALL _strayintr(SB); BYTE $0x5F
  958. CALL _strayintr(SB); BYTE $0x60
  959. CALL _strayintr(SB); BYTE $0x61
  960. CALL _strayintr(SB); BYTE $0x62
  961. CALL _strayintr(SB); BYTE $0x63
  962. CALL _strayintr(SB); BYTE $0x64
  963. CALL _strayintr(SB); BYTE $0x65
  964. CALL _strayintr(SB); BYTE $0x66
  965. CALL _strayintr(SB); BYTE $0x67
  966. CALL _strayintr(SB); BYTE $0x68
  967. CALL _strayintr(SB); BYTE $0x69
  968. CALL _strayintr(SB); BYTE $0x6A
  969. CALL _strayintr(SB); BYTE $0x6B
  970. CALL _strayintr(SB); BYTE $0x6C
  971. CALL _strayintr(SB); BYTE $0x6D
  972. CALL _strayintr(SB); BYTE $0x6E
  973. CALL _strayintr(SB); BYTE $0x6F
  974. CALL _strayintr(SB); BYTE $0x70
  975. CALL _strayintr(SB); BYTE $0x71
  976. CALL _strayintr(SB); BYTE $0x72
  977. CALL _strayintr(SB); BYTE $0x73
  978. CALL _strayintr(SB); BYTE $0x74
  979. CALL _strayintr(SB); BYTE $0x75
  980. CALL _strayintr(SB); BYTE $0x76
  981. CALL _strayintr(SB); BYTE $0x77
  982. CALL _strayintr(SB); BYTE $0x78
  983. CALL _strayintr(SB); BYTE $0x79
  984. CALL _strayintr(SB); BYTE $0x7A
  985. CALL _strayintr(SB); BYTE $0x7B
  986. CALL _strayintr(SB); BYTE $0x7C
  987. CALL _strayintr(SB); BYTE $0x7D
  988. CALL _strayintr(SB); BYTE $0x7E
  989. CALL _strayintr(SB); BYTE $0x7F
  990. CALL _strayintr(SB); BYTE $0x80 /* Vector[A]PIC */
  991. CALL _strayintr(SB); BYTE $0x81
  992. CALL _strayintr(SB); BYTE $0x82
  993. CALL _strayintr(SB); BYTE $0x83
  994. CALL _strayintr(SB); BYTE $0x84
  995. CALL _strayintr(SB); BYTE $0x85
  996. CALL _strayintr(SB); BYTE $0x86
  997. CALL _strayintr(SB); BYTE $0x87
  998. CALL _strayintr(SB); BYTE $0x88
  999. CALL _strayintr(SB); BYTE $0x89
  1000. CALL _strayintr(SB); BYTE $0x8A
  1001. CALL _strayintr(SB); BYTE $0x8B
  1002. CALL _strayintr(SB); BYTE $0x8C
  1003. CALL _strayintr(SB); BYTE $0x8D
  1004. CALL _strayintr(SB); BYTE $0x8E
  1005. CALL _strayintr(SB); BYTE $0x8F
  1006. CALL _strayintr(SB); BYTE $0x90
  1007. CALL _strayintr(SB); BYTE $0x91
  1008. CALL _strayintr(SB); BYTE $0x92
  1009. CALL _strayintr(SB); BYTE $0x93
  1010. CALL _strayintr(SB); BYTE $0x94
  1011. CALL _strayintr(SB); BYTE $0x95
  1012. CALL _strayintr(SB); BYTE $0x96
  1013. CALL _strayintr(SB); BYTE $0x97
  1014. CALL _strayintr(SB); BYTE $0x98
  1015. CALL _strayintr(SB); BYTE $0x99
  1016. CALL _strayintr(SB); BYTE $0x9A
  1017. CALL _strayintr(SB); BYTE $0x9B
  1018. CALL _strayintr(SB); BYTE $0x9C
  1019. CALL _strayintr(SB); BYTE $0x9D
  1020. CALL _strayintr(SB); BYTE $0x9E
  1021. CALL _strayintr(SB); BYTE $0x9F
  1022. CALL _strayintr(SB); BYTE $0xA0
  1023. CALL _strayintr(SB); BYTE $0xA1
  1024. CALL _strayintr(SB); BYTE $0xA2
  1025. CALL _strayintr(SB); BYTE $0xA3
  1026. CALL _strayintr(SB); BYTE $0xA4
  1027. CALL _strayintr(SB); BYTE $0xA5
  1028. CALL _strayintr(SB); BYTE $0xA6
  1029. CALL _strayintr(SB); BYTE $0xA7
  1030. CALL _strayintr(SB); BYTE $0xA8
  1031. CALL _strayintr(SB); BYTE $0xA9
  1032. CALL _strayintr(SB); BYTE $0xAA
  1033. CALL _strayintr(SB); BYTE $0xAB
  1034. CALL _strayintr(SB); BYTE $0xAC
  1035. CALL _strayintr(SB); BYTE $0xAD
  1036. CALL _strayintr(SB); BYTE $0xAE
  1037. CALL _strayintr(SB); BYTE $0xAF
  1038. CALL _strayintr(SB); BYTE $0xB0
  1039. CALL _strayintr(SB); BYTE $0xB1
  1040. CALL _strayintr(SB); BYTE $0xB2
  1041. CALL _strayintr(SB); BYTE $0xB3
  1042. CALL _strayintr(SB); BYTE $0xB4
  1043. CALL _strayintr(SB); BYTE $0xB5
  1044. CALL _strayintr(SB); BYTE $0xB6
  1045. CALL _strayintr(SB); BYTE $0xB7
  1046. CALL _strayintr(SB); BYTE $0xB8
  1047. CALL _strayintr(SB); BYTE $0xB9
  1048. CALL _strayintr(SB); BYTE $0xBA
  1049. CALL _strayintr(SB); BYTE $0xBB
  1050. CALL _strayintr(SB); BYTE $0xBC
  1051. CALL _strayintr(SB); BYTE $0xBD
  1052. CALL _strayintr(SB); BYTE $0xBE
  1053. CALL _strayintr(SB); BYTE $0xBF
  1054. CALL _strayintr(SB); BYTE $0xC0
  1055. CALL _strayintr(SB); BYTE $0xC1
  1056. CALL _strayintr(SB); BYTE $0xC2
  1057. CALL _strayintr(SB); BYTE $0xC3
  1058. CALL _strayintr(SB); BYTE $0xC4
  1059. CALL _strayintr(SB); BYTE $0xC5
  1060. CALL _strayintr(SB); BYTE $0xC6
  1061. CALL _strayintr(SB); BYTE $0xC7
  1062. CALL _strayintr(SB); BYTE $0xC8
  1063. CALL _strayintr(SB); BYTE $0xC9
  1064. CALL _strayintr(SB); BYTE $0xCA
  1065. CALL _strayintr(SB); BYTE $0xCB
  1066. CALL _strayintr(SB); BYTE $0xCC
  1067. CALL _strayintr(SB); BYTE $0xCD
  1068. CALL _strayintr(SB); BYTE $0xCE
  1069. CALL _strayintr(SB); BYTE $0xCF
  1070. CALL _strayintr(SB); BYTE $0xD0
  1071. CALL _strayintr(SB); BYTE $0xD1
  1072. CALL _strayintr(SB); BYTE $0xD2
  1073. CALL _strayintr(SB); BYTE $0xD3
  1074. CALL _strayintr(SB); BYTE $0xD4
  1075. CALL _strayintr(SB); BYTE $0xD5
  1076. CALL _strayintr(SB); BYTE $0xD6
  1077. CALL _strayintr(SB); BYTE $0xD7
  1078. CALL _strayintr(SB); BYTE $0xD8
  1079. CALL _strayintr(SB); BYTE $0xD9
  1080. CALL _strayintr(SB); BYTE $0xDA
  1081. CALL _strayintr(SB); BYTE $0xDB
  1082. CALL _strayintr(SB); BYTE $0xDC
  1083. CALL _strayintr(SB); BYTE $0xDD
  1084. CALL _strayintr(SB); BYTE $0xDE
  1085. CALL _strayintr(SB); BYTE $0xDF
  1086. CALL _strayintr(SB); BYTE $0xE0
  1087. CALL _strayintr(SB); BYTE $0xE1
  1088. CALL _strayintr(SB); BYTE $0xE2
  1089. CALL _strayintr(SB); BYTE $0xE3
  1090. CALL _strayintr(SB); BYTE $0xE4
  1091. CALL _strayintr(SB); BYTE $0xE5
  1092. CALL _strayintr(SB); BYTE $0xE6
  1093. CALL _strayintr(SB); BYTE $0xE7
  1094. CALL _strayintr(SB); BYTE $0xE8
  1095. CALL _strayintr(SB); BYTE $0xE9
  1096. CALL _strayintr(SB); BYTE $0xEA
  1097. CALL _strayintr(SB); BYTE $0xEB
  1098. CALL _strayintr(SB); BYTE $0xEC
  1099. CALL _strayintr(SB); BYTE $0xED
  1100. CALL _strayintr(SB); BYTE $0xEE
  1101. CALL _strayintr(SB); BYTE $0xEF
  1102. CALL _strayintr(SB); BYTE $0xF0
  1103. CALL _strayintr(SB); BYTE $0xF1
  1104. CALL _strayintr(SB); BYTE $0xF2
  1105. CALL _strayintr(SB); BYTE $0xF3
  1106. CALL _strayintr(SB); BYTE $0xF4
  1107. CALL _strayintr(SB); BYTE $0xF5
  1108. CALL _strayintr(SB); BYTE $0xF6
  1109. CALL _strayintr(SB); BYTE $0xF7
  1110. CALL _strayintr(SB); BYTE $0xF8
  1111. CALL _strayintr(SB); BYTE $0xF9
  1112. CALL _strayintr(SB); BYTE $0xFA
  1113. CALL _strayintr(SB); BYTE $0xFB
  1114. CALL _strayintr(SB); BYTE $0xFC
  1115. CALL _strayintr(SB); BYTE $0xFD
  1116. CALL _strayintr(SB); BYTE $0xFE
  1117. CALL _strayintr(SB); BYTE $0xFF