sdiahci.c 37 KB

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  1. /*
  2. * intel/amd ahci sata controller
  3. * copyright © 2007 coraid, inc.
  4. */
  5. #include "u.h"
  6. #include "../port/lib.h"
  7. #include "mem.h"
  8. #include "dat.h"
  9. #include "fns.h"
  10. #include "io.h"
  11. #include "../port/error.h"
  12. #include "../port/sd.h"
  13. #include "ahci.h"
  14. #define dprint(...) if(debug) iprint(__VA_ARGS__); else USED(debug)
  15. #define idprint(...) if(prid) print(__VA_ARGS__); else USED(prid)
  16. #define aprint(...) if(datapi) iprint(__VA_ARGS__); else USED(datapi)
  17. #define Tname(c) tname[(c)->type]
  18. enum {
  19. NCtlr = 4,
  20. NCtlrdrv= 32,
  21. NDrive = NCtlr*NCtlrdrv,
  22. Read = 0,
  23. Write,
  24. };
  25. /* pci space configuration */
  26. enum {
  27. Pmap = 0x90,
  28. Ppcs = 0x91,
  29. Prev = 0xa8,
  30. };
  31. enum {
  32. Tesb,
  33. Tich,
  34. Tsb600,
  35. };
  36. #define Intel(x) ((x) == Tesb || (x) == Tich)
  37. static char *tname[] = {
  38. "63xxesb",
  39. "ich",
  40. "sb600",
  41. };
  42. enum {
  43. Dnull,
  44. Dmissing,
  45. Dnew,
  46. Dready,
  47. Derror,
  48. Dreset,
  49. Doffline,
  50. Dportreset,
  51. Dlast,
  52. };
  53. static char *diskstates[Dlast] = {
  54. "null",
  55. "missing",
  56. "new",
  57. "ready",
  58. "error",
  59. "reset",
  60. "offline",
  61. "portreset",
  62. };
  63. extern SDifc sdiahciifc;
  64. typedef struct Ctlr Ctlr;
  65. enum {
  66. DMautoneg,
  67. DMsatai,
  68. DMsataii,
  69. };
  70. static char *modename[] = {
  71. "auto",
  72. "satai",
  73. "sataii",
  74. };
  75. static char *flagname[] = {
  76. "llba",
  77. "smart",
  78. "power",
  79. "nop",
  80. "atapi",
  81. "atapi16",
  82. };
  83. typedef struct {
  84. Lock;
  85. Ctlr *ctlr;
  86. SDunit *unit;
  87. char name[10];
  88. Aport *port;
  89. Aportm portm;
  90. Aportc portc; /* redundant ptr to port and portm. */
  91. uchar mediachange;
  92. uchar state;
  93. uchar smartrs;
  94. uvlong sectors;
  95. ulong intick;
  96. int wait;
  97. uchar mode; /* DMautoneg, satai or sataii. */
  98. uchar active;
  99. char serial[20+1];
  100. char firmware[8+1];
  101. char model[40+1];
  102. ushort info[0x200];
  103. int driveno; /* ctlr*NCtlrdrv + unit */
  104. /* controller port # != driveno when not all ports are enabled */
  105. int portno;
  106. } Drive;
  107. struct Ctlr {
  108. Lock;
  109. int type;
  110. int enabled;
  111. SDev *sdev;
  112. Pcidev *pci;
  113. uchar *mmio;
  114. ulong *lmmio;
  115. Ahba *hba;
  116. Drive rawdrive[NCtlrdrv];
  117. Drive* drive[NCtlrdrv];
  118. int ndrive;
  119. };
  120. static Ctlr iactlr[NCtlr];
  121. static SDev sdevs[NCtlr];
  122. static int niactlr;
  123. static Drive *iadrive[NDrive];
  124. static int niadrive;
  125. static int debug;
  126. static int prid = 1;
  127. static int datapi;
  128. static char stab[] = {
  129. [0] 'i', 'm',
  130. [8] 't', 'c', 'p', 'e',
  131. [16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  132. };
  133. static void
  134. serrstr(ulong r, char *s, char *e)
  135. {
  136. int i;
  137. e -= 3;
  138. for(i = 0; i < nelem(stab) && s < e; i++)
  139. if(r & (1<<i) && stab[i]){
  140. *s++ = stab[i];
  141. if(SerrBad & (1<<i))
  142. *s++ = '*';
  143. }
  144. *s = 0;
  145. }
  146. static char ntab[] = "0123456789abcdef";
  147. static void
  148. preg(uchar *reg, int n)
  149. {
  150. int i;
  151. char buf[25*3+1], *e;
  152. e = buf;
  153. for(i = 0; i < n; i++){
  154. *e++ = ntab[reg[i]>>4];
  155. *e++ = ntab[reg[i]&0xf];
  156. *e++ = ' ';
  157. }
  158. *e++ = '\n';
  159. *e = 0;
  160. dprint(buf);
  161. }
  162. static void
  163. dreg(char *s, Aport *p)
  164. {
  165. dprint("%stask=%ux; cmd=%ux; ci=%ux; is=%ux\n", s, p->task, p->cmd,
  166. p->ci, p->isr);
  167. }
  168. static void
  169. esleep(int ms)
  170. {
  171. if(waserror())
  172. return;
  173. tsleep(&up->sleep, return0, 0, ms);
  174. poperror();
  175. }
  176. typedef struct {
  177. Aport *p;
  178. int i;
  179. }Asleep;
  180. static int
  181. ahciclear(void *v)
  182. {
  183. Asleep *s;
  184. s = v;
  185. return (s->p->ci & s->i) == 0;
  186. }
  187. static void
  188. aesleep(Aportm *m, Asleep *a, int ms)
  189. {
  190. if(waserror())
  191. return;
  192. tsleep(m, ahciclear, a, ms);
  193. poperror();
  194. }
  195. static int
  196. ahciwait(Aportc *c, int ms)
  197. {
  198. Asleep as;
  199. Aport *p;
  200. p = c->p;
  201. p->ci = 1;
  202. as.p = p;
  203. as.i = 1;
  204. aesleep(c->m, &as, ms);
  205. if((p->task&1) == 0 && p->ci == 0)
  206. return 0;
  207. dreg("ahciwait timeout ", c->p);
  208. return -1;
  209. }
  210. static int
  211. nop(Aportc *pc)
  212. {
  213. uchar *c;
  214. Actab *t;
  215. Alist *l;
  216. if((pc->m->feat & Dnop) == 0)
  217. return -1;
  218. t = pc->m->ctab;
  219. c = t->cfis;
  220. memset(c, 0, 0x20);
  221. c[0] = 0x27;
  222. c[1] = 0x80;
  223. c[2] = 0x00;
  224. c[7] = 0xa0; /* obsolete device bits */
  225. l = pc->m->list;
  226. l->flags = Lwrite | 0x5;
  227. l->len = 0;
  228. l->ctab = PCIWADDR(t);
  229. l->ctabhi = 0;
  230. return ahciwait(pc, 3*1000);
  231. }
  232. static int
  233. setfeatures(Aportc *pc, uchar f)
  234. {
  235. uchar *c;
  236. Actab *t;
  237. Alist *l;
  238. t = pc->m->ctab;
  239. c = t->cfis;
  240. memset(c, 0, 0x20);
  241. c[0] = 0x27;
  242. c[1] = 0x80;
  243. c[2] = 0xef;
  244. c[3] = f;
  245. c[7] = 0xa0; /* obsolete device bits */
  246. l = pc->m->list;
  247. l->flags = Lwrite | 0x5;
  248. l->len = 0;
  249. l->ctab = PCIWADDR(t);
  250. l->ctabhi = 0;
  251. return ahciwait(pc, 3*1000);
  252. }
  253. static int
  254. setudmamode(Aportc *pc, uchar f)
  255. {
  256. uchar *c;
  257. Actab *t;
  258. Alist *l;
  259. /* hack */
  260. if((pc->p->sig >> 16) == 0xeb14)
  261. return 0;
  262. t = pc->m->ctab;
  263. c = t->cfis;
  264. memset(c, 0, 0x20);
  265. c[0] = 0x27;
  266. c[1] = 0x80;
  267. c[2] = 0xef;
  268. c[3] = 3; /* set transfer mode */
  269. c[7] = 0xa0; /* obsolete device bits */
  270. c[12] = 0x40 | f; /* sector count */
  271. l = pc->m->list;
  272. l->flags = Lwrite | 0x5;
  273. l->len = 0;
  274. l->ctab = PCIWADDR(t);
  275. l->ctabhi = 0;
  276. return ahciwait(pc, 3*1000);
  277. }
  278. static void
  279. asleep(int ms)
  280. {
  281. if(up == nil)
  282. delay(ms);
  283. else
  284. esleep(ms);
  285. }
  286. static int
  287. ahciportreset(Aportc *c)
  288. {
  289. u32int *cmd, i;
  290. Aport *p;
  291. p = c->p;
  292. cmd = &p->cmd;
  293. *cmd &= ~(Afre|Ast);
  294. for(i = 0; i < 500; i += 25){
  295. if((*cmd&Acr) == 0)
  296. break;
  297. asleep(25);
  298. }
  299. p->sctl = 1|(p->sctl&~7);
  300. delay(1);
  301. p->sctl &= ~7;
  302. return 0;
  303. }
  304. static int
  305. smart(Aportc *pc, int n)
  306. {
  307. uchar *c;
  308. Actab *t;
  309. Alist *l;
  310. if((pc->m->feat&Dsmart) == 0)
  311. return -1;
  312. t = pc->m->ctab;
  313. c = t->cfis;
  314. memset(c, 0, 0x20);
  315. c[0] = 0x27;
  316. c[1] = 0x80;
  317. c[2] = 0xb0;
  318. c[3] = 0xd8 + n; /* able smart */
  319. c[5] = 0x4f;
  320. c[6] = 0xc2;
  321. c[7] = 0xa0;
  322. l = pc->m->list;
  323. l->flags = Lwrite | 0x5;
  324. l->len = 0;
  325. l->ctab = PCIWADDR(t);
  326. l->ctabhi = 0;
  327. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  328. dprint("smart fail %ux\n", pc->p->task);
  329. // preg(pc->m->fis.r, 20);
  330. return -1;
  331. }
  332. if(n)
  333. return 0;
  334. return 1;
  335. }
  336. static int
  337. smartrs(Aportc *pc)
  338. {
  339. uchar *c;
  340. Actab *t;
  341. Alist *l;
  342. t = pc->m->ctab;
  343. c = t->cfis;
  344. memset(c, 0, 0x20);
  345. c[0] = 0x27;
  346. c[1] = 0x80;
  347. c[2] = 0xb0;
  348. c[3] = 0xda; /* return smart status */
  349. c[5] = 0x4f;
  350. c[6] = 0xc2;
  351. c[7] = 0xa0;
  352. l = pc->m->list;
  353. l->flags = Lwrite | 0x5;
  354. l->len = 0;
  355. l->ctab = PCIWADDR(t);
  356. l->ctabhi = 0;
  357. c = pc->m->fis.r;
  358. if(ahciwait(pc, 1000) == -1 || pc->p->task & (1|32)){
  359. dprint("smart fail %ux\n", pc->p->task);
  360. preg(c, 20);
  361. return -1;
  362. }
  363. if(c[5] == 0x4f && c[6] == 0xc2)
  364. return 1;
  365. return 0;
  366. }
  367. static int
  368. flushcache(Aportc *pc)
  369. {
  370. uchar *c, llba;
  371. Actab *t;
  372. Alist *l;
  373. static uchar tab[2] = {0xe7, 0xea};
  374. llba = pc->m->feat&Dllba? 1: 0;
  375. t = pc->m->ctab;
  376. c = t->cfis;
  377. memset(c, 0, 0x20);
  378. c[0] = 0x27;
  379. c[1] = 0x80;
  380. c[2] = tab[llba];
  381. c[7] = 0xa0;
  382. l = pc->m->list;
  383. l->flags = Lwrite | 0x5;
  384. l->len = 0;
  385. l->ctab = PCIWADDR(t);
  386. l->ctabhi = 0;
  387. if(ahciwait(pc, 60000) == -1 || pc->p->task & (1|32)){
  388. dprint("flushcache fail %ux\n", pc->p->task);
  389. // preg( pc->m->fis.r, 20);
  390. return -1;
  391. }
  392. return 0;
  393. }
  394. static ushort
  395. gbit16(void *a)
  396. {
  397. ushort j;
  398. uchar *i;
  399. i = a;
  400. j = i[1] << 8;
  401. j |= i[0];
  402. return j;
  403. }
  404. static u32int
  405. gbit32(void *a)
  406. {
  407. u32int j;
  408. uchar *i;
  409. i = a;
  410. j = i[3] << 24;
  411. j |= i[2] << 16;
  412. j |= i[1] << 8;
  413. j |= i[0];
  414. return j;
  415. }
  416. static uvlong
  417. gbit64(void *a)
  418. {
  419. uchar *i;
  420. i = a;
  421. return (uvlong)gbit32(i+4) << 32 | gbit32(a);
  422. }
  423. static int
  424. ahciidentify0(Aportc *pc, void *id, int atapi)
  425. {
  426. uchar *c;
  427. Actab *t;
  428. Alist *l;
  429. Aprdt *p;
  430. static uchar tab[] = { 0xec, 0xa1, };
  431. t = pc->m->ctab;
  432. c = t->cfis;
  433. memset(c, 0, 0x20);
  434. c[0] = 0x27;
  435. c[1] = 0x80;
  436. c[2] = tab[atapi];
  437. c[7] = 0xa0; /* obsolete device bits */
  438. l = pc->m->list;
  439. l->flags = 1<<16 | 0x5;
  440. l->len = 0;
  441. l->ctab = PCIWADDR(t);
  442. l->ctabhi = 0;
  443. memset(id, 0, 0x100);
  444. p = &t->prdt;
  445. p->dba = PCIWADDR(id);
  446. p->dbahi = 0;
  447. p->count = 1<<31 | (0x200-2) | 1;
  448. return ahciwait(pc, 3*1000);
  449. }
  450. static vlong
  451. ahciidentify(Aportc *pc, ushort *id)
  452. {
  453. int i, sig;
  454. vlong s;
  455. Aportm *m;
  456. m = pc->m;
  457. m->feat = 0;
  458. m->smart = 0;
  459. i = 0;
  460. sig = pc->p->sig >> 16;
  461. if(sig == 0xeb14){
  462. m->feat |= Datapi;
  463. i = 1;
  464. }
  465. if(ahciidentify0(pc, id, i) == -1)
  466. return -1;
  467. i = gbit16(id+83) | gbit16(id+86);
  468. if(i & (1<<10)){
  469. m->feat |= Dllba;
  470. s = gbit64(id+100);
  471. }else
  472. s = gbit32(id+60);
  473. if(m->feat&Datapi){
  474. i = gbit16(id+0);
  475. if(i&1)
  476. m->feat |= Datapi16;
  477. }
  478. i = gbit16(id+83);
  479. if((i>>14) == 1) {
  480. if(i & (1<<3))
  481. m->feat |= Dpower;
  482. i = gbit16(id+82);
  483. if(i & 1)
  484. m->feat |= Dsmart;
  485. if(i & (1<<14))
  486. m->feat |= Dnop;
  487. }
  488. return s;
  489. }
  490. static int
  491. ahciquiet(Aport *a)
  492. {
  493. u32int *p, i;
  494. p = &a->cmd;
  495. *p &= ~Ast;
  496. for(i = 0; i < 500; i += 50){
  497. if((*p & Acr) == 0)
  498. goto stop;
  499. asleep(50);
  500. }
  501. return -1;
  502. stop:
  503. if((a->task & (ASdrq|ASbsy)) == 0){
  504. *p |= Ast;
  505. return 0;
  506. }
  507. *p |= Aclo;
  508. for(i = 0; i < 500; i += 50){
  509. if((*p & Aclo) == 0)
  510. goto stop1;
  511. asleep(50);
  512. }
  513. return -1;
  514. stop1:
  515. /* extra check */
  516. dprint("clo clear %x\n", a->task);
  517. if(a->task & ASbsy)
  518. return -1;
  519. *p |= Ast;
  520. return 0;
  521. }
  522. static int
  523. ahcicomreset(Aportc *pc)
  524. {
  525. uchar *c;
  526. Actab *t;
  527. Alist *l;
  528. dprint("ahcicomreset\n");
  529. dreg("comreset ", pc->p);
  530. if(ahciquiet(pc->p) == -1){
  531. dprint("ahciquiet fails\n");
  532. return -1;
  533. }
  534. dreg("comreset ", pc->p);
  535. t = pc->m->ctab;
  536. c = t->cfis;
  537. memset(c, 0, 0x20);
  538. c[0] = 0x27;
  539. c[1] = 0x00;
  540. c[7] = 0xa0; /* obsolete device bits */
  541. c[15] = 1<<2; /* srst */
  542. l = pc->m->list;
  543. l->flags = Lclear | Lreset | 0x5;
  544. l->len = 0;
  545. l->ctab = PCIWADDR(t);
  546. l->ctabhi = 0;
  547. if(ahciwait(pc, 500) == -1){
  548. dprint("first command in comreset fails\n");
  549. return -1;
  550. }
  551. microdelay(250);
  552. dreg("comreset ", pc->p);
  553. memset(c, 0, 0x20);
  554. c[0] = 0x27;
  555. c[1] = 0x00;
  556. c[7] = 0xa0; /* obsolete device bits */
  557. l = pc->m->list;
  558. l->flags = Lwrite | 0x5;
  559. l->len = 0;
  560. l->ctab = PCIWADDR(t);
  561. l->ctabhi = 0;
  562. if(ahciwait(pc, 150) == -1){
  563. dprint("second command in comreset fails\n");
  564. return -1;
  565. }
  566. dreg("comreset ", pc->p);
  567. return 0;
  568. }
  569. static int
  570. ahciidle(Aport *port)
  571. {
  572. u32int *p, i, r;
  573. p = &port->cmd;
  574. if((*p & Arun) == 0)
  575. return 0;
  576. *p &= ~Ast;
  577. r = 0;
  578. for(i = 0; i < 500; i += 25){
  579. if((*p & Acr) == 0)
  580. goto stop;
  581. asleep(25);
  582. }
  583. r = -1;
  584. stop:
  585. if((*p & Afre) == 0)
  586. return r;
  587. *p &= ~Afre;
  588. for(i = 0; i < 500; i += 25){
  589. if((*p & Afre) == 0)
  590. return 0;
  591. asleep(25);
  592. }
  593. return -1;
  594. }
  595. /*
  596. * § 6.2.2.1 first part; comreset handled by reset disk.
  597. * - remainder is handled by configdisk.
  598. * - ahcirecover is a quick recovery from a failed command.
  599. */
  600. int
  601. ahciswreset(Aportc *pc)
  602. {
  603. int i;
  604. i = ahciidle(pc->p);
  605. pc->p->cmd |= Afre;
  606. if(i == -1)
  607. return -1;
  608. if(pc->p->task & (ASdrq|ASbsy))
  609. return -1;
  610. return 0;
  611. }
  612. int
  613. ahcirecover(Aportc *pc)
  614. {
  615. ahciswreset(pc);
  616. pc->p->cmd |= Ast;
  617. if(setudmamode(pc, 5) == -1)
  618. return -1;
  619. return 0;
  620. }
  621. static void*
  622. malign(int size, int align)
  623. {
  624. void *v;
  625. v = xspanalloc(size, align, 0);
  626. memset(v, 0, size);
  627. return v;
  628. }
  629. static void
  630. setupfis(Afis *f)
  631. {
  632. f->base = malign(0x100, 0x100);
  633. f->d = f->base + 0;
  634. f->p = f->base + 0x20;
  635. f->r = f->base + 0x40;
  636. f->u = f->base + 0x60;
  637. f->devicebits = (u32int*)(f->base + 0x58);
  638. }
  639. static void
  640. ahciwakeup(Aport *p)
  641. {
  642. ushort s;
  643. s = p->sstatus;
  644. if((s & 0xF00) != 0x600)
  645. return;
  646. if((s & 7) != 1){ /* not (device, no phy) */
  647. iprint("ahci: slumbering drive unwakeable %ux\n", s);
  648. return;
  649. }
  650. p->sctl = 3*Aipm | 0*Aspd | Adet;
  651. delay(1);
  652. p->sctl &= ~7;
  653. // iprint("ahci: wake %ux -> %ux\n", s, p->sstatus);
  654. }
  655. static int
  656. ahciconfigdrive(Ahba *h, Aportc *c, int mode)
  657. {
  658. Aportm *m;
  659. Aport *p;
  660. p = c->p;
  661. m = c->m;
  662. if(m->list == 0){
  663. setupfis(&m->fis);
  664. m->list = malign(sizeof *m->list, 1024);
  665. m->ctab = malign(sizeof *m->ctab, 128);
  666. }
  667. if(p->sstatus & 3 && h->cap & Hsss){
  668. /* device connected & staggered spin-up */
  669. dprint("configdrive: spinning up ... [%ux]\n", p->sstatus);
  670. p->cmd |= Apod|Asud;
  671. asleep(1400);
  672. }
  673. p->serror = SerrAll;
  674. p->list = PCIWADDR(m->list);
  675. p->listhi = 0;
  676. p->fis = PCIWADDR(m->fis.base);
  677. p->fishi = 0;
  678. p->cmd |= Afre|Ast;
  679. if((p->sstatus & 0xF0F) == 0x601) /* drive coming up in slumbering? */
  680. ahciwakeup(p);
  681. /* disable power managment sequence from book. */
  682. p->sctl = (3*Aipm) | (mode*Aspd) | 0*Adet;
  683. p->cmd &= ~Aalpe;
  684. p->ie = IEM;
  685. return 0;
  686. }
  687. static int
  688. ahcienable(Ahba *h)
  689. {
  690. h->ghc |= Hie;
  691. return 0;
  692. }
  693. static int
  694. ahcidisable(Ahba *h)
  695. {
  696. h->ghc &= ~Hie;
  697. return 0;
  698. }
  699. static int
  700. countbits(ulong u)
  701. {
  702. int i, n;
  703. n = 0;
  704. for(i = 0; i < 32; i++)
  705. if(u & (1<<i))
  706. n++;
  707. return n;
  708. }
  709. static int
  710. ahciconf(Ctlr *ctlr)
  711. {
  712. Ahba *h;
  713. u32int u;
  714. h = ctlr->hba = (Ahba*)ctlr->mmio;
  715. u = h->cap;
  716. if((u&Hsam) == 0)
  717. h->ghc |= Hae;
  718. print("#S/sd%c: ahci: port %#p: hba sss %d; ncs %d; coal %d; "
  719. "mports %d; led %d; clo %d; ems %d\n",
  720. ctlr->sdev->idno, h,
  721. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1,
  722. (u>>24) & 1, (u>>6) & 1);
  723. return countbits(h->pi);
  724. }
  725. static int
  726. ahcihbareset(Ahba *h)
  727. {
  728. int wait;
  729. h->ghc |= 1;
  730. for(wait = 0; wait < 1000; wait += 100){
  731. if(h->ghc == 0)
  732. return 0;
  733. delay(100);
  734. }
  735. return -1;
  736. }
  737. static void
  738. idmove(char *p, ushort *a, int n)
  739. {
  740. int i;
  741. char *op, *e;
  742. op = p;
  743. for(i = 0; i < n/2; i++){
  744. *p++ = a[i] >> 8;
  745. *p++ = a[i];
  746. }
  747. *p = 0;
  748. while(p > op && *--p == ' ')
  749. *p = 0;
  750. e = p;
  751. p = op;
  752. while(*p == ' ')
  753. p++;
  754. memmove(op, p, n - (e - p));
  755. }
  756. static int
  757. identify(Drive *d)
  758. {
  759. u16int *id;
  760. vlong osectors, s;
  761. uchar oserial[21];
  762. SDunit *u;
  763. id = d->info;
  764. s = ahciidentify(&d->portc, id);
  765. if(s == -1){
  766. d->state = Derror;
  767. return -1;
  768. }
  769. osectors = d->sectors;
  770. memmove(oserial, d->serial, sizeof d->serial);
  771. d->sectors = s;
  772. d->smartrs = 0;
  773. idmove(d->serial, id+10, 20);
  774. idmove(d->firmware, id+23, 8);
  775. idmove(d->model, id+27, 40);
  776. u = d->unit;
  777. memset(u->inquiry, 0, sizeof u->inquiry);
  778. u->inquiry[2] = 2;
  779. u->inquiry[3] = 2;
  780. u->inquiry[4] = sizeof u->inquiry - 4;
  781. memmove(u->inquiry+8, d->model, 40);
  782. if((osectors == 0 || osectors != s) &&
  783. memcmp(oserial, d->serial, sizeof oserial) != 0){
  784. d->mediachange = 1;
  785. u->sectors = 0;
  786. }
  787. return 0;
  788. }
  789. static void
  790. clearci(Aport *p)
  791. {
  792. if(p->cmd & Ast) {
  793. p->cmd &= ~Ast;
  794. p->cmd |= Ast;
  795. }
  796. }
  797. static void
  798. updatedrive(Drive *d)
  799. {
  800. u32int cause, serr, s0, pr, ewake;
  801. char *name;
  802. Aport *p;
  803. static u32int last;
  804. pr = 1;
  805. ewake = 0;
  806. p = d->port;
  807. cause = p->isr;
  808. serr = p->serror;
  809. p->isr = cause;
  810. name = "??";
  811. if(d->unit && d->unit->name)
  812. name = d->unit->name;
  813. if(p->ci == 0){
  814. d->portm.flag |= Fdone;
  815. wakeup(&d->portm);
  816. pr = 0;
  817. }else if(cause & Adps)
  818. pr = 0;
  819. if(cause & Ifatal){
  820. ewake = 1;
  821. dprint("Fatal\n");
  822. }
  823. if(cause & Adhrs){
  824. if(p->task & 33){
  825. dprint("Adhrs cause = %ux; serr = %ux; task=%ux\n",
  826. cause, serr, p->task);
  827. d->portm.flag |= Ferror;
  828. ewake = 1;
  829. }
  830. pr = 0;
  831. }
  832. if(p->task & 1 && last != cause)
  833. dprint("err ca %ux serr %ux task %ux sstat %ux\n",
  834. cause, serr, p->task, p->sstatus);
  835. if(pr)
  836. dprint("%s: upd %ux ta %ux\n", name, cause, p->task);
  837. if(cause & (Aprcs|Aifs)){
  838. s0 = d->state;
  839. switch(p->sstatus & 7){
  840. case 0: /* no device */
  841. d->state = Dmissing;
  842. break;
  843. case 1: /* device but no phy comm. */
  844. if((p->sstatus & 0xF00) == 0x600)
  845. d->state = Dnew; /* slumbering */
  846. else
  847. d->state = Derror;
  848. break;
  849. case 3: /* device & phy comm. estab. */
  850. /* power mgnt crap for suprise removal */
  851. p->ie |= Aprcs|Apcs; /* is this required? */
  852. d->state = Dreset;
  853. break;
  854. case 4: /* phy off-line */
  855. d->state = Doffline;
  856. break;
  857. }
  858. dprint("%s: %s → %s [Apcrs] %ux\n", name, diskstates[s0],
  859. diskstates[d->state], p->sstatus);
  860. /* print pulled message here. */
  861. if(s0 == Dready && d->state != Dready)
  862. idprint("%s: pulled\n", name);
  863. if(d->state != Dready)
  864. d->portm.flag |= Ferror;
  865. ewake = 1;
  866. }
  867. p->serror = serr;
  868. if(ewake){
  869. clearci(p);
  870. wakeup(&d->portm);
  871. }
  872. last = cause;
  873. }
  874. static void
  875. pstatus(Drive *d, ulong s)
  876. {
  877. /*
  878. * bogus code because the first interrupt is currently dropped.
  879. * likely my fault. serror is maybe cleared at the wrong time.
  880. */
  881. switch(s){
  882. case 0: /* no device */
  883. d->state = Dmissing;
  884. break;
  885. case 1: /* device but no phy. comm. */
  886. break;
  887. case 2: /* should this be missing? need testcase. */
  888. dprint("pstatus 2\n");
  889. /* fallthrough */
  890. case 3: /* device & phy. comm. */
  891. d->wait = 0;
  892. d->state = Dnew;
  893. break;
  894. case 4: /* offline */
  895. d->state = Doffline;
  896. break;
  897. case 6: /* ? not sure this makes sense. TODO */
  898. d->state = Dnew;
  899. break;
  900. }
  901. }
  902. static int
  903. configdrive(Drive *d)
  904. {
  905. if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1)
  906. return -1;
  907. ilock(d);
  908. pstatus(d, d->port->sstatus & 7);
  909. iunlock(d);
  910. return 0;
  911. }
  912. static void
  913. resetdisk(Drive *d)
  914. {
  915. uint state, det, stat;
  916. Aport *p;
  917. p = d->port;
  918. det = p->sctl & 7;
  919. stat = p->sstatus & 7;
  920. state = (p->cmd>>28) & 0xf;
  921. dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat);
  922. if(stat != 3){ /* device absent or phy not communicating? */
  923. ilock(d);
  924. d->state = Dportreset;
  925. iunlock(d);
  926. return;
  927. }
  928. ilock(d);
  929. state = d->state;
  930. if(d->state != Dready || d->state != Dnew)
  931. d->portm.flag |= Ferror;
  932. clearci(p); /* satisfy sleep condition. */
  933. wakeup(&d->portm);
  934. iunlock(d);
  935. qlock(&d->portm);
  936. if(p->cmd&Ast && ahciswreset(&d->portc) == -1){
  937. ilock(d);
  938. d->state = Dportreset; /* get a bigger stick. */
  939. iunlock(d);
  940. } else {
  941. ilock(d);
  942. d->state = Dmissing;
  943. iunlock(d);
  944. configdrive(d);
  945. }
  946. dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]);
  947. qunlock(&d->portm);
  948. }
  949. static int
  950. newdrive(Drive *d)
  951. {
  952. char *name, *s;
  953. Aportc *c;
  954. Aportm *m;
  955. c = &d->portc;
  956. m = &d->portm;
  957. name = d->unit->name;
  958. if(name == 0)
  959. name = "??";
  960. if(d->port->task == 0x80)
  961. return -1;
  962. qlock(c->m);
  963. if(setudmamode(c, 5) == -1){
  964. dprint("%s: can't set udma mode\n", name);
  965. goto lose;
  966. }
  967. if(identify(d) == -1){
  968. dprint("%s: identify failure\n", name);
  969. goto lose;
  970. }
  971. if(m->feat & Dpower && setfeatures(c, 0x85) == -1){
  972. m->feat &= ~Dpower;
  973. if(ahcirecover(c) == -1)
  974. goto lose;
  975. }
  976. ilock(d);
  977. d->state = Dready;
  978. iunlock(d);
  979. qunlock(c->m);
  980. s = "";
  981. if(m->feat & Dllba)
  982. s = "L";
  983. idprint("%s: %sLBA %,lld sectors\n", d->unit->name, s, d->sectors);
  984. idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial,
  985. d->mediachange?"[mediachange]":"");
  986. return 0;
  987. lose:
  988. qunlock(c->m);
  989. return -1;
  990. }
  991. enum {
  992. Nms = 256,
  993. Mphywait = 2*1024/Nms - 1,
  994. Midwait = 16*1024/Nms - 1,
  995. Mcomrwait = 64*1024/Nms - 1,
  996. };
  997. static void
  998. westerndigitalhung(Drive *d)
  999. {
  1000. if((d->portm.feat&Datapi) == 0 && d->active &&
  1001. TK2MS(MACHP(0)->ticks-d->intick) > 5000){
  1002. dprint("%s: drive hung; resetting [%ux] ci=%x\n",
  1003. d->unit->name, d->port->task, d->port->ci);
  1004. d->state = Dreset;
  1005. }
  1006. }
  1007. static ushort olds[NCtlr*NCtlrdrv];
  1008. static int
  1009. doportreset(Drive *d)
  1010. {
  1011. int i;
  1012. i = -1;
  1013. qlock(&d->portm);
  1014. if(ahciportreset(&d->portc) == -1)
  1015. dprint("ahciportreset fails\n");
  1016. else
  1017. i = 0;
  1018. qunlock(&d->portm);
  1019. dprint("portreset → %s [task %ux]\n",
  1020. diskstates[d->state], d->port->task);
  1021. return i;
  1022. }
  1023. static void
  1024. checkdrive(Drive *d, int i)
  1025. {
  1026. ushort s;
  1027. char *name;
  1028. ilock(d);
  1029. name = d->unit->name;
  1030. s = d->port->sstatus;
  1031. if(s != olds[i]){
  1032. dprint("%s: status: %04ux -> %04ux: %s\n",
  1033. name, olds[i], s, diskstates[d->state]);
  1034. olds[i] = s;
  1035. d->wait = 0;
  1036. }
  1037. westerndigitalhung(d);
  1038. switch(d->state){
  1039. case Dnull:
  1040. case Dready:
  1041. break;
  1042. case Dmissing:
  1043. case Dnew:
  1044. switch(s & 0x107){
  1045. case 1: /* no device (pm), device but no phy. comm. */
  1046. ahciwakeup(d->port);
  1047. /* fall through */
  1048. case 0: /* no device */
  1049. break;
  1050. default:
  1051. dprint("%s: unknown status %04ux\n", name, s);
  1052. /* fall through */
  1053. case 0x100: /* active, no device */
  1054. if(++d->wait&Mphywait)
  1055. break;
  1056. reset:
  1057. if(++d->mode > DMsataii)
  1058. d->mode = 0;
  1059. if(d->mode == DMsatai){ /* we tried everything */
  1060. d->state = Dportreset;
  1061. goto portreset;
  1062. }
  1063. dprint("%s: reset; new mode %s\n", name,
  1064. modename[d->mode]);
  1065. iunlock(d);
  1066. resetdisk(d);
  1067. ilock(d);
  1068. break;
  1069. case 0x103: /* active, device, phy. comm. */
  1070. if((++d->wait&Midwait) == 0){
  1071. dprint("%s: slow reset %04ux task=%ux; %d\n",
  1072. name, s, d->port->task, d->wait);
  1073. goto reset;
  1074. }
  1075. s = (uchar)d->port->task;
  1076. if(s == 0x7f || ((d->port->sig >> 16) != 0xeb14 &&
  1077. (s & ~0x17) != (1<<6)))
  1078. break;
  1079. iunlock(d);
  1080. newdrive(d);
  1081. ilock(d);
  1082. break;
  1083. }
  1084. break;
  1085. case Doffline:
  1086. if(d->wait++ & Mcomrwait)
  1087. break;
  1088. /* fallthrough */
  1089. case Derror:
  1090. case Dreset:
  1091. dprint("%s: reset [%s]: mode %d; status %04ux\n",
  1092. name, diskstates[d->state], d->mode, s);
  1093. iunlock(d);
  1094. resetdisk(d);
  1095. ilock(d);
  1096. break;
  1097. case Dportreset:
  1098. portreset:
  1099. if(d->wait++ & 0xff && (s & 0x100) == 0)
  1100. break;
  1101. /* device is active */
  1102. dprint("%s: portreset [%s]: mode %d; status %04ux\n",
  1103. name, diskstates[d->state], d->mode, s);
  1104. d->portm.flag |= Ferror;
  1105. clearci(d->port);
  1106. wakeup(&d->portm);
  1107. if((s & 7) == 0){ /* no device */
  1108. d->state = Dmissing;
  1109. break;
  1110. }
  1111. iunlock(d);
  1112. doportreset(d);
  1113. ilock(d);
  1114. break;
  1115. }
  1116. iunlock(d);
  1117. }
  1118. static void
  1119. satakproc(void*)
  1120. {
  1121. int i;
  1122. memset(olds, 0xff, sizeof olds);
  1123. for(;;){
  1124. tsleep(&up->sleep, return0, 0, Nms);
  1125. for(i = 0; i < niadrive; i++)
  1126. checkdrive(iadrive[i], i);
  1127. }
  1128. }
  1129. static void
  1130. iainterrupt(Ureg*, void *a)
  1131. {
  1132. int i;
  1133. ulong cause, m;
  1134. Ctlr *c;
  1135. Drive *d;
  1136. c = a;
  1137. ilock(c);
  1138. cause = c->hba->isr;
  1139. for(i = 0; i < c->ndrive; i++){
  1140. m = 1 << i;
  1141. if((cause & m) == 0)
  1142. continue;
  1143. d = c->rawdrive + i;
  1144. ilock(d);
  1145. if(d->port->isr && c->hba->pi & m)
  1146. updatedrive(d);
  1147. c->hba->isr = m;
  1148. iunlock(d);
  1149. }
  1150. iunlock(c);
  1151. }
  1152. static int
  1153. iaverify(SDunit *u)
  1154. {
  1155. Ctlr *c;
  1156. Drive *d;
  1157. c = u->dev->ctlr;
  1158. d = c->drive[u->subno];
  1159. ilock(c);
  1160. ilock(d);
  1161. d->unit = u;
  1162. iunlock(d);
  1163. iunlock(c);
  1164. return 1;
  1165. }
  1166. static int
  1167. iaenable(SDev *s)
  1168. {
  1169. char name[32];
  1170. Ctlr *c;
  1171. static int once;
  1172. c = s->ctlr;
  1173. ilock(c);
  1174. if(!c->enabled) {
  1175. if(once == 0) {
  1176. once = 1;
  1177. kproc("iasata", satakproc, 0);
  1178. }
  1179. if(c->ndrive == 0)
  1180. panic("iaenable: zero s->ctlr->ndrive");
  1181. pcisetbme(c->pci);
  1182. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1183. intrenable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1184. /* supposed to squelch leftover interrupts here. */
  1185. ahcienable(c->hba);
  1186. c->enabled = 1;
  1187. }
  1188. iunlock(c);
  1189. return 1;
  1190. }
  1191. static int
  1192. iadisable(SDev *s)
  1193. {
  1194. char name[32];
  1195. Ctlr *c;
  1196. c = s->ctlr;
  1197. ilock(c);
  1198. ahcidisable(c->hba);
  1199. snprint(name, sizeof name, "%s (%s)", s->name, s->ifc->name);
  1200. intrdisable(c->pci->intl, iainterrupt, c, c->pci->tbdf, name);
  1201. c->enabled = 0;
  1202. iunlock(c);
  1203. return 1;
  1204. }
  1205. static int
  1206. iaonline(SDunit *unit)
  1207. {
  1208. int r;
  1209. Ctlr *c;
  1210. Drive *d;
  1211. c = unit->dev->ctlr;
  1212. d = c->drive[unit->subno];
  1213. r = 0;
  1214. if(d->portm.feat & Datapi && d->mediachange){
  1215. r = scsionline(unit);
  1216. if(r > 0)
  1217. d->mediachange = 0;
  1218. return r;
  1219. }
  1220. ilock(d);
  1221. if(d->mediachange){
  1222. r = 2;
  1223. d->mediachange = 0;
  1224. /* devsd resets this after online is called; why? */
  1225. unit->sectors = d->sectors;
  1226. unit->secsize = 512;
  1227. } else if(d->state == Dready)
  1228. r = 1;
  1229. iunlock(d);
  1230. return r;
  1231. }
  1232. /* returns locked list! */
  1233. static Alist*
  1234. ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba)
  1235. {
  1236. uchar *c, acmd, dir, llba;
  1237. Alist *l;
  1238. Actab *t;
  1239. Aprdt *p;
  1240. static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35, };
  1241. dir = *cmd != 0x28;
  1242. llba = m->feat&Dllba? 1: 0;
  1243. acmd = tab[dir][llba];
  1244. qlock(m);
  1245. l = m->list;
  1246. t = m->ctab;
  1247. c = t->cfis;
  1248. c[0] = 0x27;
  1249. c[1] = 0x80;
  1250. c[2] = acmd;
  1251. c[3] = 0;
  1252. c[4] = lba; /* sector lba low 7:0 */
  1253. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1254. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1255. c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */
  1256. if(llba == 0)
  1257. c[7] |= (lba>>24) & 7;
  1258. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1259. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1260. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1261. c[11] = 0; /* features (exp); */
  1262. c[12] = n; /* sector count */
  1263. c[13] = n >> 8; /* sector count (exp) */
  1264. c[14] = 0; /* r */
  1265. c[15] = 0; /* control */
  1266. *(ulong*)(c + 16) = 0;
  1267. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1268. if(dir == Write)
  1269. l->flags |= Lwrite;
  1270. l->len = 0;
  1271. l->ctab = PCIWADDR(t);
  1272. l->ctabhi = 0;
  1273. p = &t->prdt;
  1274. p->dba = PCIWADDR(data);
  1275. p->dbahi = 0;
  1276. p->count = 1<<31 | (512*n - 2) | 1;
  1277. return l;
  1278. }
  1279. static Alist*
  1280. ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n)
  1281. {
  1282. int fill, len;
  1283. uchar *c;
  1284. Alist *l;
  1285. Actab *t;
  1286. Aprdt *p;
  1287. qlock(m);
  1288. l = m->list;
  1289. t = m->ctab;
  1290. c = t->cfis;
  1291. fill = m->feat&Datapi16? 16: 12;
  1292. if((len = r->clen) > fill)
  1293. len = fill;
  1294. memmove(t->atapi, r->cmd, len);
  1295. memset(t->atapi+len, 0, fill-len);
  1296. c[0] = 0x27;
  1297. c[1] = 0x80;
  1298. c[2] = 0xa0;
  1299. if(n != 0)
  1300. c[3] = 1; /* dma */
  1301. else
  1302. c[3] = 0; /* features (exp); */
  1303. c[4] = 0; /* sector lba low 7:0 */
  1304. c[5] = n; /* cylinder low lba mid 15:8 */
  1305. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1306. c[7] = 0xa0; /* obsolete device bits */
  1307. *(ulong*)(c + 8) = 0;
  1308. *(ulong*)(c + 12) = 0;
  1309. *(ulong*)(c + 16) = 0;
  1310. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1311. if(r->write != 0 && data)
  1312. l->flags |= Lwrite;
  1313. l->len = 0;
  1314. l->ctab = PCIWADDR(t);
  1315. l->ctabhi = 0;
  1316. if(data == 0)
  1317. return l;
  1318. p = &t->prdt;
  1319. p->dba = PCIWADDR(data);
  1320. p->dbahi = 0;
  1321. p->count = 1<<31 | (n - 2) | 1;
  1322. return l;
  1323. }
  1324. static int
  1325. waitready(Drive *d)
  1326. {
  1327. u32int s, t, i;
  1328. for(i = 0; i < 120; i++){
  1329. ilock(d);
  1330. s = d->port->sstatus;
  1331. t = d->port->task;
  1332. iunlock(d);
  1333. if((s & 0x100) == 0)
  1334. return -1; /* not active */
  1335. if(d->state == Dready && (s & 7) == 3)
  1336. return 0; /* ready, present & phy. comm. */
  1337. if((i+1) % 30 == 0)
  1338. print("%s: waitready: [%s] task=%ux sstat=%ux\n",
  1339. d->unit->name, diskstates[d->state], t, s);
  1340. esleep(1000);
  1341. }
  1342. print("%s: not responding; offline\n", d->unit->name);
  1343. ilock(d);
  1344. d->state = Doffline;
  1345. iunlock(d);
  1346. return -1;
  1347. }
  1348. static int
  1349. iariopkt(SDreq *r, Drive *d)
  1350. {
  1351. int n, count, try, max, flag, task;
  1352. char *name;
  1353. uchar *cmd, *data;
  1354. Aport *p;
  1355. Asleep as;
  1356. cmd = r->cmd;
  1357. name = d->unit->name;
  1358. p = d->port;
  1359. aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write],
  1360. r->dlen, r->data);
  1361. if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1362. return sdmodesense(r, cmd, d->info, sizeof d->info);
  1363. r->rlen = 0;
  1364. count = r->dlen;
  1365. max = 65536;
  1366. try = 0;
  1367. retry:
  1368. if(waitready(d) == -1)
  1369. return SDeio;
  1370. data = r->data;
  1371. n = count;
  1372. if(n > max)
  1373. n = max;
  1374. d->active++;
  1375. ahcibuildpkt(&d->portm, r, data, n);
  1376. ilock(d);
  1377. d->portm.flag = 0;
  1378. iunlock(d);
  1379. p->ci = 1;
  1380. as.p = p;
  1381. as.i = 1;
  1382. d->intick = MACHP(0)->ticks;
  1383. while(waserror())
  1384. ;
  1385. sleep(&d->portm, ahciclear, &as);
  1386. poperror();
  1387. ilock(d);
  1388. flag = d->portm.flag;
  1389. task = d->port->task;
  1390. iunlock(d);
  1391. if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){
  1392. d->port->ci = 0; /* @? */
  1393. ahcirecover(&d->portc);
  1394. task = d->port->task;
  1395. }
  1396. d->active--;
  1397. qunlock(&d->portm);
  1398. if(flag == 0){
  1399. if(++try == 10){
  1400. print("%s: bad disk\n", name);
  1401. r->status = SDcheck;
  1402. return SDcheck;
  1403. }
  1404. iprint("%s: retry\n", name);
  1405. esleep(1000);
  1406. goto retry;
  1407. }
  1408. if(flag & Ferror){
  1409. iprint("%s: i/o error %ux\n", name, task);
  1410. r->status = SDcheck;
  1411. return SDcheck;
  1412. }
  1413. data += n;
  1414. r->rlen = data - (uchar*)r->data;
  1415. r->status = SDok;
  1416. return SDok;
  1417. }
  1418. static int
  1419. iario(SDreq *r)
  1420. {
  1421. int i, n, count, try, max, flag, task;
  1422. vlong lba;
  1423. char *name;
  1424. uchar *cmd, *data;
  1425. Aport *p;
  1426. Asleep as;
  1427. Ctlr *c;
  1428. Drive *d;
  1429. SDunit *unit;
  1430. unit = r->unit;
  1431. c = unit->dev->ctlr;
  1432. d = c->drive[unit->subno];
  1433. if(d->portm.feat & Datapi)
  1434. return iariopkt(r, d);
  1435. cmd = r->cmd;
  1436. name = d->unit->name;
  1437. p = d->port;
  1438. if(r->cmd[0] == 0x35 || r->cmd[0] == 0x91){
  1439. qlock(&d->portm);
  1440. i = flushcache(&d->portc);
  1441. qunlock(&d->portm);
  1442. if(i == 0)
  1443. return sdsetsense(r, SDok, 0, 0, 0);
  1444. return sdsetsense(r, SDcheck, 3, 0xc, 2);
  1445. }
  1446. if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){
  1447. r->status = i;
  1448. return i;
  1449. }
  1450. if(*cmd != 0x28 && *cmd != 0x2a){
  1451. print("%s: bad cmd 0x%.2ux\n", name, cmd[0]);
  1452. r->status = SDcheck;
  1453. return SDcheck;
  1454. }
  1455. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1456. count = cmd[7]<<8 | cmd[8];
  1457. if(r->data == nil)
  1458. return SDok;
  1459. if(r->dlen < count * unit->secsize)
  1460. count = r->dlen / unit->secsize;
  1461. max = 128;
  1462. try = 0;
  1463. retry:
  1464. if(waitready(d) == -1)
  1465. return SDeio;
  1466. data = r->data;
  1467. while(count > 0){
  1468. n = count;
  1469. if(n > max)
  1470. n = max;
  1471. d->active++;
  1472. ahcibuild(&d->portm, cmd, data, n, lba);
  1473. ilock(d);
  1474. d->portm.flag = 0;
  1475. iunlock(d);
  1476. p->ci = 1;
  1477. as.p = p;
  1478. as.i = 1;
  1479. d->intick = MACHP(0)->ticks;
  1480. while(waserror())
  1481. ;
  1482. sleep(&d->portm, ahciclear, &as);
  1483. poperror();
  1484. ilock(d);
  1485. flag = d->portm.flag;
  1486. task = d->port->task;
  1487. iunlock(d);
  1488. if(task & (Efatal<<8) ||
  1489. task & (ASbsy|ASdrq) && d->state == Dready){
  1490. d->port->ci = 0; /* @? */
  1491. ahcirecover(&d->portc);
  1492. task = d->port->task;
  1493. }
  1494. d->active--;
  1495. qunlock(&d->portm);
  1496. if(flag == 0){
  1497. if(++try == 10){
  1498. print("%s: bad disk\n", name);
  1499. r->status = SDeio;
  1500. return SDeio;
  1501. }
  1502. iprint("%s: retry %lld\n", name, lba);
  1503. esleep(1000);
  1504. goto retry;
  1505. }
  1506. if(flag & Ferror){
  1507. iprint("%s: i/o error %ux @%,lld\n", name, task, lba);
  1508. r->status = SDeio;
  1509. return SDeio;
  1510. }
  1511. count -= n;
  1512. lba += n;
  1513. data += n * unit->secsize;
  1514. }
  1515. r->rlen = data - (uchar*)r->data;
  1516. r->status = SDok;
  1517. return SDok;
  1518. }
  1519. /*
  1520. * configure drives 0-5 as ahci sata (c.f. errata)
  1521. */
  1522. static int
  1523. iaahcimode(Pcidev *p)
  1524. {
  1525. dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91), pcicfgr8(p, 92),
  1526. pcicfgr8(p, 93));
  1527. pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */
  1528. // pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */
  1529. return 0;
  1530. }
  1531. static void
  1532. iasetupahci(Ctlr *c)
  1533. {
  1534. /* disable cmd block decoding. */
  1535. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1536. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1537. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1538. c->lmmio[0xc/4] = (1 << 6) - 1; /* 5 ports. (supposedly ro pi reg.) */
  1539. /* enable ahci mode; from ich9 datasheet */
  1540. pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5);
  1541. }
  1542. static SDev*
  1543. iapnp(void)
  1544. {
  1545. int i, n, nunit, type;
  1546. ulong io;
  1547. Ctlr *c;
  1548. Drive *d;
  1549. Pcidev *p;
  1550. SDev *head, *tail, *s;
  1551. static int done;
  1552. if(done++)
  1553. return nil;
  1554. p = nil;
  1555. head = tail = nil;
  1556. loop:
  1557. while((p = pcimatch(p, 0, 0)) != nil){
  1558. if(p->vid == 0x8086 && (p->did & 0xfffc) == 0x2680)
  1559. type = Tesb;
  1560. else if(p->vid == 0x8086 && (p->did & 0xfffe) == 0x27c4)
  1561. type = Tich; /* 82801g[bh]m */
  1562. else if(p->vid == 0x1002 && p->did == 0x4380)
  1563. type = Tsb600;
  1564. else
  1565. continue;
  1566. if (p->mem[Abar].bar == 0)
  1567. continue;
  1568. if(niactlr == NCtlr){
  1569. print("%spnp: too many controllers\n", tname[type]);
  1570. break;
  1571. }
  1572. c = iactlr + niactlr;
  1573. s = sdevs + niactlr;
  1574. memset(c, 0, sizeof *c);
  1575. memset(s, 0, sizeof *s);
  1576. io = p->mem[Abar].bar & ~0xf;
  1577. c->mmio = vmap(io, p->mem[Abar].size);
  1578. if(c->mmio == 0){
  1579. print("%s: address 0x%luX in use did=%x\n",
  1580. Tname(c), io, p->did);
  1581. continue;
  1582. }
  1583. c->lmmio = (ulong*)c->mmio;
  1584. c->pci = p;
  1585. c->type = type;
  1586. s->ifc = &sdiahciifc;
  1587. s->idno = 'E' + niactlr;
  1588. s->ctlr = c;
  1589. c->sdev = s;
  1590. if(Intel(c->type) && p->did != 0x2681)
  1591. iasetupahci(c);
  1592. nunit = ahciconf(c);
  1593. // ahcihbareset((Ahba*)c->mmio);
  1594. if(Intel(c->type) && iaahcimode(p) == -1)
  1595. break;
  1596. if(nunit < 1){
  1597. vunmap(c->mmio, p->mem[Abar].size);
  1598. continue;
  1599. }
  1600. c->ndrive = s->nunit = nunit;
  1601. i = (c->hba->cap >> 21) & 1;
  1602. print("#S/sd%c: %s: sata-%s with %d ports\n", s->idno,
  1603. Tname(c), "I\0II" + i*2, nunit);
  1604. /* map the drives -- they don't all need to be enabled. */
  1605. memset(c->rawdrive, 0, sizeof c->rawdrive);
  1606. n = 0;
  1607. for(i = 0; i < NCtlrdrv; i++) {
  1608. d = c->rawdrive + i;
  1609. d->portno = i;
  1610. d->driveno = -1;
  1611. d->sectors = 0;
  1612. d->ctlr = c;
  1613. if((c->hba->pi & (1<<i)) == 0)
  1614. continue;
  1615. d->port = (Aport*)(c->mmio + 0x80*i + 0x100);
  1616. d->portc.p = d->port;
  1617. d->portc.m = &d->portm;
  1618. d->driveno = n++;
  1619. c->drive[i] = d;
  1620. iadrive[d->driveno] = d;
  1621. }
  1622. for(i = 0; i < n; i++)
  1623. if(ahciidle(c->drive[i]->port) == -1){
  1624. dprint("%s: port %d wedged; abort\n",
  1625. Tname(c), i);
  1626. goto loop;
  1627. }
  1628. for(i = 0; i < n; i++){
  1629. c->drive[i]->mode = DMsatai;
  1630. configdrive(c->drive[i]);
  1631. }
  1632. niadrive += nunit;
  1633. niactlr++;
  1634. if(head)
  1635. tail->next = s;
  1636. else
  1637. head = s;
  1638. tail = s;
  1639. }
  1640. return head;
  1641. }
  1642. static char* smarttab[] = {
  1643. "unset",
  1644. "error",
  1645. "threshold exceeded",
  1646. "normal"
  1647. };
  1648. static char *
  1649. pflag(char *s, char *e, uchar f)
  1650. {
  1651. uchar i;
  1652. for(i = 0; i < 8; i++)
  1653. if(f & (1 << i))
  1654. s = seprint(s, e, "%s ", flagname[i]);
  1655. return seprint(s, e, "\n");
  1656. }
  1657. static int
  1658. iarctl(SDunit *u, char *p, int l)
  1659. {
  1660. char buf[32];
  1661. char *e, *op;
  1662. Aport *o;
  1663. Ctlr *c;
  1664. Drive *d;
  1665. if((c = u->dev->ctlr) == nil)
  1666. return 0;
  1667. d = c->drive[u->subno];
  1668. o = d->port;
  1669. e = p+l;
  1670. op = p;
  1671. if(d->state == Dready){
  1672. p = seprint(p, e, "model\t%s\n", d->model);
  1673. p = seprint(p, e, "serial\t%s\n", d->serial);
  1674. p = seprint(p, e, "firm\t%s\n", d->firmware);
  1675. if(d->smartrs == 0xff)
  1676. p = seprint(p, e, "smart\tenable error\n");
  1677. else if(d->smartrs == 0)
  1678. p = seprint(p, e, "smart\tdisabled\n");
  1679. else
  1680. p = seprint(p, e, "smart\t%s\n",
  1681. smarttab[d->portm.smart]);
  1682. p = seprint(p, e, "flag\t");
  1683. p = pflag(p, e, d->portm.feat);
  1684. }else
  1685. p = seprint(p, e, "no disk present [%s]\n", diskstates[d->state]);
  1686. serrstr(o->serror, buf, buf + sizeof buf - 1);
  1687. p = seprint(p, e, "reg\ttask %ux cmd %ux serr %ux %s ci %ux is %ux; "
  1688. "sig %ux sstatus %04x\n", o->task, o->cmd, o->serror, buf,
  1689. o->ci, o->isr, o->sig, o->sstatus);
  1690. p = seprint(p, e, "geometry %llud 512\n", d->sectors);
  1691. return p - op;
  1692. }
  1693. static void
  1694. runflushcache(Drive *d)
  1695. {
  1696. long t0;
  1697. t0 = MACHP(0)->ticks;
  1698. qlock(&d->portm);
  1699. flushcache(&d->portc);
  1700. qunlock(&d->portm);
  1701. dprint("flush in %ldms\n", TK2MS(MACHP(0)->ticks-t0));
  1702. }
  1703. static void
  1704. forcemode(Drive *d, char *mode)
  1705. {
  1706. int i;
  1707. for(i = 0; i < nelem(modename); i++)
  1708. if(strcmp(mode, modename[i]) == 0)
  1709. break;
  1710. if(i == nelem(modename))
  1711. i = 0;
  1712. ilock(d);
  1713. d->mode = i;
  1714. iunlock(d);
  1715. }
  1716. static void
  1717. runsmartable(Drive *d, int i)
  1718. {
  1719. if(waserror()){
  1720. qunlock(&d->portm);
  1721. d->smartrs = 0;
  1722. nexterror();
  1723. }
  1724. qlock(&d->portm);
  1725. d->smartrs = smart(&d->portc, i);
  1726. d->portm.smart = 0;
  1727. qunlock(&d->portm);
  1728. poperror();
  1729. }
  1730. static void
  1731. forcestate(Drive *d, char *state)
  1732. {
  1733. int i;
  1734. for(i = 0; i < nelem(diskstates); i++)
  1735. if(strcmp(state, diskstates[i]) == 0)
  1736. break;
  1737. if(i == nelem(diskstates))
  1738. i = 0;
  1739. ilock(d);
  1740. d->state = i;
  1741. if(i == Dnull){
  1742. d->mediachange = 1;
  1743. if(d->unit)
  1744. d->unit->sectors = 0; /* force disk to disappear. */
  1745. }
  1746. iunlock(d);
  1747. }
  1748. static int
  1749. iawctl(SDunit *u, Cmdbuf *cmd)
  1750. {
  1751. char **f;
  1752. Ctlr *c;
  1753. Drive *d;
  1754. c = u->dev->ctlr;
  1755. d = c->drive[u->subno];
  1756. f = cmd->f;
  1757. if(strcmp(f[0], "flushcache") == 0)
  1758. runflushcache(d);
  1759. else if(strcmp(f[0], "identify") == 0){
  1760. uint i;
  1761. i = strtoul(f[1]? f[1]: "0", 0, 0);
  1762. if(i > 0xff)
  1763. i = 0;
  1764. dprint("%04d %ux\n", i, d->info[i]);
  1765. }else if(strcmp(f[0], "mode") == 0)
  1766. forcemode(d, f[1]? f[1]: "satai");
  1767. else if(strcmp(f[0], "nop") == 0){
  1768. if((d->portm.feat & Dnop) == 0){
  1769. cmderror(cmd, "nop command not supported");
  1770. return -1;
  1771. }
  1772. if(waserror()){
  1773. qunlock(&d->portm);
  1774. nexterror();
  1775. }
  1776. qlock(&d->portm);
  1777. nop(&d->portc);
  1778. qunlock(&d->portm);
  1779. poperror();
  1780. }else if(strcmp(f[0], "reset") == 0)
  1781. forcestate(d, "reset");
  1782. else if(strcmp(f[0], "smart") == 0){
  1783. if(d->smartrs == 0){
  1784. cmderror(cmd, "smart not enabled");
  1785. return -1;
  1786. }
  1787. if(waserror()){
  1788. qunlock(&d->portm);
  1789. d->smartrs = 0;
  1790. nexterror();
  1791. }
  1792. qlock(&d->portm);
  1793. d->portm.smart = 2 + smartrs(&d->portc);
  1794. qunlock(&d->portm);
  1795. poperror();
  1796. }else if(strcmp(f[0], "smartdisable") == 0)
  1797. runsmartable(d, 1);
  1798. else if(strcmp(f[0], "smartenable") == 0)
  1799. runsmartable(d, 0);
  1800. else if(strcmp(f[0], "state") == 0)
  1801. forcestate(d, f[1]? f[1]: "null");
  1802. else{
  1803. cmderror(cmd, Ebadctl);
  1804. return -1;
  1805. }
  1806. return 0;
  1807. }
  1808. static char *
  1809. portr(char *p, char *e, uint x)
  1810. {
  1811. int i, a;
  1812. p[0] = 0;
  1813. a = -1;
  1814. for(i = 0; i < 32; i++){
  1815. if((x & (1<<i)) == 0){
  1816. if(a != -1 && i - 1 != a)
  1817. p = seprint(p, e, "-%d", i - 1);
  1818. a = -1;
  1819. continue;
  1820. }
  1821. if(a == -1){
  1822. if(i > 0)
  1823. p = seprint(p, e, ", ");
  1824. p = seprint(p, e, "%d", a = i);
  1825. }
  1826. }
  1827. if(a != -1 && i - 1 != a)
  1828. p = seprint(p, e, "-%d", i - 1);
  1829. return p;
  1830. }
  1831. /* must emit exactly one line per controller (sd(3)) */
  1832. static char*
  1833. iartopctl(SDev *sdev, char *p, char *e)
  1834. {
  1835. u32int cap;
  1836. char pr[25];
  1837. Ahba *hba;
  1838. Ctlr *ctlr;
  1839. #define has(x, str) if(cap & (x)) p = seprint(p, e, "%s ", (str))
  1840. ctlr = sdev->ctlr;
  1841. hba = ctlr->hba;
  1842. p = seprint(p, e, "sd%c ahci port %#p: ", sdev->idno, hba);
  1843. cap = hba->cap;
  1844. has(Hs64a, "64a");
  1845. has(Hsalp, "alp");
  1846. has(Hsam, "am");
  1847. has(Hsclo, "clo");
  1848. has(Hcccs, "coal");
  1849. has(Hems, "ems");
  1850. has(Hsal, "led");
  1851. has(Hsmps, "mps");
  1852. has(Hsncq, "ncq");
  1853. has(Hssntf, "ntf");
  1854. has(Hspm, "pm");
  1855. has(Hpsc, "pslum");
  1856. has(Hssc, "slum");
  1857. has(Hsss, "ss");
  1858. has(Hsxs, "sxs");
  1859. portr(pr, pr + sizeof pr, hba->pi);
  1860. return seprint(p, e,
  1861. "iss %d ncs %d np %d; ghc %ux isr %ux pi %ux %s ver %ux\n",
  1862. (cap>>20) & 0xf, (cap>>8) & 0x1f, 1 + (cap & 0x1f),
  1863. hba->ghc, hba->isr, hba->pi, pr, hba->ver);
  1864. #undef has
  1865. }
  1866. static int
  1867. iawtopctl(SDev *, Cmdbuf *cmd)
  1868. {
  1869. int *v;
  1870. char **f;
  1871. f = cmd->f;
  1872. v = 0;
  1873. if(strcmp(f[0], "debug") == 0)
  1874. v = &debug;
  1875. else if(strcmp(f[0], "idprint") == 0)
  1876. v = &prid;
  1877. else if(strcmp(f[0], "aprint") == 0)
  1878. v = &datapi;
  1879. else
  1880. cmderror(cmd, Ebadctl);
  1881. switch(cmd->nf){
  1882. default:
  1883. cmderror(cmd, Ebadarg);
  1884. case 1:
  1885. *v ^= 1;
  1886. break;
  1887. case 2:
  1888. *v = (strcmp(f[1], "on") == 0);
  1889. break;
  1890. }
  1891. return 0;
  1892. }
  1893. SDifc sdiahciifc = {
  1894. "iahci",
  1895. iapnp,
  1896. nil, /* legacy */
  1897. iaenable,
  1898. iadisable,
  1899. iaverify,
  1900. iaonline,
  1901. iario,
  1902. iarctl,
  1903. iawctl,
  1904. scsibio,
  1905. nil, /* probe */
  1906. nil, /* clear */
  1907. iartopctl,
  1908. iawtopctl,
  1909. };