sdiahci.c 26 KB

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  1. /*
  2. * intel 63[12]xesb ahci (advanced host controller interface)
  3. * bootstrap sata controller driver
  4. * copyright © 2007 coraid, inc.
  5. */
  6. #include "u.h"
  7. #include "lib.h"
  8. #include "mem.h"
  9. #include "dat.h"
  10. #include "fns.h"
  11. #include "io.h"
  12. #include "error.h"
  13. #include "sd.h"
  14. #include "ahci.h"
  15. #define dprint(...) if(debug == 1) print(__VA_ARGS__); else USED(debug)
  16. #define idprint(...) if(prid == 1) print(__VA_ARGS__); else USED(prid)
  17. #define aprint(...) if(datapi == 1) print(__VA_ARGS__); else USED(datapi);
  18. enum {
  19. NCtlr = 2,
  20. NCtlrdrv= 8,
  21. NDrive = NCtlr*NCtlrdrv,
  22. Read = 0,
  23. Write
  24. };
  25. /* pci space configurtion */
  26. enum {
  27. Pmap = 0x90,
  28. Ppcs = 0x91,
  29. Prev = 0xa8,
  30. };
  31. enum {
  32. Dnull,
  33. Dmissing,
  34. Dnew,
  35. Dready,
  36. Derror,
  37. Dreset,
  38. Doffline,
  39. Dportreset,
  40. Dlast
  41. };
  42. static char *diskstates[Dlast] = {
  43. "null",
  44. "missing",
  45. "new",
  46. "ready",
  47. "error",
  48. "reset",
  49. "offline",
  50. "portreset",
  51. };
  52. extern SDifc sdiahciifc;
  53. typedef struct Ctlr Ctlr;
  54. enum {
  55. DMautoneg,
  56. DMsatai,
  57. DMsataii,
  58. };
  59. static char *modename[] = {
  60. "auto",
  61. "satai",
  62. "sataii",
  63. };
  64. static char *flagname[] = {
  65. "llba",
  66. "smart",
  67. "power",
  68. "nop",
  69. "atapi",
  70. "atapi16",
  71. };
  72. typedef struct {
  73. Lock;
  74. Ctlr *ctlr;
  75. SDunit *unit;
  76. char name[10];
  77. Aport *port;
  78. Aportm portm;
  79. Aportc portc; /* redundant ptr to port and portm. */
  80. uchar mediachange;
  81. uchar state;
  82. uchar smartrs;
  83. uvlong sectors;
  84. ulong intick;
  85. int wait;
  86. uchar mode; /* DMautoneg, satai or sataii. */
  87. uchar active;
  88. char serial[20+1];
  89. char firmware[8+1];
  90. char model[40+1];
  91. ushort info[0x200];
  92. int driveno; /* ctlr*NCtlrdrv + unit */
  93. int portno; /* ctlr port # != drive # when not all ports enabled. */
  94. } Drive;
  95. struct Ctlr {
  96. Lock;
  97. int irq;
  98. int tbdf;
  99. int enabled;
  100. SDev *sdev;
  101. Pcidev *pci;
  102. uchar *mmio;
  103. ulong *lmmio;
  104. Ahba *hba;
  105. Drive rawdrive[NCtlrdrv];
  106. Drive* drive[NCtlrdrv];
  107. int ndrive;
  108. };
  109. static Ctlr iactlr[NCtlr];
  110. static SDev sdevs[NCtlr];
  111. static int niactlr;
  112. static Drive *iadrive[NDrive];
  113. static int niadrive;
  114. static int prid = 0;
  115. static int datapi = 0;
  116. static char stab[] = {
  117. [0] 'i', 'm',
  118. [8] 't', 'c', 'p', 'e',
  119. [16] 'N', 'I', 'W', 'B', 'D', 'C', 'H', 'S', 'T', 'F', 'X'
  120. };
  121. static void
  122. serrstr(ulong r, char *s, char *e)
  123. {
  124. int i;
  125. e -= 3;
  126. for(i = 0; i < nelem(stab) && s < e; i++)
  127. if((r & (1<<i)) && stab[i]){
  128. *s++ = stab[i];
  129. if(SerrBad & (1<<i))
  130. *s++ = '*';
  131. }
  132. *s = 0;
  133. }
  134. static char ntab[] = "0123456789abcdef";
  135. static void
  136. preg(uchar *reg, int n)
  137. {
  138. int i;
  139. char buf[25*3+1], *e;
  140. e = buf;
  141. for(i = 0; i < n; i++){
  142. *e++ = ntab[reg[i]>>4];
  143. *e++ = ntab[reg[i]&0xf];
  144. *e++ = ' ';
  145. }
  146. *e++ = '\n';
  147. *e = 0;
  148. dprint(buf);
  149. }
  150. static void
  151. dreg(char *s, Aport *p)
  152. {
  153. dprint("%stask=%ux; cmd=%ux; ci=%ux; is=%ux\n",
  154. s, p->task, p->cmd, p->ci, p->isr);
  155. }
  156. static void
  157. esleep(int ms)
  158. {
  159. delay(ms);
  160. }
  161. typedef struct {
  162. Aport *p;
  163. int i;
  164. } Asleep;
  165. static int
  166. ahciclear(void *v)
  167. {
  168. Asleep *s;
  169. s = v;
  170. return (s->p->ci & s->i) == 0;
  171. }
  172. static void
  173. aesleep(Aportm *, Asleep *a, int ms)
  174. {
  175. ulong start;
  176. start = m->ticks;
  177. while((a->p->ci & a->i) != 0)
  178. if(TK2MS(m->ticks-start) >= ms)
  179. break;
  180. }
  181. static int
  182. ahciwait(Aportc *c, int ms)
  183. {
  184. Asleep as;
  185. Aport *p;
  186. p = c->p;
  187. p->ci = 1;
  188. as.p = p;
  189. as.i = 1;
  190. aesleep(c->m, &as, ms);
  191. if((p->task&1) == 0 && p->ci == 0)
  192. return 0;
  193. dreg("ahciwait timeout ", c->p);
  194. return -1;
  195. }
  196. static int
  197. nop(Aportc *pc)
  198. {
  199. uchar *c;
  200. Actab *t;
  201. Alist *l;
  202. if((pc->m->feat&Dnop) == 0)
  203. return -1;
  204. t = pc->m->ctab;
  205. c = t->cfis;
  206. memset(c, 0, 0x20);
  207. c[0] = 0x27;
  208. c[1] = 0x80;
  209. c[2] = 0x00;
  210. c[7] = 0xa0; /* obsolete device bits */
  211. l = pc->m->list;
  212. l->flags = Lwrite | 0x5;
  213. l->len = 0;
  214. l->ctab = PCIWADDR(t);
  215. l->ctabhi = 0;
  216. return ahciwait(pc, 3*1000);
  217. }
  218. static int
  219. setfeatures(Aportc *pc, uchar f)
  220. {
  221. uchar *c;
  222. Actab *t;
  223. Alist *l;
  224. t = pc->m->ctab;
  225. c = t->cfis;
  226. memset(c, 0, 0x20);
  227. c[0] = 0x27;
  228. c[1] = 0x80;
  229. c[2] = 0xef;
  230. c[3] = f;
  231. c[7] = 0xa0; /* obsolete device bits */
  232. l = pc->m->list;
  233. l->flags = Lwrite | 0x5;
  234. l->len = 0;
  235. l->ctab = PCIWADDR(t);
  236. l->ctabhi = 0;
  237. return ahciwait(pc, 3*1000);
  238. }
  239. static int
  240. setudmamode(Aportc *pc, uchar f)
  241. {
  242. uchar *c;
  243. Actab *t;
  244. Alist *l;
  245. t = pc->m->ctab;
  246. c = t->cfis;
  247. memset(c, 0, 0x20);
  248. c[0] = 0x27;
  249. c[1] = 0x80;
  250. c[2] = 0xef;
  251. c[3] = 3; /* set transfer mode */
  252. c[7] = 0xa0; /* obsolete device bits */
  253. c[12] = 0x40 | f; /* sector count */
  254. l = pc->m->list;
  255. l->flags = Lwrite | 0x5;
  256. l->len = 0;
  257. l->ctab = PCIWADDR(t);
  258. l->ctabhi = 0;
  259. return ahciwait(pc, 3*1000);
  260. }
  261. static void
  262. asleep(int ms)
  263. {
  264. delay(ms);
  265. }
  266. static int
  267. ahciportreset(Aportc *c)
  268. {
  269. u32int *cmd, i;
  270. Aport *p;
  271. p = c->p;
  272. cmd = &p->cmd;
  273. *cmd &= ~(Afre|Ast);
  274. for(i = 0; i < 500; i += 25){
  275. if((*cmd & Acr) == 0)
  276. break;
  277. asleep(25);
  278. }
  279. p->sctl = 1 | (p->sctl & ~7);
  280. delay(1);
  281. p->sctl &= ~7;
  282. return 0;
  283. }
  284. static ushort
  285. gbit16(void *a)
  286. {
  287. uchar *i;
  288. i = a;
  289. return i[1]<<8 | i[0];
  290. }
  291. static u32int
  292. gbit32(void *a)
  293. {
  294. u32int j;
  295. uchar *i;
  296. i = a;
  297. j = i[3] << 24;
  298. j |= i[2] << 16;
  299. j |= i[1] << 8;
  300. j |= i[0];
  301. return j;
  302. }
  303. static uvlong
  304. gbit64(void *a)
  305. {
  306. uchar *i;
  307. i = a;
  308. return (uvlong)gbit32(i+4)<<32 | gbit32(a);
  309. }
  310. static int
  311. ahciidentify0(Aportc *pc, void *id, int atapi)
  312. {
  313. uchar *c;
  314. Actab *t;
  315. Alist *l;
  316. Aprdt *p;
  317. static uchar tab[] = { 0xec, 0xa1 };
  318. t = pc->m->ctab;
  319. c = t->cfis;
  320. memset(c, 0, 0x20);
  321. c[0] = 0x27;
  322. c[1] = 0x80;
  323. c[2] = tab[atapi];
  324. c[7] = 0xa0; /* obsolete device bits */
  325. l = pc->m->list;
  326. l->flags = 1<<16 | 0x5;
  327. l->len = 0;
  328. l->ctab = PCIWADDR(t);
  329. l->ctabhi = 0;
  330. memset(id, 0, 0x100);
  331. p = &t->prdt;
  332. p->dba = PCIWADDR(id);
  333. p->dbahi = 0;
  334. p->count = 1<<31 | (0x200-2) | 1;
  335. return ahciwait(pc, 3*1000);
  336. }
  337. static vlong
  338. ahciidentify(Aportc *pc, ushort *id)
  339. {
  340. int i, sig;
  341. vlong s;
  342. Aportm *m;
  343. m = pc->m;
  344. m->feat = 0;
  345. m->smart = 0;
  346. i = 0;
  347. sig = pc->p->sig >> 16;
  348. if(sig == 0xeb14){
  349. m->feat |= Datapi;
  350. i = 1;
  351. }
  352. if(ahciidentify0(pc, id, i) == -1)
  353. return -1;
  354. i = gbit16(id+83) | gbit16(id+86);
  355. if(i & (1<<10)){
  356. m->feat |= Dllba;
  357. s = gbit64(id+100);
  358. }else
  359. s = gbit32(id+60);
  360. if(m->feat&Datapi){
  361. i = gbit16(id+0);
  362. if(i & 1)
  363. m->feat |= Datapi16;
  364. }
  365. i = gbit16(id+83);
  366. if((i>>14) != 1)
  367. return s;
  368. if(i & (1<<3))
  369. m->feat |= Dpower;
  370. i = gbit16(id+82);
  371. if(i & 1)
  372. m->feat |= Dsmart;
  373. if(i & (1<<14))
  374. m->feat |= Dnop;
  375. return s;
  376. }
  377. static int
  378. ahciquiet(Aport *a)
  379. {
  380. u32int *p, i;
  381. p = &a->cmd;
  382. *p &= ~Ast;
  383. for(i = 0; i < 500; i += 50){
  384. if((*p & Acr) == 0)
  385. goto stop;
  386. asleep(50);
  387. }
  388. return -1;
  389. stop:
  390. if((a->task & (ASdrq|ASbsy)) == 0){
  391. *p |= Ast;
  392. return 0;
  393. }
  394. *p |= Aclo;
  395. for(i = 0; i < 500; i += 50){
  396. if((*p & Aclo) == 0)
  397. goto stop1;
  398. asleep(50);
  399. }
  400. return -1;
  401. stop1:
  402. /* extra check */
  403. dprint("clo clear %x\n", a->task);
  404. if(a->task&ASbsy)
  405. return -1;
  406. *p |= Ast;
  407. return 0;
  408. }
  409. static int
  410. ahciidle(Aport *port)
  411. {
  412. u32int *p, i, r;
  413. p = &port->cmd;
  414. if((*p & Arun) == 0)
  415. return 0;
  416. *p &= ~Ast;
  417. r = 0;
  418. for(i = 0; i < 500; i += 25){
  419. if((*p & Acr) == 0)
  420. goto stop;
  421. asleep(25);
  422. }
  423. r = -1;
  424. stop:
  425. if((*p & Afre) == 0)
  426. return r;
  427. *p &= ~Afre;
  428. for(i = 0; i < 500; i += 25){
  429. if((*p & Afre) == 0)
  430. return 0;
  431. asleep(25);
  432. }
  433. return -1;
  434. }
  435. /*
  436. * § 6.2.2.1 first part; comreset handled by reset disk.
  437. * - remainder is handled by configdisk.
  438. * - ahcirecover is a quick recovery from a failed command.
  439. */
  440. int
  441. ahciswreset(Aportc *pc)
  442. {
  443. int i;
  444. i = ahciidle(pc->p);
  445. pc->p->cmd |= Afre;
  446. if(i == -1)
  447. return -1;
  448. if(pc->p->task & (ASdrq|ASbsy))
  449. return -1;
  450. return 0;
  451. }
  452. int
  453. ahcirecover(Aportc *pc)
  454. {
  455. ahciswreset(pc);
  456. pc->p->cmd |= Ast;
  457. if(setudmamode(pc, 5) == -1)
  458. return -1;
  459. return 0;
  460. }
  461. static void*
  462. malign(int size, int align)
  463. {
  464. void *v;
  465. v = xspanalloc(size, align, 0);
  466. memset(v, 0, size);
  467. return v;
  468. }
  469. static void
  470. setupfis(Afis *f)
  471. {
  472. f->base = malign(0x100, 0x100);
  473. f->d = f->base + 0;
  474. f->p = f->base + 0x20;
  475. f->r = f->base + 0x40;
  476. f->u = f->base + 0x60;
  477. f->devicebits = (u32int*)(f->base + 0x58);
  478. }
  479. static int
  480. ahciconfigdrive(Ahba *h, Aportc *c, int mode)
  481. {
  482. Aportm *m;
  483. Aport *p;
  484. p = c->p;
  485. m = c->m;
  486. if(m->list == 0){
  487. setupfis(&m->fis);
  488. m->list = malign(sizeof *m->list, 1024);
  489. m->ctab = malign(sizeof *m->ctab, 128);
  490. }
  491. if(p->sstatus & 3 && h->cap & Hsss){
  492. dprint("configdrive: spinning up ... [%ux]\n", p->sstatus);
  493. p->cmd |= Apod|Asud;
  494. asleep(1400);
  495. }
  496. p->serror = SerrAll;
  497. p->list = PCIWADDR(m->list);
  498. p->listhi = 0;
  499. p->fis = PCIWADDR(m->fis.base);
  500. p->fishi = 0;
  501. p->cmd |= Afre | Ast;
  502. /* disable power managment sequence from book. */
  503. p->sctl = (3*Aipm) | (mode*Aspd) | (0*Adet);
  504. p->cmd &= ~Aalpe;
  505. p->ie = IEM;
  506. return 0;
  507. }
  508. static int
  509. ahcienable(Ahba *h)
  510. {
  511. h->ghc |= Hie;
  512. return 0;
  513. }
  514. static int
  515. ahcidisable(Ahba *h)
  516. {
  517. h->ghc &= ~Hie;
  518. return 0;
  519. }
  520. static int
  521. countbits(ulong u)
  522. {
  523. int i, n;
  524. n = 0;
  525. for(i = 0; i < 32; i++)
  526. if(u & (1<<i))
  527. n++;
  528. return n;
  529. }
  530. static int
  531. ahciconf(Ctlr *c)
  532. {
  533. u32int u;
  534. Ahba *h;
  535. static int count;
  536. h = c->hba = (Ahba*)c->mmio;
  537. u = h->cap;
  538. if((u&Hsam) == 0)
  539. h->ghc |= Hae;
  540. print("ahci%d port %#p: hba sss %d; ncs %d; coal %d; mports %d; "
  541. "led %d; clo %d; ems %d;\n", count++, h,
  542. (u>>27) & 1, (u>>8) & 0x1f, (u>>7) & 1, u & 0x1f, (u>>25) & 1,
  543. (u>>24) & 1, (u>>6) & 1);
  544. return countbits(h->pi);
  545. }
  546. static int
  547. ahcihbareset(Ahba *h)
  548. {
  549. int wait;
  550. h->ghc |= 1;
  551. for(wait = 0; wait < 1000; wait += 100){
  552. if(h->ghc == 0)
  553. return 0;
  554. delay(100);
  555. }
  556. return -1;
  557. }
  558. static void
  559. idmove(char *p, ushort *a, int n)
  560. {
  561. int i;
  562. char *op, *e;
  563. op = p;
  564. for(i = 0; i < n/2; i++){
  565. *p++ = a[i] >> 8;
  566. *p++ = a[i];
  567. }
  568. *p = 0;
  569. while(p > op && *--p == ' ')
  570. *p = 0;
  571. e = p;
  572. p = op;
  573. while(*p == ' ')
  574. p++;
  575. memmove(op, p, n - (e - p));
  576. }
  577. static int
  578. identify(Drive *d)
  579. {
  580. u16int *id;
  581. vlong osectors, s;
  582. uchar oserial[21];
  583. SDunit *u;
  584. id = d->info;
  585. s = ahciidentify(&d->portc, id);
  586. if(s == -1){
  587. d->state = Derror;
  588. return -1;
  589. }
  590. osectors = d->sectors;
  591. memmove(oserial, d->serial, sizeof d->serial);
  592. d->sectors = s;
  593. d->smartrs = 0;
  594. idmove(d->serial, id+10, 20);
  595. idmove(d->firmware, id+23, 8);
  596. idmove(d->model, id+27, 40);
  597. u = d->unit;
  598. memset(u->inquiry, 0, sizeof u->inquiry);
  599. u->inquiry[2] = 2;
  600. u->inquiry[3] = 2;
  601. u->inquiry[4] = sizeof u->inquiry - 4;
  602. memmove(u->inquiry+8, d->model, 40);
  603. if((osectors == 0 || osectors != s) &&
  604. memcmp(oserial, d->serial, sizeof oserial) != 0){
  605. d->mediachange = 1;
  606. u->sectors = 0;
  607. }
  608. return 0;
  609. }
  610. static void
  611. clearci(Aport *p)
  612. {
  613. if((p->cmd & Ast) == 0)
  614. return;
  615. p->cmd &= ~Ast;
  616. p->cmd |= Ast;
  617. }
  618. static void
  619. updatedrive(Drive *d)
  620. {
  621. u32int cause, serr, s0, pr, ewake;
  622. char *name;
  623. Aport *p;
  624. static u32int last;
  625. pr = 1;
  626. ewake = 0;
  627. p = d->port;
  628. cause = p->isr;
  629. serr = p->serror;
  630. p->isr = cause;
  631. name = "??";
  632. if(d->unit && d->unit->name)
  633. name = d->unit->name;
  634. if(p->ci == 0){
  635. d->portm.flag |= Fdone;
  636. pr = 0;
  637. } else if(cause&Adps)
  638. pr = 0;
  639. if(cause&Ifatal){
  640. ewake = 1;
  641. dprint("Fatal\n");
  642. }
  643. if(cause&Adhrs){
  644. if(p->task&33){
  645. dprint("Adhrs cause = %ux; serr = %ux; task=%ux\n",
  646. cause, serr, p->task);
  647. d->portm.flag |= Ferror;
  648. ewake = 1;
  649. }
  650. pr = 0;
  651. }
  652. if(pr)
  653. dprint("%s: upd %ux ta %ux\n", name, cause, p->task);
  654. if(cause & (Aprcs|Aifs)){
  655. s0 = d->state;
  656. switch(p->sstatus & 7){
  657. case 0:
  658. d->state = Dmissing;
  659. break;
  660. case 1:
  661. d->state = Derror;
  662. break;
  663. case 3:
  664. /* power mgmt crap for surprise removal */
  665. p->ie |= Aprcs|Apcs; /* is this required? */
  666. d->state = Dreset;
  667. break;
  668. case 4:
  669. d->state = Doffline;
  670. break;
  671. }
  672. dprint("%s: %s → %s [Apcrs] %ux\n", name, diskstates[s0],
  673. diskstates[d->state], p->sstatus);
  674. /* print pulled message here. */
  675. if(s0 == Dready && d->state != Dready)
  676. idprint("%s: pulled\n", name);
  677. if(d->state != Dready)
  678. d->portm.flag |= Ferror;
  679. ewake = 1;
  680. }
  681. p->serror = serr;
  682. if(ewake)
  683. clearci(p);
  684. last = cause;
  685. }
  686. static void
  687. pstatus(Drive *d, ulong s)
  688. {
  689. /*
  690. * bogus code because the first interrupt is currently dropped.
  691. * likely my fault. serror may be cleared at the wrong time.
  692. */
  693. switch(s){
  694. case 0:
  695. d->state = Dmissing;
  696. break;
  697. case 2: /* should this be missing? need testcase. */
  698. dprint("pstatus 2\n");
  699. case 3:
  700. d->wait = 0;
  701. d->state = Dnew;
  702. break;
  703. case 4:
  704. d->state = Doffline;
  705. break;
  706. }
  707. }
  708. static int
  709. configdrive(Drive *d)
  710. {
  711. if(ahciconfigdrive(d->ctlr->hba, &d->portc, d->mode) == -1)
  712. return -1;
  713. ilock(d);
  714. pstatus(d, d->port->sstatus & 7);
  715. iunlock(d);
  716. return 0;
  717. }
  718. static void
  719. resetdisk(Drive *d)
  720. {
  721. uint state, det, stat;
  722. Aport *p;
  723. p = d->port;
  724. det = p->sctl & 7;
  725. stat = p->sstatus & 7;
  726. state = (p->cmd>>28) & 0xf;
  727. dprint("resetdisk: icc %ux det %d sdet %d\n", state, det, stat);
  728. if(stat != 3){
  729. ilock(d);
  730. d->state = Dportreset;
  731. iunlock(d);
  732. return;
  733. }
  734. ilock(d);
  735. state = d->state;
  736. if(d->state != Dready || d->state != Dnew)
  737. d->portm.flag |= Ferror;
  738. clearci(p); /* satisfy sleep condition. */
  739. iunlock(d);
  740. qlock(&d->portm);
  741. if(p->cmd & Ast && ahciswreset(&d->portc) == -1){
  742. ilock(d);
  743. d->state = Dportreset; /* get a bigger stick. */
  744. iunlock(d);
  745. } else {
  746. ilock(d);
  747. d->state = Dmissing;
  748. iunlock(d);
  749. configdrive(d);
  750. }
  751. dprint("resetdisk: %s → %s\n", diskstates[state], diskstates[d->state]);
  752. qunlock(&d->portm);
  753. }
  754. static int
  755. newdrive(Drive *d)
  756. {
  757. char *name, *s;
  758. Aportc *c;
  759. Aportm *m;
  760. c = &d->portc;
  761. m = &d->portm;
  762. name = d->unit->name;
  763. if(name == 0)
  764. name = "??";
  765. if(d->port->task == 0x80)
  766. return -1;
  767. qlock(c->m);
  768. if(setudmamode(c, 5) == -1){
  769. dprint("%s: can't set udma mode\n", name);
  770. goto lose;
  771. }
  772. if(identify(d) == -1){
  773. dprint("%s: identify failure\n", name);
  774. goto lose;
  775. }
  776. if(m->feat & Dpower && setfeatures(c, 0x85) == -1){
  777. m->feat &= ~Dpower;
  778. if(ahcirecover(c) == -1)
  779. goto lose;
  780. }
  781. ilock(d);
  782. d->state = Dready;
  783. iunlock(d);
  784. qunlock(c->m);
  785. s = "";
  786. if(m->feat & Dllba)
  787. s = "L";
  788. idprint("%s: %sLBA %lld sectors\n", d->unit->name, s, d->sectors);
  789. idprint(" %s %s %s %s\n", d->model, d->firmware, d->serial,
  790. d->mediachange?"[mediachange]":"");
  791. return 0;
  792. lose:
  793. qunlock(&d->portm);
  794. return -1;
  795. }
  796. enum {
  797. Nms = 256,
  798. Mphywait = 2*1024/Nms-1,
  799. Midwait = 16*1024/Nms-1,
  800. Mcomrwait = 64*1024/Nms-1,
  801. };
  802. static void
  803. westerndigitalhung(Drive *d)
  804. {
  805. if((d->portm.feat&Datapi) == 0 && d->active &&
  806. TK2MS(m->ticks-d->intick) > 5000){
  807. dprint("%s: drive hung; resetting [%ux] ci=%x\n", d->unit->name,
  808. d->port->task, d->port->ci);
  809. d->state = Dreset;
  810. }
  811. }
  812. static ushort olds[NCtlr*NCtlrdrv];
  813. static int
  814. doportreset(Drive *d)
  815. {
  816. int i;
  817. i = -1;
  818. qlock(&d->portm);
  819. if(ahciportreset(&d->portc) == -1)
  820. dprint("ahciportreset fails\n");
  821. else
  822. i = 0;
  823. qunlock(&d->portm);
  824. dprint("portreset → %s [task %ux]\n", diskstates[d->state],
  825. d->port->task);
  826. return i;
  827. }
  828. static void
  829. checkdrive(Drive *d, int i)
  830. {
  831. ushort s;
  832. char *name;
  833. ilock(d);
  834. name = d->unit->name;
  835. s = d->port->sstatus;
  836. if(s != olds[i]){
  837. dprint("%s: status: %04ux -> %04ux: %s\n", name, olds[i],
  838. s, diskstates[d->state]);
  839. olds[i] = s;
  840. d->wait = 0;
  841. }
  842. westerndigitalhung(d);
  843. switch(d->state){
  844. case Dnull:
  845. case Dready:
  846. break;
  847. case Dmissing:
  848. case Dnew:
  849. switch(s & 0x107){
  850. case 0:
  851. case 1:
  852. break;
  853. default:
  854. dprint("%s: unknown status %04ux\n", name, s);
  855. case 0x100:
  856. if(++d->wait&Mphywait)
  857. break;
  858. reset:
  859. if(++d->mode > DMsataii)
  860. d->mode = 0;
  861. if(d->mode == DMsatai){ /* we tried everything */
  862. d->state = Dportreset;
  863. goto portreset;
  864. }
  865. dprint("%s: reset; new mode %s\n", name,
  866. modename[d->mode]);
  867. iunlock(d);
  868. resetdisk(d);
  869. ilock(d);
  870. break;
  871. case 0x103:
  872. if((++d->wait&Midwait) == 0){
  873. dprint("%s: slow reset %04ux task=%ux; %d\n",
  874. name, s, d->port->task, d->wait);
  875. goto reset;
  876. }
  877. s = d->port->task&0xff;
  878. if(s == 0x7f || ((d->port->sig>>16) != 0xeb14 &&
  879. (s & ~0x17) != (1<<6)))
  880. break;
  881. iunlock(d);
  882. newdrive(d);
  883. ilock(d);
  884. break;
  885. }
  886. break;
  887. case Doffline:
  888. if(d->wait++&Mcomrwait)
  889. break;
  890. case Derror:
  891. case Dreset:
  892. dprint("%s: reset [%s]: mode %d; status %04ux\n",
  893. name, diskstates[d->state], d->mode, s);
  894. iunlock(d);
  895. resetdisk(d);
  896. ilock(d);
  897. break;
  898. case Dportreset:
  899. portreset:
  900. if(d->wait++ & 0xff && (s & 0x100) == 0)
  901. break;
  902. dprint("%s: portreset [%s]: mode %d; status %04ux\n",
  903. name, diskstates[d->state], d->mode, s);
  904. d->portm.flag |= Ferror;
  905. clearci(d->port);
  906. if((s & 7) == 0){
  907. d->state = Dmissing;
  908. break;
  909. }
  910. iunlock(d);
  911. doportreset(d);
  912. ilock(d);
  913. break;
  914. }
  915. iunlock(d);
  916. }
  917. static void
  918. iainterrupt(Ureg*, void *a)
  919. {
  920. int i;
  921. ulong cause, m;
  922. Ctlr *c;
  923. Drive *d;
  924. c = a;
  925. ilock(c);
  926. /* check drive here! */
  927. cause = c->hba->isr;
  928. for(i = 0; i < c->ndrive; i++){
  929. m = 1 << i;
  930. if((cause & m) == 0)
  931. continue;
  932. d = c->rawdrive + i;
  933. ilock(d);
  934. if(d->port->isr && c->hba->pi & m)
  935. updatedrive(d);
  936. c->hba->isr = m;
  937. iunlock(d);
  938. }
  939. iunlock(c);
  940. }
  941. static int
  942. iaverify(SDunit *u)
  943. {
  944. Ctlr *c;
  945. Drive *d;
  946. c = u->dev->ctlr;
  947. d = c->drive[u->subno];
  948. ilock(c);
  949. ilock(d);
  950. d->unit = u;
  951. iunlock(d);
  952. iunlock(c);
  953. checkdrive(d, d->driveno);
  954. return 1;
  955. }
  956. static int
  957. iaenable(SDev *s)
  958. {
  959. Ctlr *c;
  960. c = s->ctlr;
  961. ilock(c);
  962. if(!c->enabled) {
  963. if(c->ndrive == 0)
  964. panic("iaenable: zero s->ctlr->ndrive");
  965. pcisetbme(c->pci);
  966. setvec(c->irq + VectorPIC, iainterrupt, c);
  967. /* supposed to squelch leftover interrupts here. */
  968. ahcienable(c->hba);
  969. c->enabled = 1;
  970. }
  971. iunlock(c);
  972. return 1;
  973. }
  974. static int
  975. iadisable(SDev *s)
  976. {
  977. Ctlr *c;
  978. c = s->ctlr;
  979. ilock(c);
  980. ahcidisable(c->hba);
  981. // intrdisable(c->irq, iainterrupt, c, c->tbdf, name);
  982. c->enabled = 0;
  983. iunlock(c);
  984. return 1;
  985. }
  986. static int
  987. iaonline(SDunit *unit)
  988. {
  989. Ctlr *c;
  990. Drive *d;
  991. int r;
  992. c = unit->dev->ctlr;
  993. d = c->drive[unit->subno];
  994. r = 0;
  995. if(d->portm.feat & Datapi && d->mediachange){
  996. r = scsionline(unit);
  997. if(r > 0)
  998. d->mediachange = 0;
  999. return r;
  1000. }
  1001. ilock(d);
  1002. if(d->mediachange){
  1003. r = 2;
  1004. d->mediachange = 0;
  1005. /* devsd rests this after online is called; why? */
  1006. unit->sectors = d->sectors;
  1007. unit->secsize = 512;
  1008. } else if(d->state == Dready)
  1009. r = 1;
  1010. iunlock(d);
  1011. return r;
  1012. }
  1013. /* returns locked list! */
  1014. static Alist*
  1015. ahcibuild(Aportm *m, uchar *cmd, void *data, int n, vlong lba)
  1016. {
  1017. uchar *c, acmd, dir, llba;
  1018. Alist *l;
  1019. Actab *t;
  1020. Aprdt *p;
  1021. static uchar tab[2][2] = { 0xc8, 0x25, 0xca, 0x35 };
  1022. dir = *cmd != 0x28;
  1023. llba = m->feat&Dllba? 1: 0;
  1024. acmd = tab[dir][llba];
  1025. qlock(m);
  1026. l = m->list;
  1027. t = m->ctab;
  1028. c = t->cfis;
  1029. c[0] = 0x27;
  1030. c[1] = 0x80;
  1031. c[2] = acmd;
  1032. c[3] = 0;
  1033. c[4] = lba; /* sector lba low 7:0 */
  1034. c[5] = lba >> 8; /* cylinder low lba mid 15:8 */
  1035. c[6] = lba >> 16; /* cylinder hi lba hi 23:16 */
  1036. c[7] = 0xa0 | 0x40; /* obsolete device bits + lba */
  1037. if(llba == 0)
  1038. c[7] |= (lba>>24) & 7;
  1039. c[8] = lba >> 24; /* sector (exp) lba 31:24 */
  1040. c[9] = lba >> 32; /* cylinder low (exp) lba 39:32 */
  1041. c[10] = lba >> 48; /* cylinder hi (exp) lba 48:40 */
  1042. c[11] = 0; /* features (exp); */
  1043. c[12] = n; /* sector count */
  1044. c[13] = n >> 8; /* sector count (exp) */
  1045. c[14] = 0; /* r */
  1046. c[15] = 0; /* control */
  1047. *(ulong*)(c+16) = 0;
  1048. l->flags = 1<<16 | Lpref | 0x5; /* Lpref ?? */
  1049. if(dir == Write)
  1050. l->flags |= Lwrite;
  1051. l->len = 0;
  1052. l->ctab = PCIWADDR(t);
  1053. l->ctabhi = 0;
  1054. p = &t->prdt;
  1055. p->dba = PCIWADDR(data);
  1056. p->dbahi = 0;
  1057. p->count = 1<<31 | (512*n - 2) | 1;
  1058. return l;
  1059. }
  1060. static Alist*
  1061. ahcibuildpkt(Aportm *m, SDreq *r, void *data, int n)
  1062. {
  1063. int fill, len;
  1064. uchar *c;
  1065. Actab *t;
  1066. Alist *l;
  1067. Aprdt *p;
  1068. qlock(m);
  1069. l = m->list;
  1070. t = m->ctab;
  1071. c = t->cfis;
  1072. fill = m->feat&Datapi16? 16: 12;
  1073. if((len = r->clen) > fill)
  1074. len = fill;
  1075. memmove(t->atapi, r->cmd, len);
  1076. memset(t->atapi + len, 0, fill - len);
  1077. c[0] = 0x27;
  1078. c[1] = 0x80;
  1079. c[2] = 0xa0;
  1080. if(n != 0)
  1081. c[3] = 1; /* dma */
  1082. else
  1083. c[3] = 0; /* features (exp); */
  1084. c[4] = 0; /* sector lba low 7:0 */
  1085. c[5] = n; /* cylinder low lba mid 15:8 */
  1086. c[6] = n >> 8; /* cylinder hi lba hi 23:16 */
  1087. c[7] = 0xa0; /* obsolete device bits */
  1088. *(ulong*)(c+8) = 0;
  1089. *(ulong*)(c+12) = 0;
  1090. *(ulong*)(c+16) = 0;
  1091. l->flags = 1<<16 | Lpref | Latapi | 0x5;
  1092. if(r->write != 0 && data)
  1093. l->flags |= Lwrite;
  1094. l->len = 0;
  1095. l->ctab = PCIWADDR(t);
  1096. l->ctabhi = 0;
  1097. if(data == 0)
  1098. return l;
  1099. p = &t->prdt;
  1100. p->dba = PCIWADDR(data);
  1101. p->dbahi = 0;
  1102. p->count = 1<<31 | (n - 2) | 1;
  1103. return l;
  1104. }
  1105. static int
  1106. waitready(Drive *d)
  1107. {
  1108. u32int s, t, i;
  1109. for(i = 0; i < 120; i++){
  1110. ilock(d);
  1111. s = d->port->sstatus;
  1112. t = d->port->task;
  1113. iunlock(d);
  1114. if((s & 0x100) == 0)
  1115. return -1;
  1116. if(d->state == Dready && (s & 7) == 3)
  1117. return 0;
  1118. if((i+1) % 30 == 0)
  1119. print("%s: waitready: [%s] task=%ux sstat=%ux\n",
  1120. d->unit->name, diskstates[d->state], t, s);
  1121. esleep(1000);
  1122. }
  1123. print("%s: not responding; offline\n", d->unit->name);
  1124. ilock(d);
  1125. d->state = Doffline;
  1126. iunlock(d);
  1127. return -1;
  1128. }
  1129. static int
  1130. iariopkt(SDreq *r, Drive *d)
  1131. {
  1132. int n, count, try, max, flag, task;
  1133. char *name;
  1134. uchar *cmd, *data;
  1135. Aport *p;
  1136. Asleep as;
  1137. cmd = r->cmd;
  1138. name = d->unit->name;
  1139. p = d->port;
  1140. aprint("%02ux %02ux %c %d %p\n", cmd[0], cmd[2], "rw"[r->write],
  1141. r->dlen, r->data);
  1142. // if(cmd[0] == 0x5a && (cmd[2] & 0x3f) == 0x3f)
  1143. // return sdmodesense(r, cmd, d->info, sizeof d->info);
  1144. r->rlen = 0;
  1145. count = r->dlen;
  1146. max = 65536;
  1147. try = 0;
  1148. retry:
  1149. if(waitready(d) == -1)
  1150. return SDeio;
  1151. data = r->data;
  1152. n = count;
  1153. if(n > max)
  1154. n = max;
  1155. d->active++;
  1156. ahcibuildpkt(&d->portm, r, data, n);
  1157. ilock(d);
  1158. d->portm.flag = 0;
  1159. iunlock(d);
  1160. p->ci = 1;
  1161. as.p = p;
  1162. as.i = 1;
  1163. d->intick = m->ticks;
  1164. while(ahciclear(&as) == 0)
  1165. ;
  1166. ilock(d);
  1167. flag = d->portm.flag;
  1168. task = d->port->task;
  1169. iunlock(d);
  1170. if(task & (Efatal<<8) || task & (ASbsy|ASdrq) && d->state == Dready){
  1171. d->port->ci = 0; /* @? */
  1172. ahcirecover(&d->portc);
  1173. task = d->port->task;
  1174. }
  1175. d->active--;
  1176. qunlock(&d->portm);
  1177. if(flag == 0){
  1178. if(++try == 10){
  1179. print("%s: bad disk\n", name);
  1180. r->status = SDcheck;
  1181. return SDcheck;
  1182. }
  1183. print("%s: retry\n", name);
  1184. esleep(1000);
  1185. goto retry;
  1186. }
  1187. if(flag & Ferror){
  1188. print("%s: i/o error %ux\n", name, task);
  1189. r->status = SDcheck;
  1190. return SDcheck;
  1191. }
  1192. data += n;
  1193. r->rlen = data - (uchar*)r->data;
  1194. r->status = SDok;
  1195. return SDok;
  1196. }
  1197. static int
  1198. iario(SDreq *r)
  1199. {
  1200. int n, count, max, flag, task;
  1201. vlong lba;
  1202. char *name;
  1203. uchar *cmd, *data;
  1204. Aport *p;
  1205. Asleep as;
  1206. Ctlr *c;
  1207. Drive *d;
  1208. SDunit *unit;
  1209. unit = r->unit;
  1210. c = unit->dev->ctlr;
  1211. d = c->drive[unit->subno];
  1212. if(d->portm.feat & Datapi)
  1213. return iariopkt(r, d);
  1214. cmd = r->cmd;
  1215. name = d->unit->name;
  1216. p = d->port;
  1217. // if((i = sdfakescsi(r, d->info, sizeof d->info)) != SDnostatus){
  1218. // r->status = i;
  1219. // return i;
  1220. // }
  1221. if(*cmd != 0x28 && *cmd != 0x2a){
  1222. print("%s: bad cmd 0x%.2ux\n", name, cmd[0]);
  1223. r->status = SDcheck;
  1224. return SDcheck;
  1225. }
  1226. lba = cmd[2]<<24 | cmd[3]<<16 | cmd[4]<<8 | cmd[5];
  1227. count = cmd[7]<<8 | cmd[8];
  1228. if(r->data == nil)
  1229. return SDok;
  1230. if(r->dlen < count*unit->secsize)
  1231. count = r->dlen/unit->secsize;
  1232. max = 128;
  1233. if(waitready(d) == -1)
  1234. return SDeio;
  1235. data = r->data;
  1236. while(count > 0){
  1237. n = count;
  1238. if(n > max)
  1239. n = max;
  1240. d->active++;
  1241. ahcibuild(&d->portm, cmd, data, n, lba);
  1242. ilock(d);
  1243. d->portm.flag = 0;
  1244. iunlock(d);
  1245. p->ci = 1;
  1246. as.p = p;
  1247. as.i = 1;
  1248. d->intick = m->ticks;
  1249. while(ahciclear(&as) == 0)
  1250. ;
  1251. ilock(d);
  1252. flag = d->portm.flag;
  1253. task = d->port->task;
  1254. iunlock(d);
  1255. if(task & (Efatal<<8) ||
  1256. task & (ASbsy|ASdrq) && d->state == Dready){
  1257. d->port->ci = 0; /* @? */
  1258. ahcirecover(&d->portc);
  1259. task = d->port->task;
  1260. }
  1261. d->active--;
  1262. qunlock(&d->portm);
  1263. if(flag == 0 || flag & Ferror){
  1264. print("%s: i/o error %ux @%lld\n", name, task, lba);
  1265. r->status = SDeio;
  1266. return SDeio;
  1267. }
  1268. count -= n;
  1269. lba += n;
  1270. data += n * unit->secsize;
  1271. }
  1272. r->rlen = data - (uchar*)r->data;
  1273. r->status = SDok;
  1274. return SDok;
  1275. }
  1276. /*
  1277. * configure drives 0-5 as ahci sata (c.f. errata)
  1278. */
  1279. static int
  1280. iaahcimode(Pcidev *p)
  1281. {
  1282. dprint("iaahcimode %ux %ux %ux\n", pcicfgr8(p, 0x91),
  1283. pcicfgr8(p, 92), pcicfgr8(p, 93));
  1284. pcicfgw16(p, 0x92, pcicfgr32(p, 0x92) | 0xf); /* ports 0-3 */
  1285. // pcicfgw8(p, 0x93, pcicfgr32(p, 9x93) | 3); /* ports 4-5 */
  1286. return 0;
  1287. }
  1288. static void
  1289. iasetupahci(Ctlr *c)
  1290. {
  1291. /* disable cmd block decoding. */
  1292. pcicfgw16(c->pci, 0x40, pcicfgr16(c->pci, 0x40) & ~(1<<15));
  1293. pcicfgw16(c->pci, 0x42, pcicfgr16(c->pci, 0x42) & ~(1<<15));
  1294. c->lmmio[0x4/4] |= 1 << 31; /* enable ahci mode (ghc register) */
  1295. c->lmmio[0xc/4] = (1<<6) - 1; /* five ports (supposedly ro pi reg) */
  1296. /* enable ahci mode. */
  1297. // pcicfgw8(c->pci, 0x90, 0x40);
  1298. // pcicfgw16(c->pci, 0x90, 1<<6 | 1<<5); /* pedanticly proper for ich9 */
  1299. pcicfgw8(c->pci, 0x90, 1<<6 | 1<<5); /* pedanticly proper for ich9 */
  1300. }
  1301. static SDev*
  1302. iapnp(void)
  1303. {
  1304. int i, n, nunit;
  1305. ulong io;
  1306. Ctlr *c;
  1307. Drive *d;
  1308. Pcidev *p;
  1309. SDev *head, *tail, *s;
  1310. static int done;
  1311. if(done)
  1312. return nil;
  1313. done = 1;
  1314. p = nil;
  1315. head = tail = nil;
  1316. loop:
  1317. while((p = pcimatch(p, 0x8086, 0)) != nil){
  1318. if((p->did & 0xfffc) != 0x2680 && /* esb */
  1319. (p->did & 0xfffa) != 0x27c0) /* 82801g[bh]m */
  1320. continue;
  1321. if(niactlr == NCtlr){
  1322. print("iapnp: too many controllers\n");
  1323. break;
  1324. }
  1325. c = iactlr + niactlr;
  1326. s = sdevs + niactlr;
  1327. memset(c, 0, sizeof *c);
  1328. memset(s, 0, sizeof *s);
  1329. io = p->mem[Abar].bar & ~0xf;
  1330. if (io == 0)
  1331. continue;
  1332. c->mmio = (uchar*)upamalloc(io, p->mem[Abar].size, 0);
  1333. if(c->mmio == 0){
  1334. print("iapnp: address 0x%luX in use did=%x\n", io, p->did);
  1335. continue;
  1336. }
  1337. c->lmmio = (ulong*)c->mmio;
  1338. c->pci = p;
  1339. if(p->did != 0x2681)
  1340. iasetupahci(c);
  1341. nunit = ahciconf(c);
  1342. // ahcihbareset((Ahba*)c->mmio);
  1343. if(iaahcimode(p) == -1)
  1344. break;
  1345. if(nunit < 1){
  1346. // vunmap(c->mmio, p->mem[Abar].size);
  1347. continue;
  1348. }
  1349. niactlr++;
  1350. i = (c->hba->cap>>21) & 1;
  1351. print("intel 63[12]xesb: sata-%s ports with %d ports\n",
  1352. "I\0II" + i*2, nunit);
  1353. s->ifc = &sdiahciifc;
  1354. s->ctlr = c;
  1355. s->nunit = nunit;
  1356. s->idno = 'E';
  1357. c->sdev = s;
  1358. c->irq = p->intl;
  1359. c->tbdf = p->tbdf;
  1360. c->ndrive = nunit;
  1361. /* map the drives -- they don't all need to be enabled. */
  1362. memset(c->rawdrive, 0, sizeof c->rawdrive);
  1363. n = 0;
  1364. for(i = 0; i < NCtlrdrv; i++) {
  1365. d = c->rawdrive+i;
  1366. d->portno = i;
  1367. d->driveno = -1;
  1368. d->sectors = 0;
  1369. d->ctlr = c;
  1370. if((c->hba->pi & (1<<i)) == 0)
  1371. continue;
  1372. d->port = (Aport*)(c->mmio + 0x80*i + 0x100);
  1373. d->portc.p = d->port;
  1374. d->portc.m = &d->portm;
  1375. d->driveno = n++;
  1376. c->drive[i] = d;
  1377. iadrive[d->driveno] = d;
  1378. }
  1379. for(i = 0; i < n; i++)
  1380. if(ahciidle(c->drive[i]->port) == -1){
  1381. dprint("intel 63[12]xesb: port %d wedged; abort\n", i);
  1382. goto loop;
  1383. }
  1384. for(i = 0; i < n; i++){
  1385. c->drive[i]->mode = DMsatai;
  1386. configdrive(c->drive[i]);
  1387. }
  1388. niadrive += nunit;
  1389. if(head)
  1390. tail->next = s;
  1391. else
  1392. head = s;
  1393. tail = s;
  1394. }
  1395. return head;
  1396. }
  1397. static SDev*
  1398. iaid(SDev* sdev)
  1399. {
  1400. Ctlr *c;
  1401. int i;
  1402. for(; sdev; sdev = sdev->next){
  1403. if(sdev->ifc != &sdiahciifc)
  1404. continue;
  1405. c = sdev->ctlr;
  1406. for(i = 0; i < NCtlr; i++)
  1407. if(c == iactlr + i)
  1408. sdev->idno = 'E' + i;
  1409. }
  1410. return nil;
  1411. }
  1412. SDifc sdiahciifc = {
  1413. "iahci",
  1414. iapnp,
  1415. nil, /* legacy */
  1416. iaid,
  1417. iaenable,
  1418. iadisable,
  1419. iaverify,
  1420. iaonline,
  1421. iario,
  1422. nil,
  1423. nil,
  1424. scsibio,
  1425. };